JPS5647982A - Cash memory control system - Google Patents

Cash memory control system

Info

Publication number
JPS5647982A
JPS5647982A JP12393279A JP12393279A JPS5647982A JP S5647982 A JPS5647982 A JP S5647982A JP 12393279 A JP12393279 A JP 12393279A JP 12393279 A JP12393279 A JP 12393279A JP S5647982 A JPS5647982 A JP S5647982A
Authority
JP
Japan
Prior art keywords
memory
data
cash
signal
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12393279A
Other languages
Japanese (ja)
Inventor
Yasushi Fukunaga
Tadaaki Bando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12393279A priority Critical patent/JPS5647982A/en
Publication of JPS5647982A publication Critical patent/JPS5647982A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To hold the indentity of data between a main memory device and cash memory unit in a computer system by rewriting corresponding data in the cash memory as well in responce to a write-in request of a memory bus.
CONSTITUTION: Stack 28 monitors memory bus 7 and, when a write-in request to main memory device 1 is made, is supplied with the address information and data information and after data are inputted, signal 29 is sent to cash memory controller 21. Controller 21 sends the address and data from stack 28 to comparator 22, and memory parts 24 and 25 with selective signal 32. When comparator 22 obtains identity signal 37, controller 21 sends write-in signal 33 to memory part 25 to equalize data in cash memory 2 to those in main memory.
COPYRIGHT: (C)1981,JPO&Japio
JP12393279A 1979-09-28 1979-09-28 Cash memory control system Pending JPS5647982A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12393279A JPS5647982A (en) 1979-09-28 1979-09-28 Cash memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12393279A JPS5647982A (en) 1979-09-28 1979-09-28 Cash memory control system

Publications (1)

Publication Number Publication Date
JPS5647982A true JPS5647982A (en) 1981-04-30

Family

ID=14872911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12393279A Pending JPS5647982A (en) 1979-09-28 1979-09-28 Cash memory control system

Country Status (1)

Country Link
JP (1) JPS5647982A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5236431A (en) * 1975-09-17 1977-03-19 Toshiba Corp Cash memory control system
JPS5464944A (en) * 1977-11-02 1979-05-25 Fujitsu Ltd Buffer invalidating system for multi-cpu system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5236431A (en) * 1975-09-17 1977-03-19 Toshiba Corp Cash memory control system
JPS5464944A (en) * 1977-11-02 1979-05-25 Fujitsu Ltd Buffer invalidating system for multi-cpu system

Similar Documents

Publication Publication Date Title
EP0061324A3 (en) Computer memory management
KR890007173A (en) Address bus controller
GB1264167A (en)
JPS643739A (en) Information processor
KR880009306A (en) Direct memory access control unit
EP0323123A3 (en) A storage control system in a computer system
JPS5647982A (en) Cash memory control system
KR880008172A (en) Data processing system with bus commands for another subsystem generated by one subsystem
JPS5489455A (en) Control system
JPS54140841A (en) Memory control system of multiprocessor system
JPS5274240A (en) Lsi data processing system
JPS6478361A (en) Data processing system
ES2038928A2 (en) Access processing system in information processor
JPS5674738A (en) Transfer system of display data
JPS57114966A (en) Computer system
JPS57197661A (en) Multiplex controlling system for file memory
JPS5462743A (en) Communication control system
JPS6476132A (en) Inter-storage unit page data transfer control system
JPS54100628A (en) Memory-contention control system
JPS5622157A (en) Process system multiplexing system
JPS6426940A (en) Maintenance test system for shared device
JPS6476342A (en) Information processing system
JPS5733498A (en) Control system of main storage
JPS56121152A (en) Monitor system of computer program
JPS5724088A (en) Buffer memory control system