JPS5587463A - Integrated circuit package - Google Patents

Integrated circuit package

Info

Publication number
JPS5587463A
JPS5587463A JP16401978A JP16401978A JPS5587463A JP S5587463 A JPS5587463 A JP S5587463A JP 16401978 A JP16401978 A JP 16401978A JP 16401978 A JP16401978 A JP 16401978A JP S5587463 A JPS5587463 A JP S5587463A
Authority
JP
Japan
Prior art keywords
resistance
established
pattern
ceramic substrate
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16401978A
Other languages
Japanese (ja)
Other versions
JPS596064B2 (en
Inventor
Katsuhiko Suyama
Hirotsugu Kusakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16401978A priority Critical patent/JPS596064B2/en
Publication of JPS5587463A publication Critical patent/JPS5587463A/en
Publication of JPS596064B2 publication Critical patent/JPS596064B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain high-reliability package by forming a resistance of prearranged value on a ceramic substrate and earthing the said resistance. CONSTITUTION:Ceramic substrate is established on ceramic substrate 11 with square hole in the center of copal earthing plate 16. Then MoMn pattern is created on the said substrate surface with lead terminal bonded on the external edge. The entire conductive part excepting substrate 11 is plated with gold and the internal edge is provided as a sealing area. Cr resistance 17 is established at the tip ahead of a pad on lead terminal 13'. In addition, MoMn pattern 12'' is established at the tip as a sealing area with a resistance value set at approximately 50 ohms. IC chip 14 is soldered on the earthing plate 16, is wire-connected 18 to a pad area inside the patterns 12, 12' and then the pad area of pattern 12'' and earthing plate 16 are wire- connected 18. Under this constitution, if an input signal is connected to terminal 13', the reflection of an input signal pulse is absorbed by the resistance 17 as a terminal resistance. Therefore, faulty action is eliminated.
JP16401978A 1978-12-25 1978-12-25 integrated circuit package Expired JPS596064B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16401978A JPS596064B2 (en) 1978-12-25 1978-12-25 integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16401978A JPS596064B2 (en) 1978-12-25 1978-12-25 integrated circuit package

Publications (2)

Publication Number Publication Date
JPS5587463A true JPS5587463A (en) 1980-07-02
JPS596064B2 JPS596064B2 (en) 1984-02-08

Family

ID=15785235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16401978A Expired JPS596064B2 (en) 1978-12-25 1978-12-25 integrated circuit package

Country Status (1)

Country Link
JP (1) JPS596064B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59165438A (en) * 1983-03-09 1984-09-18 Fujitsu Ltd Semiconductor device
JPS63153846A (en) * 1986-12-17 1988-06-27 Nec Corp Semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2400587A1 (en) * 1977-08-19 1979-03-16 Allied Colloids Ltd IMPROVEMENTS TO THICKENERS OF SIEVE PRINTING PASTE FOR CARPETS

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59165438A (en) * 1983-03-09 1984-09-18 Fujitsu Ltd Semiconductor device
JPH0129066B2 (en) * 1983-03-09 1989-06-07 Fujitsu Ltd
JPS63153846A (en) * 1986-12-17 1988-06-27 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPS596064B2 (en) 1984-02-08

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