JPS5534396A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS5534396A
JPS5534396A JP11176779A JP11176779A JPS5534396A JP S5534396 A JPS5534396 A JP S5534396A JP 11176779 A JP11176779 A JP 11176779A JP 11176779 A JP11176779 A JP 11176779A JP S5534396 A JPS5534396 A JP S5534396A
Authority
JP
Japan
Prior art keywords
amplifier
complementary outputs
pair
semiconductor memory
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11176779A
Other languages
Japanese (ja)
Other versions
JPS601711B2 (en
Inventor
Kiyoo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP54111767A priority Critical patent/JPS601711B2/en
Publication of JPS5534396A publication Critical patent/JPS5534396A/en
Publication of JPS601711B2 publication Critical patent/JPS601711B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To obtain a high-speed and highly-stable LSI memory by enabling a pre-amplifier coupled with a pair of data lines to generate two complementary outputs and then by forming as a main amplifier a differential amplifier which has two inputs to receive the above-mentioned complementary outputs. CONSTITUTION:On a semiconductor memory cell composed of memory cells arranged in a matrix and word lines and data lines connecting respective memory cells, two complementary outputs of pre-amplifier PA0 coupled by a pair of data line D0 and bar D0 are differentially amplified again by differential main amplifier MA after passing through transistors Q and Q by applying address signal A0, the output of a decoder.
JP54111767A 1979-09-03 1979-09-03 semiconductor memory Expired JPS601711B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54111767A JPS601711B2 (en) 1979-09-03 1979-09-03 semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54111767A JPS601711B2 (en) 1979-09-03 1979-09-03 semiconductor memory

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP14805674A Division JPS5539073B2 (en) 1974-12-25 1974-12-25

Publications (2)

Publication Number Publication Date
JPS5534396A true JPS5534396A (en) 1980-03-10
JPS601711B2 JPS601711B2 (en) 1985-01-17

Family

ID=14569655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54111767A Expired JPS601711B2 (en) 1979-09-03 1979-09-03 semiconductor memory

Country Status (1)

Country Link
JP (1) JPS601711B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61206997A (en) * 1985-03-11 1986-09-13 Nec Ic Microcomput Syst Ltd Semiconductor memory device
US5237217A (en) * 1990-11-14 1993-08-17 Matsushita Electric Industrial Co., Ltd. Decoder circuit with a differential amplifier and applications thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61135808U (en) * 1985-02-14 1986-08-23

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61206997A (en) * 1985-03-11 1986-09-13 Nec Ic Microcomput Syst Ltd Semiconductor memory device
JPH0330955B2 (en) * 1985-03-11 1991-05-01 Nippon Denki Aishii Maikon Shisutemu Kk
US5237217A (en) * 1990-11-14 1993-08-17 Matsushita Electric Industrial Co., Ltd. Decoder circuit with a differential amplifier and applications thereof

Also Published As

Publication number Publication date
JPS601711B2 (en) 1985-01-17

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