JPS5534394A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS5534394A
JPS5534394A JP11176479A JP11176479A JPS5534394A JP S5534394 A JPS5534394 A JP S5534394A JP 11176479 A JP11176479 A JP 11176479A JP 11176479 A JP11176479 A JP 11176479A JP S5534394 A JPS5534394 A JP S5534394A
Authority
JP
Japan
Prior art keywords
bar
differential
read
cell
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11176479A
Other languages
Japanese (ja)
Other versions
JPS601710B2 (en
Inventor
Kiyoo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP54111764A priority Critical patent/JPS601710B2/en
Publication of JPS5534394A publication Critical patent/JPS5534394A/en
Publication of JPS601710B2 publication Critical patent/JPS601710B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To obtain a high-speed and highly-stable LSI memory by arranging memory cells alternately at intersections between two columns of two adjacent columns. CONSTITUTION:Data line D0 and bar D0 where a differential read signal appears are arranged closely in parallel and a memory cell is connected to either one of intersections between one of word lines W0 to W63, DW0, and DW1, and D0 and bar D0. When a certain memory cell, e.g. MC63, is read, dummy cell DM0 connected to line bar D0 where the cell is not connected is read at the same time, so that a differential voltage appearing accorss line D0 and bar D0 will be used effectively by preamplifier PA0. The differential signal smplified by amplifier PA0 passes through transistors Q0 and Q 0 by applying address signal A0, the output of an decoder, and is inputted to differential amplifier MA, where it is differentially amplified again.
JP54111764A 1979-09-03 1979-09-03 semiconductor memory Expired JPS601710B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54111764A JPS601710B2 (en) 1979-09-03 1979-09-03 semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54111764A JPS601710B2 (en) 1979-09-03 1979-09-03 semiconductor memory

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP14805674A Division JPS5539073B2 (en) 1974-12-25 1974-12-25

Publications (2)

Publication Number Publication Date
JPS5534394A true JPS5534394A (en) 1980-03-10
JPS601710B2 JPS601710B2 (en) 1985-01-17

Family

ID=14569584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54111764A Expired JPS601710B2 (en) 1979-09-03 1979-09-03 semiconductor memory

Country Status (1)

Country Link
JP (1) JPS601710B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59207087A (en) * 1983-05-07 1984-11-24 Nippon Telegr & Teleph Corp <Ntt> Semiconductor storage device
JPS61110459A (en) * 1984-11-02 1986-05-28 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory
US5237217A (en) * 1990-11-14 1993-08-17 Matsushita Electric Industrial Co., Ltd. Decoder circuit with a differential amplifier and applications thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59207087A (en) * 1983-05-07 1984-11-24 Nippon Telegr & Teleph Corp <Ntt> Semiconductor storage device
JPH0634353B2 (en) * 1983-05-07 1994-05-02 日本電信電話株式会社 Semiconductor memory device
JPS61110459A (en) * 1984-11-02 1986-05-28 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory
JPH0377668B2 (en) * 1984-11-02 1991-12-11 Nippon Telegraph & Telephone
US5237217A (en) * 1990-11-14 1993-08-17 Matsushita Electric Industrial Co., Ltd. Decoder circuit with a differential amplifier and applications thereof

Also Published As

Publication number Publication date
JPS601710B2 (en) 1985-01-17

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