JPS5461858A - Digital filter - Google Patents
Digital filterInfo
- Publication number
- JPS5461858A JPS5461858A JP12901477A JP12901477A JPS5461858A JP S5461858 A JPS5461858 A JP S5461858A JP 12901477 A JP12901477 A JP 12901477A JP 12901477 A JP12901477 A JP 12901477A JP S5461858 A JPS5461858 A JP S5461858A
- Authority
- JP
- Japan
- Prior art keywords
- equation
- circuit
- multipliers
- multiplier
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0223—Computation saving measures; Accelerating measures
- H03H17/0227—Measures concerning the coefficients
- H03H17/023—Measures concerning the coefficients reducing the wordlength, the possible values of coefficients
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/04—Recursive filters
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Theoretical Computer Science (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To reduce the arithmetic amount such as multiplication and addition, by shortening the length of a signal word by using a difference in signal as a new signal. CONSTITUTION:The digital filter circuit consists of delay circuits 4, and 71 to 73, adders 21 to 24, and 81 to 83, multipliers 31 to 35, etc. In this constitution, transfer function H(Z) expressed by equation (1) is calculated by the differentiating circuit composed of delay circuit 71 and adder 81, and Z expressed by equation (2) is by multiplier 34. Further, T expressed by (3) is determined by integrating circuit 10 composed of delay circuit 72 and adder 82. Here, the calculation of equation (1) is performed not only for multiplier 34 but also for other multipliers 31 to 35, and the calculation of equation of (3) is done for multiplier 35, and as to other multipliers 31 to 33, integrating circuit 11 is used which consists of delay circuit 73 and adder 83.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12901477A JPS5461858A (en) | 1977-10-26 | 1977-10-26 | Digital filter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12901477A JPS5461858A (en) | 1977-10-26 | 1977-10-26 | Digital filter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5461858A true JPS5461858A (en) | 1979-05-18 |
Family
ID=14999021
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12901477A Pending JPS5461858A (en) | 1977-10-26 | 1977-10-26 | Digital filter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5461858A (en) |
-
1977
- 1977-10-26 JP JP12901477A patent/JPS5461858A/en active Pending
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