JPS5672739A - High-speed multiplying circuit - Google Patents
High-speed multiplying circuitInfo
- Publication number
- JPS5672739A JPS5672739A JP14780079A JP14780079A JPS5672739A JP S5672739 A JPS5672739 A JP S5672739A JP 14780079 A JP14780079 A JP 14780079A JP 14780079 A JP14780079 A JP 14780079A JP S5672739 A JPS5672739 A JP S5672739A
- Authority
- JP
- Japan
- Prior art keywords
- multiplicand
- multiplier
- bytes
- register
- stored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To increase the speed of multiplication by shortening cycles of pipeline processing by reducing the hardware of a multiplying circuit by decreasing the number of adders while reducing the addition of partial products as much as possible and also by decreasing the frequency of the addition.
CONSTITUTION: Register 101 stored with a multiplier, register 102 stored with a multiplicand and selector SEL selecting the random number of bytes of the multiplier are provided and the multiplicand is multiplied by the output of selector SEL having selected the multiplier at multipliers MUL0WMUL6. At the time of the multiplication of those multipliers MUL0WMUL6, a set of partial products of a random byte of the multiplier and even-numbered bytes of the multiplicand is stored in register RA successively from the smallest byte number of the multiplicand. Further, a set of partial products of a random byte of the multiplier and odd- numbered bytes is also stored in register RB in sequency from the smallest number of bytes of the multiplicand. Then, the contents of registers RA and RB are added together by adder 201, so that while the number of adders is reduced, the partial products of a random bytes of the multiplier and all bytes of the multiplicand will be found.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14780079A JPS5672739A (en) | 1979-11-16 | 1979-11-16 | High-speed multiplying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14780079A JPS5672739A (en) | 1979-11-16 | 1979-11-16 | High-speed multiplying circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5672739A true JPS5672739A (en) | 1981-06-17 |
Family
ID=15438493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14780079A Pending JPS5672739A (en) | 1979-11-16 | 1979-11-16 | High-speed multiplying circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5672739A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5831449A (en) * | 1981-08-19 | 1983-02-24 | Toshiba Corp | Multiplier |
| JPS58129653A (en) * | 1982-01-29 | 1983-08-02 | Hitachi Ltd | Multiplication system |
| US4864529A (en) * | 1986-10-09 | 1989-09-05 | North American Philips Corporation | Fast multiplier architecture |
| KR100434391B1 (en) * | 2001-07-20 | 2004-06-04 | 학교법인대우학원 | The architecture and the method to process image data in real-time for DSP and Microprocessor |
-
1979
- 1979-11-16 JP JP14780079A patent/JPS5672739A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5831449A (en) * | 1981-08-19 | 1983-02-24 | Toshiba Corp | Multiplier |
| JPS58129653A (en) * | 1982-01-29 | 1983-08-02 | Hitachi Ltd | Multiplication system |
| JPS6226723B2 (en) * | 1982-01-29 | 1987-06-10 | Hitachi Ltd | |
| US4864529A (en) * | 1986-10-09 | 1989-09-05 | North American Philips Corporation | Fast multiplier architecture |
| KR100434391B1 (en) * | 2001-07-20 | 2004-06-04 | 학교법인대우학원 | The architecture and the method to process image data in real-time for DSP and Microprocessor |
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