JPS54132144A - Multiple process system - Google Patents
Multiple process systemInfo
- Publication number
- JPS54132144A JPS54132144A JP4001378A JP4001378A JPS54132144A JP S54132144 A JPS54132144 A JP S54132144A JP 4001378 A JP4001378 A JP 4001378A JP 4001378 A JP4001378 A JP 4001378A JP S54132144 A JPS54132144 A JP S54132144A
- Authority
- JP
- Japan
- Prior art keywords
- matrix
- input
- adder
- multipliers
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Advance Control (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE: To reduce the matrix process time through the arithmetic process by providing one unit of the adder and n-units of multipliers to the n × n matrix and then forming then forming the addition/multiplication unit in which the output of the adder becomes the input of the 1st multiplier.
CONSTITUTION: In the case of the 4 × 4 matrix, for instance, the addition/multiplication unit is formed with use of adder ADD plus multipliers M1WM4 in which the output of adder ADD is used as the input of multiplier M1, and the output data of the unit is used as the multipliers of M2WM4. The multiplicands of each multiplier are set simultaneously from memory MB via gate G1, and the augend is set to input terminal 0 of adder ADD of the addition/multiplication unit. Then the multiple process is given to terminal 10 with the multiple process start signal used as the input. The multiple process is repeated in 2 × 4 times to carry out both the progress and regress substitutions for the 4 × 4 matrix. As a result, the order of 42 can be reduced down to the order of 4 for the process time of the 4 × 4 matrix.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4001378A JPS54132144A (en) | 1978-04-05 | 1978-04-05 | Multiple process system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4001378A JPS54132144A (en) | 1978-04-05 | 1978-04-05 | Multiple process system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54132144A true JPS54132144A (en) | 1979-10-13 |
Family
ID=12569014
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4001378A Pending JPS54132144A (en) | 1978-04-05 | 1978-04-05 | Multiple process system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54132144A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003077150A1 (en) * | 2002-02-19 | 2003-09-18 | Matsushita Electric Industrial Co., Ltd. | Matrix calculation device |
WO2004079585A1 (en) * | 2003-03-07 | 2004-09-16 | Matsushita Electric Industrial Co., Ltd. | Matrix operating device |
-
1978
- 1978-04-05 JP JP4001378A patent/JPS54132144A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003077150A1 (en) * | 2002-02-19 | 2003-09-18 | Matsushita Electric Industrial Co., Ltd. | Matrix calculation device |
WO2004079585A1 (en) * | 2003-03-07 | 2004-09-16 | Matsushita Electric Industrial Co., Ltd. | Matrix operating device |
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