JPS57189249A - Operating circuit - Google Patents

Operating circuit

Info

Publication number
JPS57189249A
JPS57189249A JP56075136A JP7513681A JPS57189249A JP S57189249 A JPS57189249 A JP S57189249A JP 56075136 A JP56075136 A JP 56075136A JP 7513681 A JP7513681 A JP 7513681A JP S57189249 A JPS57189249 A JP S57189249A
Authority
JP
Japan
Prior art keywords
adder
subtractor
division
multiplication
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56075136A
Other languages
Japanese (ja)
Inventor
Tsukasa Kudo
Akira Fusaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56075136A priority Critical patent/JPS57189249A/en
Publication of JPS57189249A publication Critical patent/JPS57189249A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To reduce the operating time, by using a signal of difference at subtraction and making the division and the multiplication with the 3rd number of the quotinent at the same time, in the operation circuit making multiplication and division through the use of adder/subtractor. CONSTITUTION:Two addition/subtraction circuits are provided. The 1st circuit is used as a subtractor 6-1 for division, and an adder 6-2 of the 2nd adder/ subtractor is controlled with one bit every time the 1-bit of the quotinent is determined and the multiplication is made by this adder 6-2, allowing to make operation processing of (bdivided by c)Xa in a short time.
JP56075136A 1981-05-19 1981-05-19 Operating circuit Pending JPS57189249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56075136A JPS57189249A (en) 1981-05-19 1981-05-19 Operating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56075136A JPS57189249A (en) 1981-05-19 1981-05-19 Operating circuit

Publications (1)

Publication Number Publication Date
JPS57189249A true JPS57189249A (en) 1982-11-20

Family

ID=13567467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56075136A Pending JPS57189249A (en) 1981-05-19 1981-05-19 Operating circuit

Country Status (1)

Country Link
JP (1) JPS57189249A (en)

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