JPS5520508A - Processor for division - Google Patents

Processor for division

Info

Publication number
JPS5520508A
JPS5520508A JP7913678A JP7913678A JPS5520508A JP S5520508 A JPS5520508 A JP S5520508A JP 7913678 A JP7913678 A JP 7913678A JP 7913678 A JP7913678 A JP 7913678A JP S5520508 A JPS5520508 A JP S5520508A
Authority
JP
Japan
Prior art keywords
remainder
processing
processing section
multiplication
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7913678A
Other languages
Japanese (ja)
Inventor
Tetsunori Nishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP7913678A priority Critical patent/JPS5520508A/en
Publication of JPS5520508A publication Critical patent/JPS5520508A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To speed up the operation by performing the process only with the upper rank bits limited, in the unit in which division is made with the processing of multiplication for the approximate value Dt -1 which is a reciprocal of the divisor D.
CONSTITUTION: The X input corresponding to the value Q(j), Y input corresponding to the value dt and the remainder R(j) are inputted to the multiplication processing section 1, and the carry output C of the multiplication corresponding to the left side of equation (1) and the sum output S are respectively set to the registers 2 and 3. The upper rank bit of the outputs C and S is fed to the addition processing section 4 to obtain the step quotient Q (j+1). On the other hand, the remainder R(j+1) at that time is returned to the processing section 1 from the registers 2 and 3. The remainder processing section 6 repeats specified processing to obtain the final remainder at the remainder generator 9. The quotient generator 5 integrates the step quotients Q(O)... obtained every step. The processing speed can be increased by limiting the number of processing bits at the processing section 4.
COPYRIGHT: (C)1980,JPO&Japio
JP7913678A 1978-06-29 1978-06-29 Processor for division Pending JPS5520508A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7913678A JPS5520508A (en) 1978-06-29 1978-06-29 Processor for division

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7913678A JPS5520508A (en) 1978-06-29 1978-06-29 Processor for division

Publications (1)

Publication Number Publication Date
JPS5520508A true JPS5520508A (en) 1980-02-14

Family

ID=13681529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7913678A Pending JPS5520508A (en) 1978-06-29 1978-06-29 Processor for division

Country Status (1)

Country Link
JP (1) JPS5520508A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60164837A (en) * 1984-02-07 1985-08-27 Nec Corp Divider
JPH01266628A (en) * 1988-01-29 1989-10-24 Texas Instr Inc <Ti> Apparatus and method for calculating division
JPH02227726A (en) * 1989-01-13 1990-09-10 Internatl Business Mach Corp <Ibm> Apparatus and method for executing floating point division

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60164837A (en) * 1984-02-07 1985-08-27 Nec Corp Divider
JPH0368416B2 (en) * 1984-02-07 1991-10-28 Nippon Electric Co
JPH01266628A (en) * 1988-01-29 1989-10-24 Texas Instr Inc <Ti> Apparatus and method for calculating division
JPH02227726A (en) * 1989-01-13 1990-09-10 Internatl Business Mach Corp <Ibm> Apparatus and method for executing floating point division

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