JPS5622168A - Control system of array processor - Google Patents

Control system of array processor

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Publication number
JPS5622168A
JPS5622168A JP9796079A JP9796079A JPS5622168A JP S5622168 A JPS5622168 A JP S5622168A JP 9796079 A JP9796079 A JP 9796079A JP 9796079 A JP9796079 A JP 9796079A JP S5622168 A JPS5622168 A JP S5622168A
Authority
JP
Japan
Prior art keywords
register
mask bit
instruction
sent
process part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9796079A
Other languages
Japanese (ja)
Inventor
Masanori Mogi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9796079A priority Critical patent/JPS5622168A/en
Publication of JPS5622168A publication Critical patent/JPS5622168A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To increase the efficiency for a series of processes, by supplying the element of the vector register into the 1st arithmetic process part and writing the mask bit generated at the 1st airthmetic process part as well as supplying the mask bit to the 2nd arithmetic process part.
CONSTITUTION: For the COMPARE instruction, the elements are read sequentially out of vector register 5 which is designated by the 2nd and 3rd operand parts of the instruction to be supplied to adder 9. The mask bit produced at adder 9 is sent to mask register 6 designated by the instruction to be written there. This mask bit is then read and then set to reading register 8 in the next timing. With this timing the elements to be sent to multiplier 10 are set to register 8. After this, both the COMPARE instruction and the MULTIPLY instruction are executed simultaneously. The result of multiplication delivered from multiplier 10 is sent to writing register 3 along with the corresponding mask bit. In this case, the result of multiplication having the mask bit of 1 is not written into vector register 5.
COPYRIGHT: (C)1981,JPO&Japio
JP9796079A 1979-07-31 1979-07-31 Control system of array processor Pending JPS5622168A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9796079A JPS5622168A (en) 1979-07-31 1979-07-31 Control system of array processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9796079A JPS5622168A (en) 1979-07-31 1979-07-31 Control system of array processor

Publications (1)

Publication Number Publication Date
JPS5622168A true JPS5622168A (en) 1981-03-02

Family

ID=14206232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9796079A Pending JPS5622168A (en) 1979-07-31 1979-07-31 Control system of array processor

Country Status (1)

Country Link
JP (1) JPS5622168A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5962905A (en) * 1982-06-28 1984-04-10 ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Controller with microcomputer
US5000555A (en) * 1988-04-21 1991-03-19 Nikon Corporation Arrangement in operation switches of microscope

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5962905A (en) * 1982-06-28 1984-04-10 ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Controller with microcomputer
US5000555A (en) * 1988-04-21 1991-03-19 Nikon Corporation Arrangement in operation switches of microscope

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