JPH08242049A - Conductive paste for multilayer wiring board - Google Patents
Conductive paste for multilayer wiring boardInfo
- Publication number
- JPH08242049A JPH08242049A JP4375995A JP4375995A JPH08242049A JP H08242049 A JPH08242049 A JP H08242049A JP 4375995 A JP4375995 A JP 4375995A JP 4375995 A JP4375995 A JP 4375995A JP H08242049 A JPH08242049 A JP H08242049A
- Authority
- JP
- Japan
- Prior art keywords
- conductive paste
- substance
- conductor
- wiring board
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＬＳＩやＩＣなどの電
子部品を搭載して電子回路を構成する多層配線基板の製
造に用いられる導電性ペーストに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conductive paste used for manufacturing a multi-layer wiring board on which electronic parts such as LSI and IC are mounted to form an electronic circuit.
【０００２】[0002]
【従来の技術】近年、低温焼結のガラス・セラミック基
板が開発されたのに伴い、その導電体にＡｕ、Ａｇ、Ｃ
ｕおよびＰｄの少なくとも１種を用いることが可能とな
った。2. Description of the Related Art In recent years, with the development of low-temperature sintered glass-ceramic substrates, Au, Ag, and C have been added to the conductors.
It has become possible to use at least one of u and Pd.
【０００３】これらの金属は、従来のセラミック多層配
線基板に用いられてきたＷやＭｏ等に比べて導体抵抗お
よび溶融温度がともに低いので、安全性のよい設備を用
いて良質の多層配線基板を低コストで製造することがで
きる。Since these metals have lower conductor resistances and melting temperatures than W and Mo, which have been used in conventional ceramic multilayer wiring boards, a good quality multilayer wiring board can be obtained by using equipment with good safety. It can be manufactured at low cost.
【０００４】かかる多層配線基板の製造方法に、グリー
ンシート積層法と、厚膜印刷法とがある。前者は高積層
に適し、微細な配線パターンを形成することができる。
しかし、焼成時の基板収縮にばらつきが生じやすいの
で、製造歩留がよくないという欠点がある。一方、後者
は焼成時における基板の板面方向への収縮量が少ないの
で、多層配線基板を歩留まりよく製造することができ
る。しかし、配線パターンによる段差が基板の表面に生
じるので、高積層や微細な配線パターンの形成には適し
ない。As a method of manufacturing such a multilayer wiring board, there are a green sheet laminating method and a thick film printing method. The former is suitable for high stacking and can form a fine wiring pattern.
However, there is a drawback that the manufacturing yield is not good because the shrinkage of the substrate during firing tends to vary. On the other hand, the latter has a small amount of shrinkage in the plate surface direction of the substrate during firing, so that a multilayer wiring substrate can be manufactured with high yield. However, since a step due to the wiring pattern is generated on the surface of the substrate, it is not suitable for highly stacked layers or formation of a fine wiring pattern.
【０００５】多層配線基板の製造においては、多層配線
基板を構成する絶縁層にスルーホール（以下、ビア穴と
いう）が設けられ、このビア穴に充填される導電体（以
下、ビア導体という）の素材たる導電性ペーストの選択
が重要な課題となる。その理由は、導電性ペーストの焼
成・焼結時における収縮率が、絶縁層の素材たる低温焼
結ガラス・セラミック材の焼成・焼結時における収縮率
に近似していないと、焼成・焼結後のビア導体や、ビア
導体と絶縁層との間に内部ポアやクラックが発生するか
らである。そこで、許容される導体抵抗値の範囲内にお
いて前記導電性ペーストに電気絶縁性の収縮抑制材を添
加している。In the manufacture of a multilayer wiring board, a through hole (hereinafter referred to as a via hole) is provided in an insulating layer forming the multilayer wiring board, and a conductor (hereinafter referred to as a via conductor) filled in the via hole is formed. The selection of the conductive paste as the material is an important issue. The reason for this is that if the shrinkage rate of the conductive paste during firing / sintering does not approximate the shrinkage rate of the low-temperature sintered glass / ceramic material that is the material of the insulating layer during firing / sintering, This is because internal pores and cracks are generated between the subsequent via conductor and between the via conductor and the insulating layer. Therefore, an electrically insulating shrinkage suppressing material is added to the conductive paste within the range of the allowable conductor resistance value.
【０００６】この種の収縮抑制材には、低温焼結のガラ
ス・セラミック材の焼結温度では焼結しない（収縮しな
い）材料が用いられる。この収縮抑制材にＡｌ2 Ｏ3 を
用いた事例を図４に示す。ここで、曲線ａは低温焼結の
ガラス・セラミック材の収縮率特性を、曲線ｂは第１の
導電性ペーストの収縮率特性を、そして、曲線ｃは第２
の導電性ペーストの収縮率特性をそれぞれ示している。
第１の導電極性ペーストとは、無機材料に平均粒径５μ
ｍのＣｕ粉末のみを混入し組成のものを指し、第２の導
電性ペーストとは、無機材料に平均粒径５μｍのＣｕ粉
末と、平均粒径２μｍのＡｌ2 Ｏ3 粉末（ペースト組成
中２０重量％）とを混入した組成のものを指す。A material that does not sinter (does not shrink) at the sintering temperature of the low-temperature glass-ceramic material is used for this type of shrinkage suppressor. FIG. 4 shows an example of using Al 2 O 3 as the shrinkage suppressing material. Here, the curve a is the shrinkage characteristic of the low temperature sintered glass-ceramic material, the curve b is the shrinkage characteristic of the first conductive paste, and the curve c is the second.
The contraction rate characteristics of the conductive paste are shown.
The first conductive polar paste is an inorganic material with an average particle size of 5 μm.
The second conductive paste is a Cu powder having an average particle size of 5 μm and an Al 2 O 3 powder having an average particle size of 2 μm (20% in the paste composition). (% By weight) and the composition is mixed.
【０００７】第１の導電性ペースト（曲線ｂ）は、低温
焼結のガラス・セラミック材（曲線ａ）よりも高い収縮
率を示すのに対し、第２の導電性ペースト（曲線ｃ）
は、低温焼結のガラス・セラミック材（曲線ａ）に近似
した収縮率を示す。このため、第１の導電性ペーストを
用いて形成されたビア導体は図５の（ａ）に示すような
形状となり、第２の導電性ペーストを用いて形成された
ビア導体は図５の（ｂ）に示すような形状となる。すな
わち、図５の（ａ）においては、上側の絶縁層１のビア
穴２内に設けられた焼成処理後のビア導体３とビア穴２
との間にクラック４が発生しているのに対し、図５の
（ｂ）にはかかるクラックが存在しない。図中の５は下
側の絶縁層、６は配線用のライン状導体を示す。The first conductive paste (curve b) exhibits higher shrinkage than the low temperature sintered glass-ceramic material (curve a), while the second conductive paste (curve c).
Indicates a shrinkage rate similar to that of a low temperature sintered glass-ceramic material (curve a). Therefore, the via conductor formed by using the first conductive paste has a shape as shown in FIG. 5A, and the via conductor formed by using the second conductive paste is shown in FIG. The shape is as shown in b). That is, in FIG. 5A, the via conductor 3 and the via hole 2 which are provided in the via hole 2 of the upper insulating layer 1 after the firing treatment
While a crack 4 is generated between the cracks, the cracks do not exist in FIG. In the figure, 5 is a lower insulating layer, and 6 is a line-shaped conductor for wiring.
【０００８】このように、ビア導体３の素材たる導電性
ペーストの焼成温度における収縮率特性を、低温焼結ガ
ラス・セラミック材の焼結温度における収縮率特性に近
似させることによって、多層配線基板の焼結後における
クラックの発生を抑制でき、高湿度下においても信頼性
の高い多層配線基板を得ることができる。As described above, by approximating the shrinkage rate characteristic of the conductive paste, which is the material of the via conductor 3, at the firing temperature to the shrinkage rate characteristic of the low temperature sintered glass / ceramic material at the sintering temperature, the multilayer wiring board Generation of cracks after sintering can be suppressed, and a highly reliable multilayer wiring board can be obtained even under high humidity.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、ビア導
体用導電性ペーストの焼成温度における収縮率特性を、
低温焼結のガラス・セラミック材の焼成温度における収
縮率特性に近似させるべく、Ａｌ2 Ｏ3 などの電気絶縁
性の収縮抑制材を導電性ペーストに添加すると、ビア導
体の抵抗値が必要以上に大きくなるという課題があっ
た。However, the shrinkage rate characteristic of the conductive paste for via conductors at the firing temperature is
If an electrically insulating shrinkage suppressor such as Al 2 O 3 is added to the conductive paste in order to approximate the shrinkage rate characteristics of low-temperature sintered glass / ceramic materials at the firing temperature, the resistance value of the via conductor becomes unnecessarily high. There was a problem of getting bigger.
【００１０】したがって本発明の目的は、ビア導体の抵
抗値を低く抑えながら、内部ポアやクラックの発生を抑
制することのできる信頼性の高い多層配線基板用導電性
ペーストを提供することにある。Therefore, an object of the present invention is to provide a highly reliable conductive paste for a multilayer wiring board which can suppress the generation of internal pores and cracks while suppressing the resistance value of the via conductor to be low.
【００１１】[0011]
【課題を解決するための手段】本発明によると、上述し
た目的を達成するために、低温焼結のガラス・セラミッ
ク材からなる絶縁層のスルーホール内に充填されて導電
体を形成する導電性ペーストであって、金属からなる物
質Ａおよび導電性金属酸化物からなる物質Ｂを主成分と
し、物質Ａの焼結温度をＴ1 、物質Ｂの焼結温度を
Ｔ2 、ガラス・セラミック材の焼結温度をＴとすると
き、Ｔ1 ＜Ｔ＜Ｔ2 の関係を満たすことを特徴とする多
層配線基板用導電性ペーストが提供される。According to the present invention, in order to achieve the above-mentioned object, a conductive material which is filled in a through hole of an insulating layer made of a low temperature sintered glass-ceramic material to form a conductor. The paste is mainly composed of a substance A made of a metal and a substance B made of a conductive metal oxide, a sintering temperature of the substance A is T 1 , a sintering temperature of the substance B is T 2 , a glass-ceramic material Provided is a conductive paste for a multilayer wiring board, which satisfies a relationship of T 1 <T <T 2 when a sintering temperature is T.
【００１２】物質ＡがＣｕ、ＡｇおよびＡｇ−Ｐｄの少
なくとも１種からなり、物質ＢがＩｎ2 Ｏ3 およびＳｎ
Ｏの少なくとも１種またはその化合物からなる構成とな
すことができる。The substance A comprises at least one of Cu, Ag and Ag-Pd, and the substance B comprises In 2 O 3 and Sn.
It can be configured to include at least one O or a compound thereof.
【００１３】また、ペースト組成中に占める物質Ａが６
０〜８０重量％、物質Ｂが１０〜３０重量％、絶縁材料
としてのガラスが０〜１０重量％、有機材料が１０〜３
０重量％である構成となすことができる。Further, the substance A in the paste composition is 6
0-80% by weight, substance B 10-30% by weight, glass as an insulating material 0-10% by weight, organic material 10-3
The composition can be 0% by weight.
【００１４】[0014]
【作用】本発明においては、物質Ａが導電材料の役割を
果たすべく、ガラス・セラミック材の焼成時に焼結す
る。一方、物質Ｂは導電材料の役割を果たすが、焼結す
ることなくビア導体の収縮抑制作用をなす。つまり、物
質Ａとともに主成分となる物質Ｂが、導電材料にしてか
つ収縮抑制材を兼ねるという一人二役を果たし、それに
よって、ビア導体の抵抗値を従来よりも低く保持するこ
とができて、なおかつ、内部ポアやクラックの発生を抑
制することができる。In the present invention, the substance A is sintered during firing of the glass-ceramic material so that the substance A plays the role of a conductive material. On the other hand, the substance B plays the role of a conductive material, but acts to suppress the shrinkage of the via conductor without sintering. In other words, the substance B, which is the main component together with the substance A, serves both as a conductive material and also as a shrinkage suppressing material, whereby the resistance value of the via conductor can be kept lower than before, In addition, the generation of internal pores and cracks can be suppressed.
【００１５】[0015]
【実施例】つぎに、本発明の実施例を説明する。本実施
例での導電性ペーストは、物質Ａとして平均粒径３μｍ
のＡｇ粉末を７５重量％、物質Ｂとして平均粒径５μｍ
のＩｎ2 Ｏ3 粉末を１０重量％、平均粒径１．８μｍの
ガラス粉末を２重量％、バインダとしてエチルセルロー
ス樹脂を０．８重量％、そして、溶剤としてテルピネオ
ールを１２．２重量％含む。これらの原料を３本ロール
で混合・混練して、ビア導体用の導電性ペーストを調製
する。EXAMPLES Examples of the present invention will be described below. The conductive paste in this example has an average particle size of 3 μm as the substance A.
75% by weight of Ag powder, the average particle size of substance B is 5 μm
10% by weight of In 2 O 3 powder, 2% by weight of glass powder having an average particle size of 1.8 μm, 0.8% by weight of ethyl cellulose resin as a binder, and 12.2% by weight of terpineol as a solvent. These raw materials are mixed and kneaded with a three-roll to prepare a conductive paste for via conductors.
【００１６】一方、多層配線基板の絶縁層としてのガラ
ス・セラミックグリーンシート（以下、グリーンシート
と略称する）は、Ｂ2 Ｏ3 −ＳｉＯ2 −ＰｂＯガラス粉
末およびＡｌ2 Ｏ3 を重量比で４０対６０の割合で混合
した組成物（日本硝子社製ＭＬＳ−１０００）と、バイ
ンダとしてのポリビニルブチラールと、可塑剤としての
ブチルベンジルフタレートと、溶剤としてのトルエンと
を含む。これらの素材をよく混合してスラリーとなし、
ドクターブレード法を適用してフィルム上にグリーンシ
ートを形成する。On the other hand, a glass / ceramic green sheet (hereinafter, simply referred to as a green sheet) as an insulating layer of a multilayer wiring board comprises B 2 O 3 —SiO 2 —PbO glass powder and Al 2 O 3 in a weight ratio of 40. It contains a composition (MLS-1000 manufactured by Nippon Glass Co., Ltd.) mixed in a ratio of 60: polyvinyl butyral as a binder, butylbenzyl phthalate as a plasticizer, and toluene as a solvent. Mix these materials well to make a slurry,
A doctor blade method is applied to form a green sheet on the film.
【００１７】このグリーンシートのビア導体形成位置
に、パンチング加工を施してビア穴を形成したのち、こ
のグリーンシートの表面をメタルマスクで覆い、このメ
タルマスクを介してグリーンシートの表面上に前記導電
性ペーストを印刷する。メタルマスクはビア穴に対応し
た位置に開口を有しているので、スキージによって展延
された導電性ペーストの一部分がビア穴に充墳される。
このとき、グリーンシートの裏面側から焼結金属および
ろ紙を通じて真空吸引する。After punching is performed at the via conductor forming position of the green sheet to form a via hole, the surface of the green sheet is covered with a metal mask, and the conductive layer is formed on the surface of the green sheet through the metal mask. Print the sex paste. Since the metal mask has an opening at a position corresponding to the via hole, a part of the conductive paste spread by the squeegee is filled in the via hole.
At this time, vacuum suction is performed from the back surface side of the green sheet through the sintered metal and the filter paper.
【００１８】次いで、配線用のライン状導体をグリーン
シート上に設ける印刷処理を施したのち、複数のグリー
ンシートを積層して熱プレスで積層体となし、この積層
体を加熱炉内に納めて大気中でバインダを除去し、か
つ、焼成する。Next, after performing a printing process in which a line-shaped conductor for wiring is provided on the green sheet, a plurality of green sheets are laminated and formed into a laminated body by hot pressing, and the laminated body is placed in a heating furnace. Binder is removed in the air and firing is performed.
【００１９】このようにして作製された低温焼結ガラス
・セラミック多層配線基板のビア導体の抵抗値を測定し
たところ、２ｍΩ／１ビア導体であった。これは従来の
導電性ペーストを用いた場合の５ｍΩ／１ビア導体に比
べて格段に低い値である。そして、上述した実施例で作
製したビア導体用導電性ペーストは、図１の曲線ａに示
すような収縮率特性をもつ。曲線ｂはガラス・セラミッ
ク材の収縮率特性で、曲線ａは曲線ｂに近似したものと
なっている。When the resistance value of the via conductor of the low temperature sintered glass / ceramic multilayer wiring board thus produced was measured, it was 2 mΩ / 1 via conductor. This is a much lower value than the 5 mΩ / 1 via conductor when the conventional conductive paste is used. The conductive paste for via conductors manufactured in the above-mentioned examples has the shrinkage ratio characteristic as shown by the curve a in FIG. The curve b is the shrinkage ratio characteristic of the glass / ceramic material, and the curve a is similar to the curve b.
【００２０】ビア導体用導電性ペーストの物質Ａおよび
物質Ｂの添加量を種々変えて実験を重ねた。図１の曲線
ｃは物質Ａに平均粒径３μｍのＡｇ粉末を８５重量％、
物質Ｂに平均粒径５μｍのＩｎ2 Ｏ3 粉末を５重量％を
含ませた場合（比較例１）の収縮率特性である。また、
曲線ｄは物質Ａに平均粒径３μｍのＡｇ粉末Ａｇを５０
重量％、物質Ｂに平均粒径５μｍのＩｎ2 Ｏ3 を３５重
量％を含ませた場合（比較例２）の収縮率特性である。
そして、比較例１、２（曲線ｃ、ｄ）はいずれも、ガラ
ス・セラミック材の曲線ｂから離れたものとなってい
る。Experiments were repeated with various amounts of the substances A and B added to the conductive paste for via conductors. The curve c in FIG. 1 is the substance A containing 85% by weight of Ag powder having an average particle size of 3 μm,
This is the shrinkage ratio characteristic when the substance B contains 5% by weight of In 2 O 3 powder having an average particle size of 5 μm (Comparative Example 1). Also,
The curve d is the substance A containing 50 g of Ag powder Ag having an average particle size of 3 μm.
%, And the contraction rate characteristics when the substance B contains 35% by weight of In 2 O 3 having an average particle size of 5 μm (Comparative Example 2).
In addition, Comparative Examples 1 and 2 (curves c and d) are both separated from the curve b of the glass / ceramic material.
【００２１】図２の（ａ）に示すように、本発明の実施
例で形成されたビア導体７は、上側の絶縁層８に設けら
れたビア穴９内に安定に納まっており、上側の絶縁層８
と下側の絶縁層１０との間に設けられた配線用のライン
状導体１１に当接している。As shown in FIG. 2A, the via conductor 7 formed in the embodiment of the present invention is stably accommodated in the via hole 9 provided in the upper insulating layer 8, and the upper via conductor 9 is formed. Insulating layer 8
And a line-shaped conductor 11 for wiring provided between the lower insulating layer 10 and the lower insulating layer 10.
【００２２】一方、図２の（ｂ）に示すビア導体１２
は、比較例１の導電性ペーストを用いて形成されたもの
で、焼成によって生じたクラック１３がビア穴９との間
に存在する。また、図２の（ｃ）に示すビア導体１４
は、比較例２の導電性ペーストを用いて形成したもの
で、焼成時によって生じたクラック１５が存在する。On the other hand, the via conductor 12 shown in FIG.
Is formed using the conductive paste of Comparative Example 1, and cracks 13 caused by firing exist between the via holes 9. In addition, the via conductor 14 shown in FIG.
Is formed by using the conductive paste of Comparative Example 2, and has cracks 15 caused by firing.
【００２３】上述した実施例では、物質ＡにＡｇを用い
たが、好ましくは、Ｃｕ、ＡｇおよびＡｇ−Ｐｄの少な
くとも１種を用いることができる。また、物質ＢにはＩ
ｎ2Ｏ3 およびＳｎＯの少なくとも１種またはその化合
物を用いるのが望ましい。さらに、ペースト組成中に占
める物質Ａは６０〜８０重量％の範囲内に、そして、物
質Ｂは１０〜３０重量％の範囲内にそれぞれ納めること
が望ましい。In the above-mentioned embodiments, Ag is used as the substance A, but it is preferable to use at least one of Cu, Ag and Ag-Pd. Also, the substance B has I
It is desirable to use at least one of n 2 O 3 and SnO or a compound thereof. Further, it is desirable that the content of the substance A in the paste composition is 60 to 80% by weight, and the content of the substance B in the paste composition is 10 to 30% by weight.
【００２４】ビア穴内に導電性ペーストを充填したグリ
ーンシートの積層体を加熱炉内に納めて加熱し、バイン
ダを除去する処理工程および焼成する処理工程のプロフ
ァイルたる時間−温度分布特性を図３の（ａ）、（ｂ）
にそれぞれ例示する。FIG. 3 shows the time-temperature distribution characteristics, which are profiles of the processing steps of removing the binder by heating the green sheet laminated body in which the conductive paste is filled in the via holes in a heating furnace. (A), (b)
Examples of each are given below.
【００２５】[0025]
【発明の効果】以上のように本発明に係る導電性ペース
トは、とくに低温焼結のガラス・セラミック多層配線基
板のビア導体に用いることによって、その抵抗値を低く
抑えることができ、しかも、基板焼成後におけるビア導
体やその周辺部に内部ポアまたはクラックを発生させる
ことがなく、高湿度下にも耐える高い信頼性を得ること
ができる。As described above, when the conductive paste according to the present invention is used as a via conductor of a glass / ceramic multilayer wiring board which is sintered at a low temperature, the resistance value thereof can be suppressed to a low level, and the board is also reduced. No internal pores or cracks are generated in the via conductor and its peripheral portion after firing, and high reliability that can withstand high humidity can be obtained.
【図１】本発明の一実施例の導電性ペーストの収縮率特
性を他と比較する特性図。FIG. 1 is a characteristic diagram comparing a shrinkage rate characteristic of a conductive paste according to an embodiment of the present invention with others.
【図２】本発明の一実施例におけるビア導体の形状を他
と比較して示す断面図。FIG. 2 is a cross-sectional view showing a shape of a via conductor in one embodiment of the present invention in comparison with others.
【図３】本発明におけるビア導体および絶縁層の焼成処
理における温度特性図。FIG. 3 is a temperature characteristic diagram in a firing process of a via conductor and an insulating layer according to the present invention.
【図４】従来のビア導体用導電性ペーストの収縮率特性
を他と比較する特性図。FIG. 4 is a characteristic diagram comparing shrinkage ratio characteristics of a conventional conductive paste for via conductors with those of others.
【図５】従来のビア導体の形状を示す断面図。FIG. 5 is a cross-sectional view showing the shape of a conventional via conductor.
７ ビア導体 ８、１０ 絶縁層 ９ ビア穴 １１ ライン状導体 7 Via conductor 8, 10 Insulating layer 9 Via hole 11 Line-shaped conductor
フロントページの続き (72)発明者 熊谷 浩一 大阪府門真市大字門真1006番地 松下電器 産業株式会社内Front page continuation (72) Inventor Koichi Kumagai 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.
Claims (3)
る絶縁層のスルーホール内に充填されて導電体を形成す
る導電性ペーストであって、金属からなる物質Ａおよび
導電性金属酸化物からなる物質Ｂを主成分とし、物質Ａ
の焼結温度をＴ1 、物質Ｂの焼結温度をＴ2 、ガラス・
セラミック材の焼結温度をＴとするとき、Ｔ1 ＜Ｔ＜Ｔ
2 の関係を満たすことを特徴とする多層配線基板用導電
性ペースト。1. A conductive paste which is filled in a through hole of an insulating layer made of a low-temperature-sintered glass-ceramic material to form a conductor, and which comprises a substance A made of metal and a conductive metal oxide. Substance B as the main component, substance A
The sintering temperature of T 1 , the sintering temperature of the substance B is T 2 ,
When the sintering temperature of the ceramic material is T, T 1 <T <T
A conductive paste for a multilayer wiring board, which satisfies the relationship of 2 .
少なくとも１種からなり、物質ＢがＩｎ2 Ｏ3 およびＳ
ｎＯの少なくとも１種またはその化合物からなる請求項
１記載の多層配線基板用導電性ペースト。2. The substance A comprises at least one of Cu, Ag and Ag—Pd, and the substance B comprises In 2 O 3 and S.
The conductive paste for a multilayer wiring board according to claim 1, comprising at least one kind of nO or a compound thereof.
８０重量％、物質Ｂが１０〜３０重量％、絶縁材料とし
てのガラスが０〜１０重量％、有機材料が１０〜３０重
量％である請求項１記載の多層配線基板用導電性ペース
ト。3. The substance A contained in the paste composition is 60 to 60%.
The conductive paste for a multilayer wiring board according to claim 1, wherein 80 wt%, the substance B is 10 to 30 wt%, the glass as an insulating material is 0 to 10 wt%, and the organic material is 10 to 30 wt%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4375995A JPH08242049A (en) | 1995-03-03 | 1995-03-03 | Conductive paste for multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4375995A JPH08242049A (en) | 1995-03-03 | 1995-03-03 | Conductive paste for multilayer wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08242049A true JPH08242049A (en) | 1996-09-17 |
Family
ID=12672698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4375995A Pending JPH08242049A (en) | 1995-03-03 | 1995-03-03 | Conductive paste for multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08242049A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5436662B2 (en) * | 2010-03-31 | 2014-03-05 | 京セラ株式会社 | Mounting boards and devices |
-
1995
- 1995-03-03 JP JP4375995A patent/JPH08242049A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5436662B2 (en) * | 2010-03-31 | 2014-03-05 | 京セラ株式会社 | Mounting boards and devices |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0992983A (en) | Manufacture of ceramic multilayer board | |
| JP3331083B2 (en) | Low temperature firing ceramic circuit board | |
| US5655209A (en) | Multilayer ceramic substrates having internal capacitor, and process for producing same | |
| JP2002015939A (en) | Multilayered electronic component and its manufacturing method | |
| JP3351043B2 (en) | Method for manufacturing multilayer ceramic substrate | |
| JP3121822B2 (en) | Conductor paste and wiring board | |
| KR100227412B1 (en) | Conductive paste | |
| JPH06100377A (en) | Production of multilayer ceramic board | |
| US7186307B2 (en) | Method for manufacturing a ceramic multilayer circuit board | |
| JPH06237081A (en) | Manufacture of multilayer ceramic substrate | |
| JP4122612B2 (en) | Low temperature fired ceramic circuit board | |
| JPH08242049A (en) | Conductive paste for multilayer wiring board | |
| JPH0650703B2 (en) | Paste composition and method for manufacturing laminated ceramic capacitor | |
| JPH08242050A (en) | Conductive paste for wiring board, and manufacture of wiring board | |
| JPH08134388A (en) | Electrically conductive ink | |
| JP3222296B2 (en) | Conductive ink | |
| JP3934910B2 (en) | Circuit board | |
| JPH0544838B2 (en) | ||
| JPH0137878B2 (en) | ||
| JPH0521931A (en) | Manufacture of glass ceramic substrate | |
| JPH10341067A (en) | Inorganic multilayered substrate and conductor paste for via holes | |
| JPH07162152A (en) | Manufacture of multilayer ceramic board | |
| JPH1097949A (en) | Manufacture of laminated capacitor | |
| JPH08191177A (en) | Via conducting paste and its manufacture | |
| JPS61222198A (en) | Composite ceramic multilayer wiring board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040302 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20040629 |