JPH06237081A - Manufacture of multilayer ceramic substrate - Google Patents
Manufacture of multilayer ceramic substrateInfo
- Publication number
- JPH06237081A JPH06237081A JP2268493A JP2268493A JPH06237081A JP H06237081 A JPH06237081 A JP H06237081A JP 2268493 A JP2268493 A JP 2268493A JP 2268493 A JP2268493 A JP 2268493A JP H06237081 A JPH06237081 A JP H06237081A
- Authority
- JP
- Japan
- Prior art keywords
- glass
- conductor wiring
- conductor
- ceramic substrate
- multilayer ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体ＬＳＩ，チップ部
品などを搭載し、かつそれらを相互配線するための多層
セラミック基板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multi-layer ceramic substrate for mounting semiconductor LSIs, chip parts, etc. and interconnecting them.
【０００２】[0002]
【従来の技術】近年、低温焼結ガラス・セラミック多層
基板の開発によって、使用できる導体材料に、金、銀、
銅、パラジウムまたはそれらの混合物が用いられるよう
になった。これらの金属は従来使用されたタングステ
ン、モリブデンなどに比べ導体抵抗が低く、且つ使用で
きる設備も安全で低コストに製造できる。2. Description of the Related Art In recent years, with the development of a low temperature sintered glass / ceramic multilayer substrate, usable conductor materials include gold, silver,
Copper, palladium or mixtures thereof have come into use. These metals have lower conductor resistance than conventionally used tungsten, molybdenum, etc., and the equipment that can be used is safe and can be manufactured at low cost.
【０００３】一方これらの金属の内、貴金属である金、
銀、パラジウムは高価でかつ価格変動が大きいことか
ら、安価で価格変動の少ないＣu電極材料の使用が望ま
れている。On the other hand, of these metals, the precious metal gold,
Since silver and palladium are expensive and have large price fluctuations, it is desired to use Cu electrode materials which are inexpensive and whose price fluctuations are small.
【０００４】ここではそれらの低温焼結多層基板は代表
的な製造方法の一例を述べる。低温焼結多層基板の種類
には大きく分けて３種類の方法がある。Here, an example of a typical manufacturing method for these low-temperature sintered multilayer substrates will be described. There are roughly three types of methods for the low-temperature sintering multilayer substrate.
【０００５】まず、第１の方法には多層基板の内層導体
に銀を用い、配線パターンを形成した低温焼結基板のグ
リーンシートを所望の枚数積層し、空気中で焼成し、そ
の後、最上層に銀・パラジウムペーストを印刷、焼成し
て得られるものである。これは内部にインピーダンスの
小さい銀を用い、最上層に半田耐熱を有する銀・パラジ
ウムを使用するものである。First, in the first method, a desired number of green sheets of a low temperature sintered substrate having a wiring pattern formed by laminating silver as an inner layer conductor of a multilayer substrate are laminated and fired in air, and then the uppermost layer is formed. It is obtained by printing and firing silver / palladium paste on. This uses silver with low impedance inside and silver / palladium having solder heat resistance as the uppermost layer.
【０００６】第２の方法は、内層導体に前者と同様に銀
を用い、最上層に銅を用いる方法で、これは最上層配線
に銅を用いることで、前者の銀・パラジウムに比べ低い
インピーダンスのものが得られる。The second method is to use silver for the inner layer conductor as in the former case and copper for the uppermost layer. This method uses copper for the uppermost layer wiring, which has a lower impedance than the former silver / palladium. You can get
【０００７】最後に第３の方法として、内層および最上
層に銅を用いる方法がある。この方法には２通りの方法
があり、その１つは導体の出発原料にＣuペーストを用
いる方法で、Ｃuの融点以下の温度(850〜950℃程度)で
かつＣuが酸化されず導体ペースト中の有機成分が十分
燃焼するように酸素分圧を制御した窒素雰囲気中で焼成
を行なうものである。もう１つの方法は導体の出発原料
にＣuＯペーストを用いる方法が有る。Finally, the third method is to use copper for the inner layer and the uppermost layer. There are two methods of this method. One is a method of using Cu paste as a starting material of the conductor, which is a temperature below the melting point of Cu (about 850 to 950 ° C.) and Cu is not oxidized in the conductor paste. The firing is performed in a nitrogen atmosphere in which the oxygen partial pressure is controlled so that the organic component of (3) is sufficiently burned. Another method is to use CuO paste as the starting material for the conductor.
【０００８】この方法は、脱バインダ工程，還元工程，
焼成工程の３段階とする焼成方法で、炭素に対して充分
な酸素雰囲気でかつ内部の有機バインダを熱分解させる
に充分な温度で熱処理を行なう脱バインダ工程、ＣuＯ
をＣuに還元する還元工程、基板の焼結を行なう焼成工
程からなる。この方法では微妙な酸素分圧のコントロー
ルを必要とせず、焼成時の雰囲気制御が容易になり緻密
な焼結体が得られる。This method includes a binder removal step, a reduction step,
The binder removal step of performing heat treatment in a sufficient oxygen atmosphere with respect to carbon and at a temperature sufficient to thermally decompose the organic binder inside, CuO
Is reduced to Cu and a firing process is performed to sinter the substrate. This method does not require delicate control of the oxygen partial pressure, facilitates control of the atmosphere during firing, and provides a dense sintered body.
【０００９】[0009]
【発明が解決しようとする課題】通常、多層セラミック
基板は最上層配線上にＩＣやチップコンデンサー等のチ
ップ部品を半田付け等で実装して用いられる。そのた
め、チップ部品のが実装され最上層のパッド部は、特に
高い接着強度と半田濡れ性が要求される。一般に接着強
度を高めるために最上層の導体ペーストとして、ガラス
にＢｉ2Ｏ3，ＣuＯ，ＣdＯなどの金属酸化物を添加した
ペーストが用いられる。Generally, a multilayer ceramic substrate is used by mounting a chip component such as an IC or a chip capacitor on the uppermost wiring by soldering or the like. For this reason, the uppermost pad portion on which the chip components are mounted is required to have particularly high adhesive strength and solder wettability. Generally, a paste obtained by adding a metal oxide such as Bi 2 O 3 , CuO or CdO to glass is used as the uppermost conductor paste in order to enhance the adhesive strength.
【００１０】しかしながら、高い接着強度を得るために
ガラスを多く添加すると半田濡れ性、シート抵抗が著し
く悪くなる。一方、半田濡れ性を高めるためにガラス量
を少なくすると接着強度が低くなる等の障害があった。However, if a large amount of glass is added in order to obtain high adhesive strength, the solder wettability and the sheet resistance are significantly deteriorated. On the other hand, if the amount of glass is reduced in order to improve the solder wettability, there is a problem that the adhesive strength becomes low.
【００１１】本発明は上記の欠点を解消し、接着強度と
半田濡れ性が共に優れた多層セラミック基板の製造方法
を提供することを目的とする。It is an object of the present invention to solve the above-mentioned drawbacks and to provide a method for manufacturing a multilayer ceramic substrate having excellent adhesive strength and solder wettability.
【００１２】[0012]
【課題を解決するための手段】この目的を達成するため
本発明は、高い接着強度を得るにはガラスを多く必要と
し、高い半田濡れ性を得るにはガラスを少なくする必要
があることに着目し、最上層導体の基板との接合部には
ガラスが多く存在し、半田付けを施す導体表面は、わず
かなガラスしか存在しないことができるようにして接着
強度と半田濡れ性との両立を可能とする。そのため、本
発明は内部導体配線を有するガラス・セラミック積層体
表面に前記内部導体配線との接続のためのビアホールと
最上層導体配線パターンを有するガラス層を形成した
後、焼成することにより多層セラミック基板を製造する
ものである。In order to achieve this object, the present invention focuses on the fact that a large amount of glass is required to obtain high adhesive strength and a small amount of glass is required to obtain high solder wettability. However, there is a lot of glass at the joint of the uppermost conductor to the substrate, and the surface of the conductor to be soldered can have a small amount of glass so that both adhesive strength and solder wettability can be achieved. And Therefore, according to the present invention, a glass layer having a via hole for connection with the internal conductor wiring and a glass layer having an uppermost conductor wiring pattern is formed on the surface of the glass / ceramic laminate having the internal conductor wiring, and then the multilayer ceramic substrate is fired. Is manufactured.
【００１３】[0013]
【作用】本発明によれば、最上層導体との間にガラス層
を設けた構成にすることにより、焼成時にガラスが軟化
し、基板側と最上層導体側に浸漬するが、基板と最上層
導体との接合部はガラスが多く存在するので高い接着強
度が得られ、導体表面はガラスが少ないので高い半田濡
れ性が得られる。According to the present invention, the glass layer is provided between the uppermost conductor and the uppermost conductor, so that the glass softens during firing and is immersed in the substrate side and the uppermost conductor side. Since a large amount of glass is present in the joint portion with the conductor, high adhesive strength is obtained, and since the conductor surface is low in glass, high solder wettability is obtained.
【００１４】[0014]
【実施例】以下本発明の各実施例について、図面を参照
しながら説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１５】（実施例１）まず、基板材料のガラス・セ
ラミックは、ホウ珪酸鉛ガラス粉末にセラミック材料と
してのアルミナ粉体を50対50の重量比で混合した組成物
(日本電気硝子社製 ＭＬＳ−19)を用いた。このガラス
・セラミック粉体と有機バインダとしてポリビニルブチ
ラール、可塑剤としてジ−ｎ−ブチルフタレート、溶剤
としてトルエンとイソプロピルアルコールの混合液(30
対70重量比)を混合しスラリーとした。(Example 1) First, a glass ceramic of a substrate material is a composition obtained by mixing lead borosilicate glass powder with alumina powder as a ceramic material in a weight ratio of 50:50.
(MLS-19 manufactured by Nippon Electric Glass Co., Ltd.) was used. This glass / ceramic powder, polyvinyl butyral as an organic binder, di-n-butyl phthalate as a plasticizer, and a mixed solution of toluene and isopropyl alcohol as a solvent (30
(70 weight ratio) was mixed to form a slurry.
【００１６】このスラリーをドクターブレード法で有機
フィルム上にシート成形した。この時、造膜から乾燥、
打ち抜き、さらには必要に応じてビアホール加工を行う
各工程を連続的に行うシステムを使用した。このグリー
ンシートに銀ペーストを用いで導体パターンの形成およ
びビアホール埋め印刷をスクリーン印刷法によって行っ
た。This slurry was formed into a sheet on an organic film by the doctor blade method. At this time, drying from film formation,
A system was used in which each step of punching and, if necessary, processing a via hole was continuously performed. Conductive pattern formation and via hole filling printing were performed on this green sheet by using a silver paste by a screen printing method.
【００１７】導体ペーストは、Ａg粉末(平均粒径１μm)
に接着強度を得るためのガラスフリット(日本電気硝子
社製 ＧＡ−９ガラス粉末、平均粒径2.5μm)を５重量
％加えたものを無機成分とし、これに有機バインダであ
るエチルセルロースをターピネオールに溶かしたビヒク
ルを加えて、３段ロールにより適度な粘度になるように
混合したものを用いた。The conductor paste is Ag powder (average particle size 1 μm).
5% by weight of glass frit (GA-9 glass powder manufactured by Nippon Electric Glass Co., Ltd., average particle diameter 2.5 μm) for obtaining adhesive strength was added as an inorganic component, and ethyl cellulose as an organic binder was dissolved in terpineol. The vehicle was added and mixed by a three-stage roll so as to have an appropriate viscosity.
【００１８】なお、ビア埋め用のＡgペーストは更に無
機成分として前記ガラス・セラミック粉末を15重量％加
えたものを使用した。The Ag paste for filling vias was prepared by adding 15% by weight of the glass-ceramic powder as an inorganic component.
【００１９】この導体印刷を施したグリーンシートを所
定の枚数積み重ね、熱圧着して積層体を形成した。この
ときの熱圧着条件は、温度が80℃、圧力は200kg/cm2で
行った。A predetermined number of the green sheets printed with the conductor were stacked and thermocompression bonded to form a laminate. The thermocompression bonding conditions at this time were a temperature of 80 ° C. and a pressure of 200 kg / cm 2 .
【００２０】次にこの積層体の両面にガラスペーストを
スクリーン印刷法によって印刷し、内部導体との接続箇
所にはビアホールを設けた。乾燥後のガラス層の厚みを
測定したところ８μmであった。ガラスペーストは、平
均粒径２μmのガラス粉体(日本電気硝子社製 ＧＡ−９
ガラス粉末、ガラス軟化点430℃)にエチルセルロースを
ターピネオールに溶かしたビヒクルを加えて、３段ロー
ルにより適度な粘度になるように混合したものを用い
た。Next, a glass paste was printed on both surfaces of this laminate by a screen printing method, and via holes were provided at connection points with internal conductors. The thickness of the glass layer after drying was measured and found to be 8 μm. The glass paste is a glass powder having an average particle size of 2 μm (GA-9 manufactured by Nippon Electric Glass Co., Ltd.).
A vehicle in which ethyl cellulose was dissolved in terpineol was added to a glass powder and a glass softening point of 430 ° C., and the mixture was mixed by a three-stage roll so as to have an appropriate viscosity.
【００２１】次にこのガラス層上に銀・パラジウムペー
ストを用いて最上層導体配線パターンをスクリーン印刷
し、乾燥の後、空気中900℃で１時間焼成した。図１は
上記のようにして作製された多層セラミック基板の焼成
前の積層体の断面図を示し、図中、１はガラスセラミッ
ク層、２はガラス層、３は最上層導体配線、４は内部導
体配線、５はビア導体である。この図１に示すガラス層
２上に用いる銀・パラジュウムペーストは、Ａg／Ｐd比
を90／10とした粉体に金属酸化物としてＢｉＯ3，ＰdＯ
を１重量％添加し、これにエチルセルロースをターピネ
オールに溶かしてビヒクルを加えて、３段ロールにより
適度な粘度になるように混合したものを用いた。焼成後
得られた試料を評価した結果、接着強度、半田濡れ性と
もに良好であった。Next, the uppermost conductor wiring pattern was screen-printed on this glass layer using a silver / palladium paste, dried, and then baked in air at 900 ° C. for 1 hour. FIG. 1 shows a cross-sectional view of a laminated body of a multilayer ceramic substrate manufactured as described above before firing, in which 1 is a glass ceramic layer, 2 is a glass layer, 3 is the uppermost conductor wiring, and 4 is an internal layer. Conductor wirings 5 are via conductors. The silver / palladium paste used on the glass layer 2 shown in FIG. 1 is a powder having an Ag / Pd ratio of 90/10 and BiO 3 and PdO as metal oxides.
1% by weight was added, ethyl cellulose was dissolved in terpineol, a vehicle was added thereto, and the mixture was mixed by a three-stage roll so as to have an appropriate viscosity. As a result of evaluating the sample obtained after firing, both the adhesive strength and the solder wettability were good.
【００２２】（実施例２）基板材料用のグリーンシート
とガラス形成用のグリーンシートをそれぞれ次の方法で
作製した。基板材料用ガラス・セラミックグリーンシー
トは、実施例１と同様の組成のスラリーをドクターブレ
ード法で成形した後、ＣuＯペーストを用いて導体パタ
ーンの形成およびビアホール埋め印刷をスクリーン印刷
法によって行った。Example 2 A green sheet for a substrate material and a green sheet for forming a glass were produced by the following methods. For the glass / ceramic green sheet for substrate material, a slurry having the same composition as in Example 1 was formed by the doctor blade method, and then a conductor pattern was formed using CuO paste and via hole filling printing was performed by the screen printing method.
【００２３】導体ペーストは、ＣuＯ粉末(平均粒径３μ
m)に接着強度を得るためのガラスフリット(日本電気硝
子社製 ＬＳ−0803ガラス粉末、平均粒径2.5μm)を３
重量％加えたものを無機成分とし、これに有機バインダ
であるエチルセルロースをターピネオールに溶かしたビ
ヒクルを加えて、３段ロールにより適度な粘度になるよ
うに混合したものを用いた。The conductor paste is CuO powder (average particle size 3 μm).
3) glass frit (LS-0803 glass powder manufactured by Nippon Electric Glass Co., average particle size 2.5 μm) for obtaining adhesive strength
What was added by weight% was used as an inorganic component, and a vehicle in which ethyl cellulose as an organic binder was dissolved in terpineol was added thereto, and the mixture was mixed by a three-stage roll so as to have an appropriate viscosity.
【００２４】なお、ビア埋め用のＣuＯペーストは更に
無機成分として前記ガラス・セラミック粉末を15重量％
加えたものを使用した。The CuO paste for filling vias further contains 15% by weight of the above-mentioned glass-ceramic powder as an inorganic component.
The added one was used.
【００２５】ガラス形成用グリーンシートは、平均粒径
３μmのガラス粉体(日本電気硝子社製 ＧＡ−１ガラス
粉末、軟化点595℃)を用い、このガラス粉体と有機バイ
ンダとしてポリビニルブチラール、可塑性としてジ−ｎ
−ブチルフタレート、溶剤としてトルエンとイソプロピ
ルアルコールの混合液(30対70重量比)をドクターブレー
ド法で有機フィルム上にシート成形した後、内部導体と
の接続箇所にスルホール加工を施した。グリーンシート
の厚みは10μmであった。As the green sheet for forming glass, glass powder having an average particle diameter of 3 μm (GA-1 glass powder manufactured by Nippon Electric Glass Co., softening point 595 ° C.) was used, and this glass powder and polyvinyl butyral as an organic binder and plasticity were used. As J-n
-Butyl phthalate, a mixed solution of toluene and isopropyl alcohol as a solvent (30:70 weight ratio) was formed into a sheet on an organic film by a doctor blade method, and then a through hole was formed at a connection point with an internal conductor. The thickness of the green sheet was 10 μm.
【００２６】次にこれらのグリーンシートを積み重ね、
熱圧着して積層体を形成した。積層方法は、所定枚数の
ガラス・セラミック積層体の上下にガラスグリーンシー
トを５枚ずつ積層した。このときの熱圧着条件は、温度
が80℃、圧力は200kg/cm2で行った。Next, stack these green sheets,
The laminate was formed by thermocompression bonding. As a laminating method, five glass green sheets were laminated above and below a predetermined number of glass-ceramic laminated bodies. The thermocompression bonding conditions at this time were a temperature of 80 ° C. and a pressure of 200 kg / cm 2 .
【００２７】次に、この積層体の両面にはＣuＯペース
トを用いて、最上層導体配線パターンをスクリーン印刷
した。ＣuＯペーストは、平均粒径３μmのＣuＯ粉体に
ガラス(日本電気硝子社製 ＧＡ−９ガラス粉末、平均
粒径2.5μm)を加えたものを無機成分とし、これに有機
バインダであるエチルセルロースをターピネオールに溶
かしたビヒクルを加えて、３段ロールにより適度な粘度
になるように混合したものを用いた。Next, a CuO paste was used on both surfaces of this laminate to screen print the uppermost conductor wiring pattern. The CuO paste contains CuO powder having an average particle size of 3 μm and glass (GA-9 glass powder manufactured by Nippon Electric Glass Co., Ltd., an average particle size of 2.5 μm) as an inorganic component, and ethyl cellulose as an organic binder is terpineol. The vehicle dissolved in was added and mixed with a three-stage roll so as to have an appropriate viscosity.
【００２８】次に、焼成工程を説明する。まず最初は、
脱バインダ工程であり、グリーンシート、ＣuＯペース
トの有機バインダは、ＰＶＢ及びエチルセルロースであ
る。したがって空気中での分解温度は、500℃以上あれ
ば良いので、600℃の温度で行なった。その後、前記積
層体を水素ガス100％雰囲気中で200℃−５時間で還元し
た。この時のＣu層をＸ線回折により分析したところ100
％Ｃuであることを確認した。Next, the firing process will be described. First of all,
In the binder removal step, the organic binders of the green sheet and CuO paste are PVB and ethyl cellulose. Therefore, the decomposition temperature in air should be 500 ° C or higher, so 600 ° C was used. Then, the laminated body was reduced in an atmosphere of 100% hydrogen gas at 200 ° C. for 5 hours. When the Cu layer at this time was analyzed by X-ray diffraction, it was 100
It was confirmed to be% Cu.
【００２９】次にメッシュベルト炉を用いて純窒素中90
0℃で１時間焼成した。焼成後の基板の接着強度と半田
濡れ性は良好であった。Next, using a mesh belt furnace, 90 in pure nitrogen.
It was baked at 0 ° C. for 1 hour. The adhesive strength and solder wettability of the board after firing were good.
【００３０】（実施例３）基板材料用のグリーンシート
は実施例２の方法で作製した内部導体配線パターンを形
成したガラス・セラミックグリーンシートを用いた。ガ
ラス形成用グリーンシートは、平均粒径３μmのガラス
粉体(日本電気硝子社製 ＧＡ−11ガラス粉末 軟化点7
00℃)を用い、このガラス粉体と有機バインダとしてポ
リビニルブチラール、可塑剤としてジ−ｎ−ブチルフタ
レート、溶剤としてトルエンとイソプロピルアルコール
の混合液(30対70重量比)をドクターブレード法で有機フ
ィルム上にシート成形した後、内部導体との接続箇所に
スルホール加工を施した後、最上層導体配線パターンを
形成したものを用いた。最上層導体にはＣuＯ粉末にビ
ヒクルを加え混合したＣuＯペーストを用いた。(Example 3) As the green sheet for the substrate material, the glass / ceramic green sheet having the internal conductor wiring pattern formed by the method of Example 2 was used. The green sheet for glass formation is a glass powder having an average particle size of 3 μm (GA-11 glass powder manufactured by Nippon Electric Glass Co., Ltd., softening point 7
This glass powder, polyvinyl butyral as an organic binder, di-n-butyl phthalate as a plasticizer, and a mixed solution of toluene and isopropyl alcohol (30:70 weight ratio) as a solvent are used as an organic film by a doctor blade method. After forming a sheet on the top, through-hole processing was applied to the connection point with the internal conductor, and then the top conductor wiring pattern was formed. A CuO paste obtained by mixing a CuO powder with a vehicle was used as the uppermost conductor.
【００３１】次にこれらのグリーンシートを積み重ね、
熱圧着して積層体を形成した。積層方法は実施例２の方
法と同様、所定枚数のガラス・セラミック積層体の上下
にガラスグリーンシートを５枚ずつ積層した。熱圧着条
件は、温度が80℃、圧力は200kg/cm2で行った。この積
層体を実施例２の方法と同様に脱バインダ、還元の後、
純窒素中900℃で１時間メッシュベルト炉で焼成した。
焼成後得られた試料の接着強度、半田濡れ性ともに優れ
たものである。Next, stack these green sheets,
The laminate was formed by thermocompression bonding. The laminating method was the same as in the method of Example 2, and five glass green sheets were laminated above and below a predetermined number of glass-ceramic laminated bodies. The thermocompression bonding conditions were a temperature of 80 ° C. and a pressure of 200 kg / cm 2 . After removing the binder and reducing this laminate in the same manner as in Example 2,
It was fired in pure nitrogen at 900 ° C. for 1 hour in a mesh belt furnace.
The sample obtained after firing has excellent adhesive strength and solder wettability.
【００３２】[0032]
【発明の効果】以上説明したように本発明の多層セラミ
ック基板の製造方法によって作製された多層セラミック
基板は、ガラス・セラミック基板と最上層導体との界面
はガラスが多く存在し、これによって高い接着強度が得
られる。さらに導体表面はガラスがわずかしか存在しな
いので半田濡れ性が阻害されず、高い半田濡れ性が得ら
れる。As described above, in the multilayer ceramic substrate manufactured by the method for manufacturing a multilayer ceramic substrate of the present invention, a large amount of glass is present at the interface between the glass-ceramic substrate and the uppermost layer conductor, which results in high adhesion. Strength is obtained. Furthermore, since a small amount of glass is present on the surface of the conductor, the solder wettability is not hindered, and high solder wettability can be obtained.
【００３３】以上のように、多層セラミック基板のチッ
プ部品が実装されるパッド電極部の半田濡れ性と接着強
度の両立という課題を解決したものである。As described above, the problem of achieving both the solder wettability and the adhesive strength of the pad electrode portion on which the chip component of the multilayer ceramic substrate is mounted is solved.
【図１】本発明の実施例の多層セラミック基板の焼成前
の積層体の断面図である。FIG. 1 is a cross-sectional view of a laminated body of a multilayer ceramic substrate of an example of the present invention before firing.
１…ガラス・セラミック層、 ２…ガラス層、 ３…最
上層導体配線、 ４…内部導体配線、 ５…ビア導体。DESCRIPTION OF SYMBOLS 1 ... Glass / ceramic layer, 2 ... Glass layer, 3 ... Uppermost layer conductor wiring, 4 ... Internal conductor wiring, 5 ... Via conductor.
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/12 // Ｈ０５Ｋ 3/40 Ｋ 7511−4Ｅ 9355−4Ｍ Ｈ０１Ｌ 23/12 Ｆ (72)発明者 箱谷 靖彦 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 中村 嘉文 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 中谷 誠一 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 三浦 和裕 大阪府門真市大字門真1006番地 松下電器 産業株式会社内Continuation of front page (51) Int.Cl. 5 Identification number Office reference number FI technical display location H01L 23/12 // H05K 3/40 K 7511-4E 9355-4M H01L 23/12 F (72) Inventor's box Yasuhiko Tani 1006 Kadoma, Kadoma, Osaka Prefecture Matsuda Denki Sangyo Co., Ltd. (72) Inventor, Yoshifumi Nakamura Kadoma, Kadoma, Osaka Prefecture 1006 Kadoma Matsushita Electric Industrial Co., Ltd. (72) Seiichi Nakatani Kadoma, Kadoma City, Osaka 1006 At Matsushita Electric Industrial Co., Ltd. (72) Inventor Kazuhiro Miura Kadoma City, Osaka Prefecture 1006 At Matsushita Electric Industrial Co., Ltd.
Claims (6)
ーンを形成した少なくとも有機バインダ、可塑剤を含む
ガラス・セラミックよりなるグリーンシートを所望枚数
積層し、このグリーンシート積層体の両面もしくは片面
に、少なくとも有機バインダ、有機溶剤を含むガラスペ
ーストを前記内部導体配線との接続箇所にビアホールを
設けて印刷した後、導体ペースト組成物で最上層導体配
線パターンを印刷し、乾燥した後、焼成することを特徴
とする多層セラミック基板の製造方法。1. A desired number of green sheets made of glass / ceramic containing at least an organic binder and a plasticizer having an internal conductor wiring pattern formed of a conductor paste composition are laminated, and at least on both sides or one side of the green sheet laminate. A glass paste containing an organic binder and an organic solvent is printed by forming a via hole at a connection point with the internal conductor wiring, printing the uppermost conductor wiring pattern with a conductor paste composition, drying, and then firing. And a method for manufacturing a multilayer ceramic substrate.
ーンを形成した少なくとも有機バインダ、可塑剤を含む
ガラス・セラミックよりなるグリーンシートを所望枚数
積層し、このグリーンシート積層体の両面もしくは片面
に、前記内部導体配線との接続箇所にスルホール加工を
施した少なくとも有機バインダ、可塑剤を含むガラスよ
りなるグリーンシートを積層した後、導体ペースト組成
物で最上層導体配線パターンを印刷し、乾燥した後、焼
成することを特徴とする多層セラミック基板の製造方
法。2. A desired number of green sheets made of glass-ceramic containing at least an organic binder and a plasticizer having an internal conductor wiring pattern formed of a conductor paste composition are laminated, and the green sheet laminate is provided on both sides or one side of the green sheet laminate. After stacking a green sheet made of glass containing at least an organic binder and a plasticizer that has been subjected to through-hole processing at the connection point with the internal conductor wiring, the uppermost conductor wiring pattern is printed with a conductor paste composition, dried, and then baked. A method of manufacturing a multilayer ceramic substrate, comprising:
ーンを形成した少なくとも有機バインダ、可塑剤を含む
ガラス・セラミックよりなるグリーンシートを所望枚数
積層し、このグリーンシート積層体の両面もしくは片面
に、前記内部導体配線との接続のためのビアホールと最
上層導体配線パターンを形成した少なくとも有機バイン
ダ、可塑を含むガラスよりなるグリーンシートを積層し
た後、焼成することを特徴とする多層セラミック基板の
製造方法。3. A desired number of green sheets made of glass / ceramic containing at least an organic binder and a plasticizer in which an internal conductor wiring pattern is formed from a conductor paste composition are laminated, and the green sheet laminated body is provided on both sides or one side of the green sheet laminated body. A method for manufacturing a multilayer ceramic substrate, comprising laminating a green sheet made of glass containing at least an organic binder and plastic having a via hole for connection with an internal conductor wiring and an uppermost layer conductor wiring pattern, and then firing.
トのガラス軟化点が400℃から700℃の範囲であることを
特徴とする請求項１，２または３記載の多層セラミック
基板の製造方法。4. The method for producing a multilayer ceramic substrate according to claim 1, wherein the glass softening point of the glass paste and the glass green sheet is in the range of 400 ° C. to 700 ° C.
uＯのいずれかを主成分とすることを特徴とする請求項
１，２または３記載の多層セラミック基板の製造方法。5. The conductor paste is Ag, Ag / Pd, Cu, C.
4. The method of manufacturing a multilayer ceramic substrate according to claim 1, wherein the main component is any one of uO.
成することを特徴とする請求項１，２または３記載の多
層セラミック基板の製造方法。6. The method for manufacturing a multilayer ceramic substrate according to claim 1, wherein the firing temperature is 800 ° C. to 1000 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2268493A JPH06237081A (en) | 1993-02-10 | 1993-02-10 | Manufacture of multilayer ceramic substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2268493A JPH06237081A (en) | 1993-02-10 | 1993-02-10 | Manufacture of multilayer ceramic substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06237081A true JPH06237081A (en) | 1994-08-23 |
Family
ID=12089697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2268493A Pending JPH06237081A (en) | 1993-02-10 | 1993-02-10 | Manufacture of multilayer ceramic substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06237081A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005106973A1 (en) * | 2004-04-27 | 2005-11-10 | Kyocera Corporation | Wiring board for light emitting element |
| JP2006041230A (en) * | 2004-07-28 | 2006-02-09 | Kyocera Corp | Light emitting devices and wiring board therefor |
| JP2006066409A (en) * | 2004-07-28 | 2006-03-09 | Kyocera Corp | Wiring board for light emitting element, manufacturing method thereof and light emitting device |
| JP2006156447A (en) * | 2004-11-25 | 2006-06-15 | Kyocera Corp | Wiring board for light emitting element, light emitting device and its manufacturing method |
| EP1940210A2 (en) | 2006-12-26 | 2008-07-02 | TDK Corporation | Multilayer ceramics substrate |
| WO2013133827A1 (en) * | 2012-03-07 | 2013-09-12 | Intel Corporation | Glass clad microelectronic substrate |
| US9001520B2 (en) | 2012-09-24 | 2015-04-07 | Intel Corporation | Microelectronic structures having laminated or embedded glass routing structures for high density packaging |
| WO2016111281A1 (en) * | 2015-01-07 | 2016-07-14 | 株式会社村田製作所 | Ceramic board, electronic component, and ceramic-board manufacturing method |
| US9420707B2 (en) | 2009-12-17 | 2016-08-16 | Intel Corporation | Substrate for integrated circuit devices including multi-layer glass core and methods of making the same |
| US9686861B2 (en) | 2009-12-17 | 2017-06-20 | Intel Corporation | Glass core substrate for integrated circuit devices and methods of making the same |
-
1993
- 1993-02-10 JP JP2268493A patent/JPH06237081A/en active Pending
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005106973A1 (en) * | 2004-04-27 | 2005-11-10 | Kyocera Corporation | Wiring board for light emitting element |
| US8314346B2 (en) | 2004-04-27 | 2012-11-20 | Kyocera Corporation | Wiring board for light-emitting element |
| JP2006041230A (en) * | 2004-07-28 | 2006-02-09 | Kyocera Corp | Light emitting devices and wiring board therefor |
| JP2006066409A (en) * | 2004-07-28 | 2006-03-09 | Kyocera Corp | Wiring board for light emitting element, manufacturing method thereof and light emitting device |
| JP2006156447A (en) * | 2004-11-25 | 2006-06-15 | Kyocera Corp | Wiring board for light emitting element, light emitting device and its manufacturing method |
| EP1940210A2 (en) | 2006-12-26 | 2008-07-02 | TDK Corporation | Multilayer ceramics substrate |
| US7662477B2 (en) | 2006-12-26 | 2010-02-16 | Tdk Corporation | Multilayer ceramics substrate |
| US9420707B2 (en) | 2009-12-17 | 2016-08-16 | Intel Corporation | Substrate for integrated circuit devices including multi-layer glass core and methods of making the same |
| US9686861B2 (en) | 2009-12-17 | 2017-06-20 | Intel Corporation | Glass core substrate for integrated circuit devices and methods of making the same |
| US10070524B2 (en) | 2009-12-17 | 2018-09-04 | Intel Corporation | Method of making glass core substrate for integrated circuit devices |
| US9761514B2 (en) | 2009-12-17 | 2017-09-12 | Intel Corporation | Substrate for integrated circuit devices including multi-layer glass core and methods of making the same |
| US9793201B2 (en) | 2012-03-07 | 2017-10-17 | Intel Corporation | Glass clad microelectronic substrate |
| US9445496B2 (en) | 2012-03-07 | 2016-09-13 | Intel Corporation | Glass clad microelectronic substrate |
| WO2013133827A1 (en) * | 2012-03-07 | 2013-09-12 | Intel Corporation | Glass clad microelectronic substrate |
| US9642248B2 (en) | 2012-09-24 | 2017-05-02 | Intel Corporation | Microelectronic structures having laminated or embedded glass routing structures for high density packaging |
| US9001520B2 (en) | 2012-09-24 | 2015-04-07 | Intel Corporation | Microelectronic structures having laminated or embedded glass routing structures for high density packaging |
| US10008452B2 (en) | 2012-09-24 | 2018-06-26 | Intel Corporation | Microelectronic structures having laminated or embedded glass routing structures for high density packaging |
| CN107113985A (en) * | 2015-01-07 | 2017-08-29 | 株式会社村田制作所 | The manufacture method of ceramic substrate, electronic unit and ceramic substrate |
| JPWO2016111281A1 (en) * | 2015-01-07 | 2017-10-12 | 株式会社村田製作所 | Ceramic substrate, electronic component, and method for manufacturing ceramic substrate |
| WO2016111281A1 (en) * | 2015-01-07 | 2016-07-14 | 株式会社村田製作所 | Ceramic board, electronic component, and ceramic-board manufacturing method |
| US10405430B2 (en) | 2015-01-07 | 2019-09-03 | Murata Manufacturing Co., Ltd. | Ceramic substrate, electronic component, and method of manufacturing ceramic substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2785544B2 (en) | Method for manufacturing multilayer ceramic substrate | |
| JPH0728128B2 (en) | Ceramic multilayer wiring board and manufacturing method thereof | |
| JPH06237081A (en) | Manufacture of multilayer ceramic substrate | |
| JP3351043B2 (en) | Method for manufacturing multilayer ceramic substrate | |
| JP3003413B2 (en) | Method for manufacturing multilayer ceramic substrate | |
| JPH05327218A (en) | Manufacture of multilayer ceramic base | |
| JP2803414B2 (en) | Method for manufacturing multilayer ceramic substrate | |
| JP3082475B2 (en) | Method for manufacturing multilayer ceramic substrate | |
| JPH0730253A (en) | Method of manufacturing multilayer ceramic board | |
| JPH06223621A (en) | Conductor paste composition | |
| JP2803421B2 (en) | Method for manufacturing multilayer ceramic substrate | |
| JP3100796B2 (en) | Method for manufacturing multilayer ceramic substrate | |
| JPH05327220A (en) | Manufacture of multilayer ceramic base | |
| JP2812605B2 (en) | Method for manufacturing multilayer ceramic substrate | |
| JP2855959B2 (en) | Method for manufacturing multilayer ceramic substrate | |
| JP3222296B2 (en) | Conductive ink | |
| JP3197147B2 (en) | Method for manufacturing multilayer ceramic substrate | |
| JPH0588557B2 (en) | ||
| JPH08134388A (en) | Electrically conductive ink | |
| JPH05343851A (en) | Manufacture of multilayer ceramic substrate | |
| JPH05139849A (en) | Production of ceramic multilayer substrate | |
| JPS62145896A (en) | Manufacture of ceramic copper multilayer wiring board | |
| JPS6126293A (en) | Ceramic multilayer circuit board and method of producing same | |
| JPH0613756A (en) | Conductive paste composition | |
| JPH0321109B2 (en) |