JP2002015939A - Multilayered electronic component and its manufacturing method - Google Patents

Multilayered electronic component and its manufacturing method

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Publication number
JP2002015939A
JP2002015939A JP2000199127A JP2000199127A JP2002015939A JP 2002015939 A JP2002015939 A JP 2002015939A JP 2000199127 A JP2000199127 A JP 2000199127A JP 2000199127 A JP2000199127 A JP 2000199127A JP 2002015939 A JP2002015939 A JP 2002015939A
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JP
Japan
Prior art keywords
electronic component
internal electrode
coating layer
layer
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000199127A
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Japanese (ja)
Other versions
JP4573956B2 (en
Inventor
Shinichi Osawa
真一 大沢
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Kyocera Corp
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Kyocera Corp
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Priority to JP2000199127A priority Critical patent/JP4573956B2/en
Publication of JP2002015939A publication Critical patent/JP2002015939A/en
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Publication of JP4573956B2 publication Critical patent/JP4573956B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered electronic component whose capacitance is improved, whose variation is reduced and which exhibits a high connecting strength between inner electrode layers and outer electrodes, and to provide a method of its manufacturing. SOLUTION: With respect to the multilayered electronic component, which is made by forming a pair of outer electrodes to which internal electrode layers are alternately connected at ends of an electronic component body in which dielectrical layers and inner electrode layers are alternately laminated, a coring layer 7 is provided between the electronic component body 1 and the pair of outer electrodes 3 and through-holes 4 are provided in the coating layer 7 for electrically connecting the inner electrode layers 11 and the outer electrodes 3 to the coating layer 7.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、積層型電子部品お
よびその製法に関し、特に、積層セラミックコンデンサ
に用いられる積層型電子部品およびその製法に関する。The present invention relates to a multilayer electronic component and a method of manufacturing the same, and more particularly, to a multilayer electronic component used for a multilayer ceramic capacitor and a method of manufacturing the same.

【０００２】[0002]

【従来技術】近年、電子機器の小型化、高密度化に伴
い、積層型電子部品、例えば、積層セラミックコンデン
サは、小型、高容量、および、その容量バラツキの低減
が求められており、このため、誘電体層の薄層化と積
層数の増加、内部電極層の有効面積の大面積化、内
部電極層と外部電極との接合の強化が図られている。2. Description of the Related Art In recent years, as electronic devices have become smaller and higher in density, multilayer electronic components, for example, multilayer ceramic capacitors, have been required to be smaller in size, have higher capacitance, and have reduced capacitance variations. In addition, the thickness of the dielectric layer is reduced and the number of layers is increased, the effective area of the internal electrode layer is increased, and the bonding between the internal electrode layer and the external electrode is strengthened.

【０００３】このような積層セラミックコンデンサとし
ては、内部電極層と外部電極との接合部に関し、例え
ば、特開平３−９１２１７号公報に開示されるようなも
のが知られている。この公報に開示された積層セラミッ
クコンデンサでは、誘電体セラミックグリーンシート上
に内部電極パターンを形成し、内部電極パターンが形成
されたグリーンシートを複数積層して得られた積層成形
体を所望の大きさのチップに切断後、該チップ状成形体
の両端部に露出した内部電極パターンについて、先ず、
一方のチップ状成形体の端面部に露出した一方の内部電
極パターンの端部を一層置きにスパッタリング等によっ
て絶縁処理を行い、他方の端面部に露出した内部電極パ
ターンの端部は、短絡を避けるため、前記絶縁処理を行
わなかった内部電極パターンの端部を一層置きにスパッ
タリング等によって絶縁処理を行った後に焼成し、その
後、両端部に外部電極を設けることにより、内部電極層
の端部を一層置きにずらして積層して作製する従来の積
層セラミックコンデンサよりも、従来通りの積層数で大
きな静電容量を得ることができる。[0003] As such a multilayer ceramic capacitor, there has been known, for example, one disclosed in Japanese Patent Application Laid-Open No. 3-91217, which relates to a joint between an internal electrode layer and an external electrode. In the multilayer ceramic capacitor disclosed in this publication, an internal electrode pattern is formed on a dielectric ceramic green sheet, and a multilayer molded body obtained by laminating a plurality of green sheets on which the internal electrode pattern is formed has a desired size. After cutting into chips, the internal electrode patterns exposed at both ends of the chip-shaped molded body
One end of the one internal electrode pattern exposed on the end face of one chip-shaped molded body is subjected to insulation treatment by sputtering or the like, and the other end of the internal electrode pattern exposed on the other end face is short-circuited. Therefore, after performing the insulation treatment by sputtering or the like on the other end of the internal electrode pattern that has not been subjected to the insulation treatment, baking, and then providing external electrodes at both ends, the end of the internal electrode layer, A larger capacitance can be obtained with a conventional number of layers than a conventional multilayer ceramic capacitor manufactured by stacking the layers by shifting each other.

【０００４】あるいは、特開平４−１７００１６号公報
に開示されているように、内部電極層を有する積層セラ
ミック焼結体を酸化雰囲気中で加熱することにより、内
部電極層の両側縁近傍部分を絶縁体化した後、前記内部
電極層と電気的に接続される外部電極を形成することに
よって、積層セラミックコンデンサのサイドマージン領
域の幅を狭くし、小型・大容量化を果たすことができ
る。[0004] Alternatively, as disclosed in Japanese Patent Application Laid-Open No. 4-170016, by heating a multilayer ceramic sintered body having an internal electrode layer in an oxidizing atmosphere, portions near both side edges of the internal electrode layer are insulated. By forming external electrodes that are electrically connected to the internal electrode layers after the integration, the width of the side margin region of the multilayer ceramic capacitor can be reduced, and the size and the capacitance can be increased.

【０００５】[0005]

【発明が解決しようとする課題】近年、積層セラミック
コンデンサは、小型、高容量化のため、誘電体層および
内部電極層の薄層化が行われており、例えば、誘電体層
の厚みを５μｍ以下とした積層セラミックコンデンサも
開発されている。In recent years, in order to reduce the size and increase the capacity of multilayer ceramic capacitors, the thickness of dielectric layers and internal electrode layers has been reduced. For example, the thickness of the dielectric layers has been reduced to 5 μm. The following multilayer ceramic capacitors have also been developed.

【０００６】しかしながら、上記特開平３−９１２１７
号公報に開示された積層セラミックコンデンサでは、露
出した内部電極層の端面部のみを絶縁処理しており、絶
縁膜の接合面積が小さいため、絶縁処理部分の欠損や欠
落が発生し易くなり、ショート故障に至ること、また、
両端部に露出した内部電極の絶縁処理において微小なマ
スキングが必要となるため、絶縁処理方法として、例え
ば、スパッタ法や蒸着法などコストの高い手法に限られ
るいう問題があった。[0006] However, Japanese Patent Laid-Open Publication No.
In the monolithic ceramic capacitor disclosed in Japanese Patent Application Laid-Open No. H10-157, only the exposed end faces of the internal electrode layers are insulated, and since the bonding area of the insulating film is small, the insulation-treated portion is liable to be chipped or chipped. Leading to failure,
Since minute masking is required in the insulation treatment of the internal electrodes exposed at both ends, there has been a problem that the insulation treatment method is limited to a high-cost method such as a sputtering method or a vapor deposition method.

【０００７】また、露出した内部電極層を酸化処理して
絶縁体化する特開平４−１７００１６号公報では、内部
電極層が金属粉末を焼結したものであるから、粒界や気
孔が存在するため、金属組織的に不均質であり、加熱に
よる酸化処理では、酸化する領域が不均質となり、積層
セラミックコンデンサの静電容量がばらつきやすくなる
という問題があった。In Japanese Patent Application Laid-Open No. 4-170016, in which an exposed internal electrode layer is oxidized to be an insulator, the internal electrode layer is formed by sintering a metal powder, so that grain boundaries and pores are present. Therefore, there is a problem that the metallographic structure is heterogeneous, and the oxidation treatment by heating makes the oxidized region non-uniform, and the capacitance of the multilayer ceramic capacitor tends to vary.

【０００８】従って、本発明は、静電容量の向上とばら
つきの低減を図ると同時に、内部電極層と外部電極との
接続強度の高い積層型電子部品およびその製法を提供す
ることを目的とする。Accordingly, it is an object of the present invention to provide a laminated electronic component having a high connection strength between an internal electrode layer and an external electrode while improving the capacitance and reducing the variation, and a method of manufacturing the same. .

【０００９】[0009]

【課題を解決するための手段】本発明の積層型電子部品
は、誘電体層と内部電極層とが交互に積層された電子部
品本体の端面に、前記内部電極層が交互に接続される一
対の外部電極を形成してなる積層型電子部品において、
前記電子部品本体と、一対の外部電極との間に被覆層を
配設するとともに、該被覆層に前記内部電極層と外部電
極とを電気的に接続するための貫通孔を設けたことを特
徴とするものである。According to a first aspect of the present invention, there is provided a laminated electronic component comprising a pair of internal electrode layers alternately connected to an end face of an electronic component main body in which dielectric layers and internal electrode layers are alternately laminated. In the multilayer electronic component formed by forming the external electrodes of
A coating layer is provided between the electronic component body and a pair of external electrodes, and a through hole for electrically connecting the internal electrode layer and the external electrode is provided in the coating layer. It is assumed that.

【００１０】このような構成によれば、被覆層の厚みを
薄くすることにより、内部電極層と外部電極との間を絶
縁するための距離を最小にでき、内部電極層の有効面積
を大きくすることができ、静電容量を大きくすることが
できる。According to such a configuration, by reducing the thickness of the coating layer, the distance for insulating between the internal electrode layer and the external electrode can be minimized, and the effective area of the internal electrode layer is increased. And the capacitance can be increased.

【００１１】また、誘電体層の間に形成される内部電極
層の面積は、誘電体層とほぼ同じ面積であるため、静電
容量のばらつきが殆ど無く、電子部品本体の場所による
厚み差が生じることが無いために厚み差に起因する内部
応力からデラミネーションが発生することを防止でき
る。Further, since the area of the internal electrode layer formed between the dielectric layers is substantially the same as the area of the dielectric layer, there is almost no variation in capacitance, and the thickness difference due to the location of the electronic component body is small. Since it does not occur, it is possible to prevent the occurrence of delamination from the internal stress caused by the thickness difference.

【００１２】また、内部電極層の端部を交互に絶縁処理
して外部電極を形成した従来の場合に比較して、被覆層
が電子部品本体の端面の全面に被覆されているために、
被覆層と、誘電体層あるいは内部電極層の端部との接着
強度を高めることができ、電子部品本体と被覆層との接
続強度を向上できる。In addition, as compared with the conventional case in which the external electrodes are formed by alternately insulating the ends of the internal electrode layers, the coating layer covers the entire end surface of the electronic component body.
The adhesive strength between the coating layer and the end of the dielectric layer or the internal electrode layer can be increased, and the connection strength between the electronic component body and the coating layer can be improved.

【００１３】上記積層型電子部品は、被覆層の厚さが５
０μｍ以下であることが望ましい。５０μｍ以下であれ
ば、被覆層に形成される貫通孔に充填して接続される外
部電極と内部電極層との接続性を高め、且つ、積層型電
子部品の小型、高容量化に対して、静電容量の体積効率
を高めることができる。In the above-mentioned laminated electronic component, the thickness of the coating layer is 5
It is desirable that the thickness be 0 μm or less. When the thickness is 50 μm or less, the connectivity between the external electrode and the internal electrode layer which are filled and connected to the through holes formed in the coating layer is enhanced, and the size and capacity of the multilayer electronic component are reduced. The volumetric efficiency of the capacitance can be increased.

【００１４】上記積層型電子部品では、被覆層には、同
一の内部電極層が露出する貫通孔が、複数形成されてい
ることが望ましい。例えば、電子部品本体の端面におい
て、1層の内部電極上に、被覆層が残るように、複数の
貫通孔を形成することにより、被覆層と電子部品本体と
の接着面積を大きくでき、接合強度を高めることができ
る。In the above-mentioned multilayer electronic component, it is preferable that a plurality of through holes exposing the same internal electrode layer are formed in the coating layer. For example, by forming a plurality of through-holes on the end surface of the electronic component body so that the coating layer remains on one layer of the internal electrode, the bonding area between the coating layer and the electronic component body can be increased, and the bonding strength can be increased. Can be increased.

【００１５】上記積層型電子部品では、電子部品本体の
同一端面に複数の外部電極を設けることが望ましい。例
えば、積層セラミックコンデンサの一つの端面に、内部
電極層に交互に接続される一対の複数の外部電極を近接
して形成することにより、電流経路の対称性が増すため
に、高周波におけるインピーダンスを下げることがで
き、さらに、前記コンデンサ内に流れる電流を分散でき
ることから、コンデンサの電磁界分布を均一化し、自己
インダクタンスを低くすることができる。In the multilayer electronic component, it is desirable to provide a plurality of external electrodes on the same end surface of the electronic component body. For example, a pair of external electrodes alternately connected to the internal electrode layer are formed close to one end face of the multilayer ceramic capacitor, thereby increasing the symmetry of the current path, thereby lowering the impedance at high frequencies. Further, since the current flowing in the capacitor can be dispersed, the electromagnetic field distribution of the capacitor can be made uniform and the self-inductance can be reduced.

【００１６】本発明の積層型電子部品の製法は、誘電体
グリーンシートと内部電極パターンとを交互に積層し、
内部電極パターンの端部が端面に導出する電子部品本体
成形体を作製するとともに、該電子部品本体成形体の少
なくとも端面にセラミックペーストを塗布して被覆層成
形体を作製する工程と、前記電子部品本体成形体及び被
覆層成形体を焼成し、少なくとも端面に被覆層が被着さ
れている誘電体層と内部電極層とが交互に積層されてな
る電子部品本体を作製する工程と、前記被覆層に内部電
極層の端部が交互に露出するように複数個の貫通孔を形
成する工程と、前記被覆層表面および貫通孔内に外部電
極ペーストを塗布充填するとともに焼き付け内部電極層
が交互に接続している一対の外部電極を作製する工程と
を具備する製法である。In the method of manufacturing a laminated electronic component according to the present invention, dielectric green sheets and internal electrode patterns are alternately laminated,
A step of producing a molded body of the electronic component in which the end of the internal electrode pattern is led out to the end face, and applying a ceramic paste to at least the end face of the molded body of the electronic part to produce a coating layer molded article; A step of firing the main body molded body and the coating layer molded body to produce an electronic component main body in which dielectric layers and internal electrode layers each having at least an end face with a coating layer are alternately laminated; Forming a plurality of through-holes such that the ends of the internal electrode layers are alternately exposed, and applying and filling an external electrode paste on the surface of the coating layer and in the through-holes and alternately connecting the baked internal electrode layers. Manufacturing a pair of external electrodes.

【００１７】この製法においては、内部電極パターンの
形状、形成位置を制御する必要がないために、積層型電
子部品を容易に作製できる。In this manufacturing method, it is not necessary to control the shape and position of the internal electrode pattern, so that a multilayer electronic component can be easily manufactured.

【００１８】また、被覆層が形成された電子部品本体の
端面に貫通孔を形成することから、例えば、電子部品本
体の端面に露出した内部電極層にマスキングなどを行っ
て絶縁部を形成する従来の場合に比較して、電子部品本
体の端面に、被覆層を一体化して強固な被覆層を形成で
きるため、高信頼性の積層型電子部品を作製することが
できる。Further, since a through-hole is formed in the end face of the electronic component body on which the coating layer is formed, for example, masking is performed on the internal electrode layer exposed on the end face of the electronic component body to form an insulating portion. As compared with the case of (1), since a strong covering layer can be formed by integrating the covering layer on the end surface of the electronic component body, a highly reliable laminated electronic component can be manufactured.

【００１９】[0019]

【発明の実施の形態】本発明の積層型電子部品である積
層セラミックコンデンサについて、図１の概略断面図を
もとに詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer ceramic capacitor which is a multilayer electronic component of the present invention will be described in detail with reference to a schematic sectional view of FIG.

【００２０】本発明の積層型電子部品は、直方体状の電
子部品本体１と、一対の外部電極３との間に、貫通孔４
を形成した被覆層７を形成して構成されている。この外
部電極３の上面には、図示しないが、例えば、順にＮｉ
のめっき膜、ＳｎもしくはＳｎ−Ｐｂ合金のめっき層が
形成されている。これらは外部電極３のはんだ食われ防
止やはんだ濡れ性を補うものである。The laminated electronic component of the present invention comprises a through hole 4 between a rectangular parallelepiped electronic component body 1 and a pair of external electrodes 3.
Is formed by forming a coating layer 7 on which is formed. Although not shown, for example, Ni
, And a plating layer of Sn or Sn—Pb alloy. These are to prevent the solder erosion of the external electrode 3 and to supplement the solder wettability.

【００２１】図２は電子部品本体１に被覆層７を形成し
た状態を示す斜視図である。電子部品本体１の両端表面
を含む全周面には被覆層７が形成され、前記電子部品本
体１の一端面９において、内部電極層１１の端部が交互
に露出するように被覆層７に貫通孔４を形成し、他端面
１５においては、一端面において貫通孔４が形成されな
かった内部電極層１１の端部が交互に露出するように被
覆層７に貫通孔４を形成したものである。FIG. 2 is a perspective view showing a state in which the coating layer 7 is formed on the electronic component main body 1. A coating layer 7 is formed on the entire peripheral surface including both end surfaces of the electronic component body 1. The coating layer 7 is formed on one end surface 9 of the electronic component body 1 such that the ends of the internal electrode layers 11 are alternately exposed. The through holes 4 are formed, and the through holes 4 are formed in the coating layer 7 at the other end surface 15 so that the end portions of the internal electrode layers 11 where the through holes 4 are not formed at one end surface are alternately exposed. is there.

【００２２】また、電子部品本体１は、図３に示すよう
に、誘電体層１９と内部電極層１１が交互に積層され、
電子部品本体１の端面には全内部電極層１１の端部が露
出している。As shown in FIG. 3, the electronic component body 1 has dielectric layers 19 and internal electrode layers 11 alternately laminated,
The end of the entire internal electrode layer 11 is exposed at the end face of the electronic component body 1.

【００２３】誘電体層１９の厚みは、１０μｍ以下が好
ましく、小型、大容量化、および絶縁信頼性を高める上
で、特に、２〜４μｍ以下が望ましい。The thickness of the dielectric layer 19 is preferably 10 μm or less, and particularly preferably 2 to 4 μm or less in order to reduce the size, increase the capacity, and enhance insulation reliability.

【００２４】内部電極層１１の厚みは、コンデンサの小
型化という点から２μｍ以下が好ましく、内部電極層１
１によるデラミネーションを防止し、信頼性を高める上
で、特には０．５〜１μｍの範囲であることが望まし
い。The thickness of the internal electrode layer 11 is preferably 2 μm or less from the viewpoint of miniaturization of the capacitor.
In order to prevent the delamination by No. 1 and increase the reliability, it is particularly preferable that the thickness be in the range of 0.5 to 1 μm.

【００２５】被覆層７の厚みは５０μｍ以下であれば、
積層型電子部品の静電容量の体積効率を高めることがで
きるが、積層型電子部品の耐湿性と、電子部品本体１と
被覆層７の接着強度を高めるために、特には、０．１〜
２０μｍが望ましい。If the thickness of the coating layer 7 is 50 μm or less,
Although the volumetric efficiency of the capacitance of the multilayer electronic component can be increased, in order to increase the moisture resistance of the multilayer electronic component and the adhesive strength between the electronic component body 1 and the coating layer 7, in particular, 0.1 to 0.1%
20 μm is desirable.

【００２６】被覆層７に形成された貫通孔４は、図４に
示すように、内部電極層１１から外部電極３へ向けて拡
径している。即ち、テーパ状に形成することが望まし
い。これにより貫通孔４への外部電極ペーストの充填が
容易にでき、且つ、内部電極層１１と外部電極３の接合
を確実に行うことができる。As shown in FIG. 4, the diameter of the through hole 4 formed in the coating layer 7 increases from the internal electrode layer 11 to the external electrode 3. That is, it is desirable to form the tapered shape. This facilitates the filling of the through-hole 4 with the external electrode paste, and also allows the internal electrode layer 11 and the external electrode 3 to be reliably bonded.

【００２７】電子部品本体１に用いている誘電体層１９
は、シート状のセラミック焼結体からなり、例えば、Ｂ
ａＴｉＯ3を主成分とするグリーンシートを焼成して形
成した誘電体磁器からなる。Dielectric layer 19 used in electronic component body 1
Is composed of a sheet-shaped ceramic sintered body, for example, B
It is made of a dielectric porcelain formed by firing a green sheet containing aTiO 3 as a main component.

【００２８】内部電極層１１は、導電性ペーストの膜を
焼結させた金属膜からなり、導電性ペーストとしては、
例えば、Ｎｉ、Ｃｏ、Ｃｕ等の卑金属が使用されてい
る。The internal electrode layer 11 is made of a metal film obtained by sintering a conductive paste film.
For example, base metals such as Ni, Co, and Cu are used.

【００２９】また、外部電極３の金属成分は、内部電極
層１１の金属と同一のＮｉ、Ｃｏ、Ｃｕ等を含有する金
属からなり、その他にガラス成分を含有している。The metal component of the external electrode 3 is made of the same metal containing Ni, Co, Cu, etc. as the metal of the internal electrode layer 11, and further contains a glass component.

【００３０】被覆層７は、絶縁体であればどのような材
料でもよいが、特に、誘電体と同一の材料を用いること
により熱膨張率の違いによる応力が緩和され、熱衝撃に
対する耐性が大きくなる。The covering layer 7 may be made of any material as long as it is an insulator. In particular, by using the same material as the dielectric, stress due to a difference in coefficient of thermal expansion is reduced, and resistance to thermal shock is increased. Become.

【００３１】また、被覆層７として、ガラスを用いるこ
とにより内部電極の被覆性が高くなるため、ショート率
が低く、また耐熱性が高くなる。Further, the use of glass as the coating layer 7 enhances the coverage of the internal electrodes, so that the short-circuit rate is low and the heat resistance is high.

【００３２】また、被覆層７として、樹脂を用いること
により電子部品本体１表面における応力が緩和され、強
度が高くなる。Further, by using resin as the coating layer 7, the stress on the surface of the electronic component body 1 is reduced, and the strength is increased.

【００３３】次に、本発明の積層セラミックコンデンサ
からなる積層型電子部品の製法について説明する。ま
ず、誘電体粉末を用いて、ドクターブレード法、引き上
げ法、リバースロールコータ法、グラビアコータ法、ス
クリーン印刷法、グラビア印刷等の成形法により誘電体
層のセラミックグリーンシートを作製する。Next, a method of manufacturing a multilayer electronic component comprising the multilayer ceramic capacitor of the present invention will be described. First, using a dielectric powder, a ceramic green sheet of a dielectric layer is prepared by a molding method such as a doctor blade method, a pulling method, a reverse roll coater method, a gravure coater method, a screen printing method, and a gravure printing method.

【００３４】誘電体材料としては、具体的には、ＢａＴ
ｉＯ3−ＭｎＯ−ＭｇＯ−Ｙ2Ｏ3等の誘電体粉末と焼結
助剤が好適に使用できる。また、この誘電体層のセラミ
ックグリーンシートの厚みは、１２μｍ以下が好まし
く、特に、小型、大容量化という理由から２．５〜４．
５μｍの範囲が望ましい。As the dielectric material, specifically, BaT
iO 3 -MnO-MgO-Y 2 O dielectric powder and sintering aid such 3 can be suitably used. Further, the thickness of the ceramic green sheet of the dielectric layer is preferably 12 μm or less, and particularly, from 2.5 to 4.
A range of 5 μm is desirable.

【００３５】次に、この誘電体層のセラミックグリーン
シートの表面に、スクリーン印刷法などにより内部電極
パターンを形成する。内部電極パターンの厚みは、コン
デンサの小型、高信頼性化という点から２．４μｍ以
下、特には０．６〜１．２μｍの範囲であることが望ま
しい。Next, an internal electrode pattern is formed on the surface of the ceramic green sheet of the dielectric layer by a screen printing method or the like. The thickness of the internal electrode pattern is desirably 2.4 μm or less, particularly preferably in the range of 0.6 to 1.2 μm, from the viewpoint of reducing the size and increasing the reliability of the capacitor.

【００３６】そして、内部電極パターンが形成された誘
電体層のセラミックグリーンシートを複数枚積層圧着
し、所定の形状にカットすることにより、電子部品本体
成形体を得る。Then, a plurality of ceramic green sheets of the dielectric layer on which the internal electrode patterns are formed are laminated and pressed, and cut into a predetermined shape to obtain a molded body of the electronic component.

【００３７】その後、塗布法、スクリーン印刷法などに
より被覆層成形体を形成する。塗布法やスクリーン印刷
法であれば、被覆層成形体となる材料のスラリーを調製
し、ディッピングにより形成することができ、容易且つ
安価に被覆層成形体を形成することができる。例えば、
塗布法を用いて形成する被覆層７のスラリーは、誘電体
層１９と同じ誘電体の粉末と、有機ビヒクル、添加剤、
および溶剤とを混合し、粘度１〜１０Ｐａ・Ｓ（せん断
速度＝１００Ｓ-1）のスラリーを調製し、この中に電子
部品本体成形体を入れ、その電子部品本体成形体の表面
に被覆層成形体を形成する。この後、６０〜１００℃で
乾燥した後、焼成した。Thereafter, a coating layer molding is formed by a coating method, a screen printing method or the like. In the case of a coating method or a screen printing method, a slurry of a material to be a coating layer molded body can be prepared and formed by dipping, and the coating layer molded body can be easily and inexpensively formed. For example,
The slurry of the coating layer 7 formed by using the coating method includes the same dielectric powder as the dielectric layer 19, an organic vehicle, an additive,
And a solvent, and a slurry having a viscosity of 1 to 10 Pa · S (shear rate = 100 S −1 ) is prepared, and the molded body of the electronic component is put into the slurry, and a coating layer is formed on the surface of the molded body of the electronic component. Form the body. Then, after drying at 60-100 degreeC, it baked.

【００３８】他の方法としては、塗布法で用いたスラリ
ーの粘度を２〜１２Ｐａ・Ｓ調製した後、吸引可能なパ
レット内に電子部品本体成形体の端面を揃えて置き、２
５０〜３００メッシュのスクリーンを用いて、電子部品
本体成形体の端面に印刷を行った。この場合には、内部
電極パターンが露出した面に対して、塗布膜の印刷を行
う。As another method, after the viscosity of the slurry used in the coating method is adjusted to 2 to 12 Pa · S, the end faces of the electronic component main body are placed in a pallet that can be sucked, and are placed.
Printing was performed on the end surface of the electronic component body molded body using a screen of 50 to 300 mesh. In this case, a coating film is printed on the surface where the internal electrode pattern is exposed.

【００３９】この他に被覆層成形体の形成方法として
は、被覆層７の薄膜化に対して、スパッタ法や蒸着法な
どを用いることもできる。In addition, as a method of forming the coating layer molded body, a sputtering method, a vapor deposition method, or the like can be used for thinning the coating layer 7.

【００４０】尚、被覆層成形体の形成は電子部品本体成
形体の焼成後あるいは熱処理後に行うこともある。例え
ば、被覆層７は、誘電体層１９と同一材料やガラスを用
いて形成する場合は、焼成前または焼成後に形成され
る。The formation of the coating layer molded body may be performed after firing or heat treatment of the electronic component body molded body. For example, when the covering layer 7 is formed using the same material or glass as the dielectric layer 19, it is formed before or after firing.

【００４１】被覆層７が樹脂である場合は、電子部品本
体成形体を焼成した後に形成することが必要である。When the coating layer 7 is a resin, it must be formed after firing the electronic component body molded body.

【００４２】その後、被覆層成形体が形成された、この
電子部品本体成形体を大気中２５０〜３００℃または酸
素分圧０．１〜１Ｐａの低酸素雰囲気中５００〜８００
℃で脱バイした後、非酸化性雰囲気で１１００〜１３０
０℃で２〜３時間焼成し、被覆層７が形成された電子部
品本体１を作製する。Thereafter, the molded body of the electronic component, on which the molded body of the coating layer is formed, is placed in the air at 250 to 300 ° C. or in a low oxygen atmosphere having an oxygen partial pressure of 0.1 to 1 Pa for 500 to 800.
After debubbling at a temperature of 1100 ° C. in a non-oxidizing atmosphere,
By firing at 0 ° C. for 2 to 3 hours, the electronic component body 1 on which the coating layer 7 is formed is produced.

【００４３】さらに、所望の誘電特性を得るために、酸
素分圧が０．１〜１０-4Ｐａ程度の低酸素分圧下、９０
０〜１１００℃で３〜１０時間熱処理を施すこともあ
る。Further, in order to obtain a desired dielectric characteristic, the oxygen partial pressure is set to 90.degree. Under a low oxygen partial pressure of about 0.1 to 10 @ -4 Pa.
Heat treatment may be performed at 0 to 1100 ° C. for 3 to 10 hours.

【００４４】次に、イオンビームエッチング法やレーザ
ー加工法などを用いて、内部電極層１１が交互に露出す
るように被覆層７に貫通孔４を形成する。尚、貫通孔４
の形成は脱バイ前に行うこともある。Next, through holes 4 are formed in the coating layer 7 by using an ion beam etching method, a laser processing method, or the like so that the internal electrode layers 11 are alternately exposed. In addition, the through hole 4
May be formed before de-buying.

【００４５】また、他の被覆層７および貫通孔４の形成
においては、フォトリソグラフィー法を用いて、樹脂か
らなる被覆層７を形成することができる。この場合に
は、電子部品本体１を焼成した後に、フォトレジスト加
工を行う。内部電極層１１の端部が露出した電子部品本
体１の端面全面に、例えば、被覆層７となるネガ型のエ
ポキシアクリル系の感光性材料を塗布した後、前記電子
部品本体１の端面に対して、内部電極層１１が交互に露
出するように開口したマスクパターンを置き、３００〜
８００ｍＪの紫外線を照射する。次に、アルカリ現像液
を用いて、現像を行い、内部電極層１１が露出した貫通
孔４を被覆層７に形成する。次に、この樹脂からなる被
覆層７に対し、熱硬化型樹脂を含有した導電性ペースト
を用いて、外部電極３を形成する。In forming the other coating layer 7 and the through hole 4, the coating layer 7 made of resin can be formed by using a photolithography method. In this case, after baking the electronic component body 1, a photoresist process is performed. For example, a negative-type epoxy acrylic photosensitive material serving as the coating layer 7 is applied to the entire end surface of the electronic component body 1 where the end of the internal electrode layer 11 is exposed. Then, a mask pattern that is opened so that the internal electrode layers 11 are alternately exposed is placed, and 300 to
Irradiate with 800 mJ of ultraviolet light. Next, development is performed using an alkaline developer to form through holes 4 in which the internal electrode layers 11 are exposed, in the coating layer 7. Next, the external electrodes 3 are formed on the coating layer 7 made of this resin using a conductive paste containing a thermosetting resin.

【００４６】最後に、得られた焼結体の両端部に形成さ
れた被覆層の表面および貫通孔内に、外部電極ペースト
を塗布充填し、内部電極層１１と電気的に接続された外
部電極３を形成し、積層セラミックコンデンサを作製す
る。Finally, an external electrode paste is applied and filled on the surface of the coating layer formed on both ends of the obtained sintered body and in the through holes, and the external electrodes electrically connected to the internal electrode layer 11 are filled. 3 to form a multilayer ceramic capacitor.

【００４７】以上のように構成された積層型電子部品で
は、電子部品本体１と、一対の外部電極３との間に被覆
層７を配設するとともに、該被覆層７に内部電極層１１
と外部電極３とを電気的に接続するための貫通孔４を設
けたことにより、内部電極層１１を誘電体層１９の全面
に形成し、且つ、内部電極層１１の他端と外部電極３と
の間の絶縁するための距離を最小にすることができ、こ
れにより有効面積を大きくすることができ、静電容量を
大きくすることができるとともに、静電容量のばらつき
を小さくできる。In the multilayer electronic component configured as described above, the coating layer 7 is provided between the electronic component body 1 and the pair of external electrodes 3, and the internal electrode layer 11 is provided on the coating layer 7.
The internal electrode layer 11 is formed on the entire surface of the dielectric layer 19 and the other end of the internal electrode layer 11 is connected to the external electrode 3 by providing the through hole 4 for electrically connecting the external electrode 3 to the external electrode 3. Can be minimized, thereby increasing the effective area, increasing the capacitance, and reducing the variation in capacitance.

【００４８】また、誘電体層１９の間に形成される内部
電極層１１の面積は、誘電体層１９と同じ面積であるた
め、積層型電子部品の場所による厚み差が生じることが
無いために厚み差に起因する内部応力からデラミネーシ
ョンが発生することを防止できる。Further, since the area of the internal electrode layer 11 formed between the dielectric layers 19 is the same as the area of the dielectric layer 19, there is no difference in thickness depending on the location of the multilayer electronic component. Delamination can be prevented from occurring due to the internal stress caused by the thickness difference.

【００４９】そして、内部電極層１１の端部を交互に絶
縁処理して外部電極３を形成した、従来と比較して、被
覆層７を内部電極を露出させる部分を除いて、電子部品
本体１の端面の全面に被覆するために、被覆層７と誘電
体層１９あるいは内部電極層１１の端部との接着強度を
高めることができる。Then, the external electrode 3 is formed by alternately insulating the ends of the internal electrode layer 11 to form the external electrode 3. , It is possible to increase the adhesive strength between the coating layer 7 and the end of the dielectric layer 19 or the internal electrode layer 11.

【００５０】また、図５は、本発明の積層型電子部品の
他の形態を示すもので、この積層型電子部品では、被覆
層２１に同一の内部電極層２３が露出する貫通孔２５
ａ、２５ｂが２つ形成されている。即ち、電子部品本体
の端面において、1層の内部電極層２３上に、被覆層２
１が残るように、２つの貫通孔２５ａ、２５ｂを形成す
ることにより、被覆層２１と電子部品本体と１の接着面
積を大きくでき、接合強度を高めることができる。FIG. 5 shows another embodiment of the multilayer electronic component of the present invention. In this multilayer electronic component, the through-hole 25 through which the same internal electrode layer 23 is exposed in the coating layer 21 is shown.
a and 25b are formed. That is, on the end surface of the electronic component body, the coating layer 2
By forming the two through-holes 25a and 25b so that 1 remains, the bonding area between the coating layer 21 and the electronic component body 1 can be increased, and the bonding strength can be increased.

【００５１】また、図６は、本発明の他の積層型電子部
品１を示すもので、この積層型電子部品では、被覆層３
０を形成して構成された電子部品本体１の同一端面に一
対の外部電極３３ａ、３３ｂが形成されている。FIG. 6 shows another multilayer electronic component 1 according to the present invention.
A pair of external electrodes 33a and 33b are formed on the same end surface of the electronic component main body 1 formed by forming 0.

【００５２】この場合、図７に示すように、電子部品本
体１に形成した内部電極層のうち、奇数層の内部電極層
３１ａを被覆層３０から露出させる貫通孔３５ａを左側
に、偶数層の内部電極層３１ｂを被覆層３０から露出さ
せる貫通孔３５ｂを右側に、それぞれ形成し、左右に形
成された貫通孔３５ａ、３５ｂは積層方向からみて重畳
しないように隔離されている。このように、同一端面に
外部電極３３ａ、３３ｂを２個形成することにより、電
流経路が対称的となるために高周波におけるインピーダ
ンスを下げることができ、また、実装性に関して、高い
自由度を有することができ、実装面積を小さくすること
ができる。In this case, as shown in FIG. 7, among the internal electrode layers formed on the electronic component body 1, the through-hole 35a exposing the odd-numbered internal electrode layer 31a from the coating layer 30 is located on the left side, and the even-numbered layer is opened. Through holes 35b for exposing the internal electrode layer 31b from the coating layer 30 are formed on the right side, and the through holes 35a and 35b formed on the left and right are isolated so as not to overlap when viewed from the laminating direction. As described above, by forming two external electrodes 33a and 33b on the same end surface, the current path becomes symmetrical, so that the impedance at high frequencies can be reduced, and the degree of freedom in mounting is high. And the mounting area can be reduced.

【００５３】尚、上記例では、電子部品本体１の全周面
に被覆層７を形成したが、本発明では、外部電極３が形
成される面に、被覆層７が形成されていればよい。この
場合、側面については、予め、マージン領域を形成して
おくことが望ましい。In the above example, the coating layer 7 is formed on the entire peripheral surface of the electronic component body 1. However, in the present invention, the coating layer 7 may be formed on the surface on which the external electrodes 3 are formed. . In this case, it is desirable to form a margin region in advance for the side surface.

【００５４】[0054]

【実施例】まず、ＢａＴｉＯ3、ＭｇＣＯ3、ＭｎＣＯ3
およびＹ2Ｏ3粉末と、粒界相成分として、ＣａＯ、Ｓｉ
Ｏ2等と、有機成分として、ブチラール樹脂、およびト
ルエンからなるセラミックスラリーを作製し、これをド
クターブレード法によりＰＥＴフィルム上に塗布するこ
とによって、誘電体層１９となるグリーンシートを作製
した。DESCRIPTION OF THE PREFERRED EMBODIMENTS First, BaTiO 3 , MgCO 3 , MnCO 3
And Y 2 O 3 powder and CaO, Si as grain boundary phase components
A green slurry to be the dielectric layer 19 was prepared by preparing a ceramic slurry comprising O 2 and the like and butyral resin and toluene as organic components, and applying the slurry on a PET film by a doctor blade method.

【００５５】その後、グリーンシートをＰＥＴフィルム
から剥離して、厚み９μｍのセラミックグリーンシート
を形成し、これを１０枚積層して端面セラミックグリー
ンシート層を形成した。そして、これらの端面セラミッ
クグリーンシート層を乾燥させた。この端面セラミック
グリーンシート層を台板上に配置し、プレス機により圧
着して台板上にはりつけた。Thereafter, the green sheet was peeled off from the PET film to form a 9 μm-thick ceramic green sheet, and ten of these were laminated to form an end face ceramic green sheet layer. Then, these end face ceramic green sheet layers were dried. This end face ceramic green sheet layer was arranged on a base plate, pressed by a press machine, and adhered to the base plate.

【００５６】一方、ＰＥＴフィルム上に、上記と同一の
セラミックスラリーをドクターブレード法により塗布
し、乾燥後、厚み４μｍのセラミックグリーンシートを
作製した。On the other hand, the same ceramic slurry as described above was applied on a PET film by a doctor blade method, and dried to form a ceramic green sheet having a thickness of 4 μm.

【００５７】次に、平均粒径０．２μｍのＮｉ粉末、エ
チルセルロース、有機ビヒクルを３本ロールで混練して
内部電極ペーストを作製した。Next, an internal electrode paste was prepared by kneading Ni powder having an average particle size of 0.2 μm, ethyl cellulose, and an organic vehicle with three rolls.

【００５８】この後、得られたセラミックグリーンシー
トの一方主面に、スクリーン印刷装置を用いて、上記し
た内部電極ペーストを印刷し、乾燥後、剥離した。Thereafter, the above-mentioned internal electrode paste was printed on one main surface of the obtained ceramic green sheet using a screen printing apparatus, dried, and then peeled off.

【００５９】この後、端面セラミックグリーンシート層
の上に、内部電極が形成されたグリーンシートを４００
枚積層し、この後、さらに、端面セラミックグリーンシ
ート層を積層し、積層成形体を作製した。Thereafter, a green sheet having an internal electrode formed thereon was placed on the end face ceramic green sheet layer by 400
Then, an end face ceramic green sheet layer was further laminated to produce a laminated molded body.

【００６０】次に、積層成形体を金型上に載置し、積層
方向からプレス機の加圧板により圧力を段階的に増加し
て圧着し、この後、この積層成形体を所定のチップ形状
にカットし、全内部電極パターンの端部が端面に導出し
た電子部品本体成形体を作製した。Next, the laminated molded body is placed on a mold, and the pressure is increased stepwise from the laminating direction by a pressing plate of a press machine, and then the laminated molded body is pressed into a predetermined chip shape. To form an electronic component body molded body in which the ends of all the internal electrode patterns were led out to the end faces.

【００６１】次に、塗布法、あるいはスクリーン印刷法
を用いて、電子部品本体成形体に上記セラミックペース
ト、あるいはＣａＯ・ＳｉＯ2系ガラスを含むペースト
を固着させることにより被覆層成形体を形成した。Next, the above-mentioned ceramic paste or a paste containing CaO.SiO 2 -based glass was fixed to the electronic component main body using a coating method or a screen printing method to form a coating layer molded body.

【００６２】塗布法を用いて形成する被覆層７のスラリ
ーは、誘電体層７と同じ誘電体の粉末と、有機ビヒク
ル、添加剤、および溶剤とを混合し、粘度４〜７Ｐａ・
Ｓ（せん断速度＝１００Ｓ-1）のスラリーを調製し、こ
の中に電子部品本体成形体を入れ（ディッピング）、そ
の電子部品本体成形体の表面に被覆層成形体を塗布形成
した。この後、８０〜９０℃で乾燥した。The slurry of the coating layer 7 formed by the coating method is obtained by mixing the same dielectric powder as the dielectric layer 7 with an organic vehicle, an additive, and a solvent, and having a viscosity of 4 to 7 Pa ·
A slurry of S (shear rate = 100S -1 ) was prepared, and the molded body of the electronic component was put therein (dipping), and the molded product of the coating layer was applied and formed on the surface of the molded body of the electronic component. Then, it dried at 80-90 degreeC.

【００６３】次に、大気中３００℃または０．１Ｐａの
酸素／窒素雰囲気中５００℃に加熱し、脱バイを行っ
た。さらに、１０-7Ｐａの酸素／窒素雰囲気中、１３０
０℃で２時間焼成し、さらに、１０-2Ｐａの酸素／窒素
雰囲気中にて１０００℃で熱処理を行い、被覆層７を形
成した電子部品本体１を得た。このときの被覆層７の厚
さは０．０５〜７０μｍであった。Next, heating was performed at 300 ° C. in the air or at 500 ° C. in an oxygen / nitrogen atmosphere of 0.1 Pa to remove the copper. Further, in an oxygen / nitrogen atmosphere of 10 -7 Pa, 130
The resultant was fired at 0 ° C. for 2 hours, and further heat-treated at 1000 ° C. in an oxygen / nitrogen atmosphere of 10 −2 Pa to obtain the electronic component body 1 on which the coating layer 7 was formed. At this time, the thickness of the coating layer 7 was 0.05 to 70 μm.

【００６４】他方、被覆層が樹脂の試料は、熱硬化型樹
脂とシリカ粉末とを混合して調製したスラリーを、予め
焼成、熱処理した電子部品本体１の表面に塗布した後、
硬化して作製した。On the other hand, a sample whose resin is a coating layer is prepared by applying a slurry prepared by mixing a thermosetting resin and silica powder onto the surface of the electronic component body 1 which has been previously fired and heat-treated.
It was made by curing.

【００６５】また、マスキングを用いたスパッタ法を用
いて、内部電極層１１のみに一層おきに絶縁処理を施し
た比較例の試料も用意した。A sample of a comparative example in which only the internal electrode layer 11 was subjected to insulation treatment every other layer by using a sputtering method using masking was also prepared.

【００６６】その後、表１に示す貫通孔形成法を用い
て、内部電極層が交互に露出するように被覆層７に貫通
孔４を形成した。イオンビームエッチング法はビーム径
を内部電極層１１の端部の幅に設定し、貫通孔４の加工
領域が１層の内部電極層１１の全域にわたって加工し
た。Thereafter, the through holes 4 were formed in the coating layer 7 using the through hole forming method shown in Table 1 so that the internal electrode layers were alternately exposed. In the ion beam etching method, the beam diameter was set to the width of the end of the internal electrode layer 11, and the processing area of the through hole 4 was processed over the entire area of the single internal electrode layer 11.

【００６７】その後、電子部品本体１の端面に形成され
た被覆層７およびその貫通孔４にＣｕペーストを塗布、
充填し、９００℃で焼き付け、さらにＮｉ／Ｓｎメッキ
を施し、内部電極層１１と接続する外部電極３を形成
し、図１の積層型電子部品を作製した。尚、試料Ｎｏ．
８については、図５の積層型電子部品を作製した。Thereafter, a Cu paste is applied to the coating layer 7 formed on the end face of the electronic component body 1 and the through holes 4 thereof,
It was filled, baked at 900 ° C., and further subjected to Ni / Sn plating to form the external electrodes 3 connected to the internal electrode layers 11 to produce the multilayer electronic component of FIG. In addition, sample No.
For No. 8, the laminated electronic component of FIG. 5 was produced.

【００６８】このようにして得られた積層セラミックコ
ンデンサの内部電極層１１間に介在する誘電体層１９の
厚みは３μｍであり、誘電体層９の有効積層数は４００
層とした。The thickness of the dielectric layer 19 interposed between the internal electrode layers 11 of the multilayer ceramic capacitor thus obtained is 3 μm, and the effective number of laminated dielectric layers 9 is 400 μm.
Layers.

【００６９】次に、作製した各１００個のサンプルにつ
いて、下記の測定を行った。結果を表１に示す。静電容
量計を用いて周波数１ｋＨｚ、交流電圧１Ｖでの静電容
量を測定し、ショート率も合わせて評価した。Next, the following measurement was carried out for each of the 100 samples produced. Table 1 shows the results. The capacitance at a frequency of 1 kHz and an AC voltage of 1 V was measured using a capacitance meter, and the short-circuit rate was also evaluated.

【００７０】また、外部電極上に銅線を接続し、それを
両側から引っ張ることにより、外部電極接続部の強度を
測定した。Further, a copper wire was connected to the external electrode, and the strength of the external electrode connection was measured by pulling the copper wire from both sides.

【００７１】[0071]

【表１】 [Table 1]

【００７２】表１の結果から明らかなように、電子部品
本体１の端面に、貫通孔４を有する被覆層７を形成した
本発明の試料Ｎｏ．１〜１５は、静電容量が９μＦ以
上、外部電極３の引張強度が４．７ｋｇｆ以上と高く、
且つ、ショートが殆ど無く、積層コンデンサの特性を改
善できた。As is clear from the results shown in Table 1, the sample No. of the present invention in which the coating layer 7 having the through holes 4 was formed on the end face of the electronic component body 1 was obtained. Nos. 1 to 15 have a high capacitance of 9 μF or more and a tensile strength of the external electrode 3 of 4.7 kgf or more,
In addition, there was almost no short circuit, and the characteristics of the multilayer capacitor could be improved.

【００７３】一方、内部電極層１１の印刷パターンを制
御し、マージン部を形成して作製した試料Ｎｏ．１６で
は、引張強度が高く、ショートはなかったが、内部電極
層１１の有効面積が小さいために静電容量が低くなっ
た。On the other hand, the print pattern of the internal electrode layer 11 was controlled to form a margin portion, and the sample No. In No. 16, although the tensile strength was high and there was no short circuit, the capacitance was low because the effective area of the internal electrode layer 11 was small.

【００７４】また、電子部品本体１の端面にマスキング
を行い、スパッタ法により交互に絶縁処理を施して作製
した試料Ｎｏ．１７では、絶縁処理部の面積が小さく、
誘電体層と一体化していないために、静電容量が低く、
ショートが発生し、引張強度は著しく低下した。The sample No. 1 was prepared by masking the end surface of the electronic component body 1 and alternately performing insulation processing by sputtering. In No. 17, the area of the insulating portion is small,
Because it is not integrated with the dielectric layer, the capacitance is low,
A short circuit occurred, and the tensile strength was significantly reduced.

【００７５】[0075]

【発明の効果】本発明の積層型電子部品は、電子部品本
体と、一対の外部電極との間に被覆層を配設するととも
に、該被覆層に内部電極層と外部電極とを電気的に接続
するための貫通孔を設けているため、内部電極層と外部
電極との間を絶縁するための距離を最小にでき、内部電
極層の有効面積を大きくすることができ、静電容量を大
きくすることができる。According to the multilayer electronic component of the present invention, a coating layer is provided between the electronic component body and a pair of external electrodes, and the internal electrode layer and the external electrode are electrically connected to the coating layer. Since a through hole for connection is provided, the distance for insulating between the internal electrode layer and the external electrode can be minimized, the effective area of the internal electrode layer can be increased, and the capacitance can be increased. can do.

【００７６】また、誘電体層の間に形成される内部電極
層の面積は、誘電体層とほぼ同じ面積であるため、電子
部品本体の場所による厚み差が生じることが無いために
厚み差に起因する内部応力からデラミネーションが発生
することを防止できる。The area of the internal electrode layer formed between the dielectric layers is almost the same as the area of the dielectric layer. Delamination can be prevented from occurring due to the resulting internal stress.

【００７７】さらに、被覆層が電子部品本体の端面の全
面に被覆されているために、被覆層と、誘電体層あるい
は内部電極層の端部との接着強度を高めることができ
る。Further, since the coating layer covers the entire end face of the electronic component body, the adhesive strength between the coating layer and the end of the dielectric layer or the internal electrode layer can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の積層型電子部品の概略断面図である。FIG. 1 is a schematic cross-sectional view of a multilayer electronic component of the present invention.

【図２】電子部品本体に被覆層を形成した状態を示す斜
視図である。FIG. 2 is a perspective view showing a state in which a coating layer is formed on the electronic component body.

【図３】本発明の電子部品本体を示す斜視図である。FIG. 3 is a perspective view showing an electronic component body of the present invention.

【図４】貫通孔が形成された被覆層およびその近傍を示
す断面図である。FIG. 4 is a cross-sectional view showing a coating layer in which a through hole is formed and the vicinity thereof.

【図５】被覆層に一つの内部電極層が露出する貫通孔を
２個形成した本発明の他の積層型電子部品を示す斜視図
である。FIG. 5 is a perspective view showing another laminated electronic component of the present invention in which two through holes exposing one internal electrode layer are formed in a coating layer.

【図６】同一端面に２個の外部電極を設けた本発明のさ
らに他の積層型電子部品を示す斜視図である。FIG. 6 is a perspective view showing still another laminated electronic component of the present invention in which two external electrodes are provided on the same end surface.

【図７】図６の被覆層における貫通孔の形成位置を示す
斜視図である。FIG. 7 is a perspective view showing positions where through holes are formed in the coating layer of FIG. 6;

【符号の説明】[Explanation of symbols]

１ 電子部品本体 ３ 外部電極 ４ 貫通孔 ７ 被覆層 １１ 内部電極層 １９ 誘電体層 DESCRIPTION OF SYMBOLS 1 Electronic component main body 3 External electrode 4 Through-hole 7 Coating layer 11 Internal electrode layer 19 Dielectric layer

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】誘電体層と内部電極層とが交互に積層され
た電子部品本体の端面に、前記内部電極層が交互に接続
される一対の外部電極を形成してなる積層型電子部品に
おいて、前記電子部品本体と、一対の外部電極との間に
被覆層を配設するとともに、該被覆層に前記内部電極層
と外部電極とを電気的に接続するための貫通孔を設けた
ことを特徴とする積層型電子部品。1. A laminated electronic component comprising a pair of external electrodes formed by alternately connecting said internal electrode layers to an end surface of an electronic component body in which dielectric layers and internal electrode layers are alternately laminated. Providing a coating layer between the electronic component body and the pair of external electrodes, and providing a through hole in the coating layer for electrically connecting the internal electrode layer and the external electrode. Characterized multilayer electronic components. 【請求項２】被覆層の厚さが５０μｍ以下であることを
特徴とする請求項１記載の積層型電子部品。2. The multilayer electronic component according to claim 1, wherein the thickness of the coating layer is 50 μm or less. 【請求項３】被覆層には、同一の内部電極層が露出する
貫通孔が複数形成されていることを特徴とする請求項１
または２記載の積層型電子部品。3. The coating layer according to claim 1, wherein a plurality of through holes exposing the same internal electrode layer are formed.
Or the laminated electronic component of 2. 【請求項４】電子部品本体の同一端面に一対の外部電極
を設けてなることを特徴とする請求項１乃至３のうちい
ずれかに記載の積層型電子部品。4. The multilayer electronic component according to claim 1, wherein a pair of external electrodes are provided on the same end surface of the electronic component body. 【請求項５】誘電体グリーンシートと内部電極パターン
とを交互に積層し、内部電極パターンの端部が端面に導
出する電子部品本体成形体を作製するとともに、該電子
部品本体成形体の少なくとも端面にセラミックペースト
を塗布して被覆層成形体を作製する工程と、前記電子部
品本体成形体及び被覆層成形体を焼成し、少なくとも端
面に被覆層が被着されている誘電体層と内部電極層とが
交互に積層されてなる電子部品本体を作製する工程と、
前記被覆層に内部電極層の端部が交互に露出するように
複数個の貫通孔を形成する工程と、前記被覆層表面およ
び貫通孔内に外部電極ペーストを塗布充填するとともに
焼き付け、内部電極層が交互に接続している一対の外部
電極を作製する工程とから成る積層型電子部品の製法。5. An electronic component molded body in which dielectric green sheets and internal electrode patterns are alternately laminated to form an electronic component main body in which an end of the internal electrode pattern extends to an end face, and at least an end face of the electronic component main body molded article. A ceramic paste is applied to form a coating layer molded body, and the electronic component body molded body and the coating layer molded body are baked, and a dielectric layer and an internal electrode layer having a coating layer applied to at least end faces thereof A step of producing an electronic component body in which are alternately laminated,
Forming a plurality of through-holes such that the end portions of the internal electrode layer are alternately exposed in the coating layer, and applying and filling an external electrode paste on the surface of the coating layer and in the through-hole, and baking; Forming a pair of external electrodes alternately connected to each other.
JP2000199127A 2000-06-30 2000-06-30 Multilayer electronic component and manufacturing method thereof Expired - Fee Related JP4573956B2 (en)

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