JPH0728119B2 - Electrode structure of electronic component mounting board - Google Patents
Electrode structure of electronic component mounting boardInfo
- Publication number
- JPH0728119B2 JPH0728119B2 JP2083870A JP8387090A JPH0728119B2 JP H0728119 B2 JPH0728119 B2 JP H0728119B2 JP 2083870 A JP2083870 A JP 2083870A JP 8387090 A JP8387090 A JP 8387090A JP H0728119 B2 JPH0728119 B2 JP H0728119B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- electrode
- substrate
- terminal
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、ハイブリッドICにおける電子部品搭載用基板
の電極構造の改良に関するものである。TECHNICAL FIELD The present invention relates to improvement of an electrode structure of an electronic component mounting substrate in a hybrid IC.
（従来の技術） 第２図は、従来のハイブリッドICにおける電子部品搭載
用基板の電極構造を示す斜視図であって、図中、10は電
子部品としてのパワートランジスタ、20は電子部品搭載
用基板である。(Prior Art) FIG. 2 is a perspective view showing an electrode structure of an electronic component mounting substrate in a conventional hybrid IC, in which 10 is a power transistor as an electronic component and 20 is an electronic component mounting substrate. Is.
ハイブリッドICに搭載されるパワートランジスタ10は、
チップ等を内蔵し、かつ、樹脂が充填された本体11が平
板形状をなし、その一の側面11aの下方からはフィンと
しての機能を併せ持つ板状のコレクタ端子12が導出さ
れ、側面11aの対向側面11bからはリード状のエミッタ端
子13並びにベース端子14が導出されている。The power transistor 10 installed in the hybrid IC is
A resin-filled main body 11 having a built-in chip and the like has a flat plate shape, and a plate-shaped collector terminal 12 that also has a function as a fin is led out from the lower side of one side surface 11a thereof, and the side surface 11a faces A lead-shaped emitter terminal 13 and a base terminal 14 are led out from the side surface 11b.
このような形状を有するパワートランジスタ10を搭載す
るため、基板20上には、各端子12,13,14を変形させるこ
となく半田付けができる位置関係をもって、端子対応の
３電極21,22,23が形成される。Since the power transistor 10 having such a shape is mounted, the three electrodes 21, 22, 23 corresponding to the terminals are arranged on the substrate 20 in such a position that the terminals 12, 13, 14 can be soldered without being deformed. Is formed.
これら電極21,22,23のうち、エミッタ端子13並びにベー
ス端子14取付用の電極22,23は各端子13,14に応じた大き
さに形成される。一方、コレクタ端子12取付用の電極21
は、本体11の下面11cのフレームに合わせ、かつ、半田
のマウント領域を大きくし、放熱効果を高めるため、コ
レクタ端子12のみならず、下面11cと対向するように、
電極22,23より大きく形成される。Of these electrodes 21, 22, 23, the electrodes 22, 23 for attaching the emitter terminal 13 and the base terminal 14 are formed in a size corresponding to the terminals 13, 14. On the other hand, the electrode 21 for mounting the collector terminal 12
Is aligned with the frame of the lower surface 11c of the main body 11, and in order to increase the solder mounting area and enhance the heat dissipation effect, so as to face not only the collector terminal 12 but also the lower surface 11c,
It is formed larger than the electrodes 22 and 23.
以上の構造において、パワートランジスタ10を基板20に
搭載するには、半田リフロー法が用いられる。In the above structure, the solder reflow method is used to mount the power transistor 10 on the substrate 20.
その手順を説明すると、まず、電極21におけるコレクタ
端子12との対向領域並びに電極22,23の各々にペースト
状半田を印刷する。The procedure will be described. First, paste-like solder is printed on a region of the electrode 21 facing the collector terminal 12 and each of the electrodes 22 and 23.
次に、パワートランジスタ10の各端子12,13,14をそれぞ
れ対応電極21,22,23上に載置、即ち、パワートランジス
タ10を基板20上にマウントする。Next, the terminals 12, 13, 14 of the power transistor 10 are placed on the corresponding electrodes 21, 22, 23, that is, the power transistor 10 is mounted on the substrate 20.
次いで、半田をリフローさせて各端子12,13,14と電極2
1,22,23とを半田付けする。これにより、パワートラン
ジスタ10の基板20への搭載が完了する。Next, the solder is reflowed so that each terminal 12, 13, 14 and electrode 2
Solder 1,22,23. This completes the mounting of the power transistor 10 on the substrate 20.
また、基板20へのパワートランジスタ10等の搭載後は、
各電子部品を覆うように樹脂塗装が行われる。Also, after mounting the power transistor 10 etc. on the substrate 20,
Resin coating is performed so as to cover each electronic component.
（発明が解決しようとする課題） しかしながら、上記構造を有する電極21,22,23に対し、
パワートランジスタ10を半田付けすると、第３図に示す
ように、コレクタ端子12のみならず、本体11の下面11c
が電極21と密着した状態で半田付けされてしまい、半田
SLの熱が本体11の広い範囲に亘って直接伝導されるよう
になる。(Problems to be solved by the invention) However, with respect to the electrodes 21, 22, 23 having the above structure,
When the power transistor 10 is soldered, as shown in FIG. 3, not only the collector terminal 12 but also the bottom surface 11c of the main body 11
Will be soldered in close contact with the electrode 21.
The heat of the SL is directly conducted over a wide area of the main body 11.
これにより、本体11内に充填されている樹脂RNが熱によ
り活性化され、トランジスタチップ15に応力を加えるよ
うになり、遂には、トランジスタチップ15に水平クラッ
クCRが発生してしまうという欠点があった。As a result, the resin RN filled in the main body 11 is activated by heat, and stress is applied to the transistor chip 15, which eventually causes a horizontal crack CR in the transistor chip 15. It was
また、樹脂塗装を行った後、熱ストレスにより樹脂が収
縮する際に発生する応力が、基板20から半田SLを介して
トランジスタ10に直接加わるようになり、やはり、トラ
ンジスタチップ15におけるクラックCR発生の要因とな
る。Further, after the resin coating, the stress generated when the resin shrinks due to the thermal stress comes to be directly applied to the transistor 10 from the substrate 20 through the solder SL, and again, the crack CR in the transistor chip 15 may occur. It becomes a factor.
従って、従来の電極構造によって製造されたハイブリッ
ドICは歩留まりが悪く、生産性、信頼性が低いという問
題点があった。Therefore, the hybrid IC manufactured by the conventional electrode structure has a problem that the yield is low and the productivity and reliability are low.
本発明は、かかる事情に鑑みてなされたものであり、そ
の目的は、半田付の際の半田の熱が電子部品本体に直接
伝わることを防止し、内，外部から電子部品に加わる応
力を緩和でき、ハイブリッドICの生産性、信頼性の向上
を図れる電子部品搭載用基板の電極構造を提供すること
にある。The present invention has been made in view of the above circumstances, and an object thereof is to prevent the heat of solder during soldering from being directly transmitted to the electronic component body and reduce the stress applied to the electronic component from inside and outside. Another object of the present invention is to provide an electrode structure of a substrate for mounting electronic components, which can improve the productivity and reliability of the hybrid IC.
（課題を解決するための手段） 上記目的を達成するため、本発明は、電子部品本体の下
面から延びて更に該電子部品本体の側面から突出した幅
広の一端子を含む複数の端子を半田付けするための電極
が複数形成され、かつ、これらの電極のうち該一端子に
対応する一の電極が、該一端子の下面に対向するよう形
成された電子部品搭載用基板の電極構造において、前記
一の電極を、前記電子部品搭載用基板上における前記電
子部品本体との対向領域を除く領域に形成したことを特
徴とする。(Means for Solving the Problems) To achieve the above object, the present invention solders a plurality of terminals including one wide terminal extending from a lower surface of an electronic component body and further protruding from a side surface of the electronic component body. In the electrode structure of the electronic component mounting substrate, a plurality of electrodes for forming the electrode are formed, and one of the electrodes corresponding to the one terminal is formed so as to face the lower surface of the one terminal. One electrode is formed on a region of the electronic component mounting substrate except a region facing the electronic component main body.
（作用） 本発明によれば、例えば、各電極にペースト状半田を印
刷し、電子部品の各端子を対応電極上に載置して、半田
リフロー法により半田付けを行った場合、各端子は各電
極に固定される。この際、一の電極においては、溶融し
た半田が基板上における電子部品本体との対向領域には
回り込まず、端子のみが電極と半田付けされる。(Operation) According to the present invention, for example, when paste-like solder is printed on each electrode, each terminal of the electronic component is placed on the corresponding electrode, and soldering is performed by the solder reflow method, each terminal is It is fixed to each electrode. At this time, in the one electrode, the molten solder does not flow into the area of the substrate facing the electronic component body, and only the terminal is soldered to the electrode.
従って、電子部品本体と基板とが密着せず、半田の熱が
電子部品本体に直接伝わることが回避され、また、電子
部品本体内のチップ等に対する外部からの応力印加が緩
和される。Therefore, the heat of the solder is prevented from being directly transferred to the electronic component body because the electronic component body and the substrate are not in close contact with each other, and the stress application from the outside to the chip or the like in the electronic component body is relieved.
（実施例） 第１図は、本発明に係るハイブリッドICにおける電子部
品搭載用基板の電極構造の一実施例を示す斜視図、第４
図は本発明に係る電子部品搭載状態を示す断面図であっ
て、従来例を示す第２図及び第３図と同一構成部分は同
一符号をもって表す。(Embodiment) FIG. 1 is a perspective view showing an embodiment of an electrode structure of an electronic component mounting substrate in a hybrid IC according to the present invention, FIG.
The figure is a cross-sectional view showing the electronic component mounting state according to the present invention, and the same components as those in FIGS. 2 and 3 showing a conventional example are represented by the same reference numerals.
即ち、10は電子部品としてのパワートランジスタ、11は
平板形状をなすパワートランジスタ10の本体、12は側面
11aから突出した板状のコレクタ端子、13は側面11bから
突出したリード状のエミッタ端子、14はエミッタ端子13
と並列して側面11bから突出したリード状のベース端
子、15は本体11内に搭載されたトランジスタチップ、20
はアルミナ等からなる電子部品搭載用基板、21aはコレ
クタ端子12取付用電極、22はエミッタ端子13取付用電
極、23はベース端子14取付用電極で、これら電極21a,2
2,23は例えば基板20上に印刷したAg−Pdにより構成され
ている。That is, 10 is a power transistor as an electronic component, 11 is a main body of the power transistor 10 having a flat plate shape, and 12 is a side surface.
11a is a plate-shaped collector terminal protruding from 11a, 13 is a lead-shaped emitter terminal protruding from the side surface 11b, and 14 is an emitter terminal 13
A lead-shaped base terminal protruding in parallel from the side surface 11b, 15 is a transistor chip mounted inside the main body 11, 20
Is an electronic component mounting substrate made of alumina or the like, 21a is an electrode for mounting the collector terminal 12, 22 is an electrode for mounting the emitter terminal 13, 23 is an electrode for mounting the base terminal 14, and these electrodes 21a, 2
2, 23 are composed of Ag-Pd printed on the substrate 20, for example.
コレクタ端子12取付用電極21aは、第２図に示す従来構
造と異なり、コレクタ端子12との対向領域のみに形成さ
れ、パワートランジスタ10の本体11の下面11cとの対向
領域には形成されていない。即ち、本体下面11cとの対
向領域は、基板20の表面となっている。Unlike the conventional structure shown in FIG. 2, the collector terminal 12 mounting electrode 21a is formed only in a region facing the collector terminal 12 and is not formed in a region facing the lower surface 11c of the body 11 of the power transistor 10. . That is, the area facing the lower surface 11c of the main body is the surface of the substrate 20.
また、第１図中、符号24で示す領域は、厚膜回路の作製
工程における最終工程で形成されるオーバーコートガラ
ス層で、各電極部を除く導体パターン部を被覆してい
る。In addition, in FIG. 1, a region indicated by reference numeral 24 is an overcoat glass layer formed in the final step of the manufacturing process of the thick film circuit, and covers the conductor pattern portion excluding each electrode portion.
次に、上記電極構造を持つ基板20に対するパワートラン
ジスタ10の搭載手順について説明する。Next, a procedure for mounting the power transistor 10 on the substrate 20 having the above electrode structure will be described.
まず、電極21a並びに電極22,23の各々にペースト状半田
を印刷する。First, paste solder is printed on each of the electrode 21a and the electrodes 22 and 23.
次に、パワートランジスタ10の各端子12,13,14をそれぞ
れ対応電極21a,22,23上に載置、即ち、パワートランジ
スタ10を基板20上にマウントする。Next, the terminals 12, 13, 14 of the power transistor 10 are placed on the corresponding electrodes 21a, 22, 23, respectively, that is, the power transistor 10 is mounted on the substrate 20.
次いで、半田をリフローさせて各端子12,13,14と電極21
a,22,23とを半田付けする。Next, the solder is reflowed so that each terminal 12, 13, 14 and electrode 21
Solder a, 22, and 23.
この工程における半田溶融の際、溶融した半田は、パワ
ートランジスタ10の本体11の下面11cと対向する基板20
上には回り込まないため、第４図に示すように、本体11
の近接領域においてはコレクタ端子12のみが密着固定さ
れ、本体11の下面11cには半田が付着することがない。
従って、半田付けの際の半田SLの熱が本体11に直接伝わ
ることはない。During the melting of the solder in this step, the melted solder is the substrate 20 facing the lower surface 11c of the main body 11 of the power transistor 10.
As it does not wrap around above, as shown in FIG.
Only the collector terminal 12 is fixed in close contact in the area adjacent to, and solder does not adhere to the lower surface 11c of the main body 11.
Therefore, the heat of the solder SL at the time of soldering is not directly transmitted to the main body 11.
さらに、上記したように基板20に対するパワートランジ
スタ10等の電子部品搭載完了後には、これら電子部品を
覆い保護するように樹脂塗装が行われる。Furthermore, as described above, after the electronic components such as the power transistor 10 have been mounted on the substrate 20, resin coating is performed so as to cover and protect these electronic components.
この樹脂塗装において、塗布された樹脂が冷却し、収縮
する際に基板20等による応力が発生するが、上述したよ
うにパワートランジスタ10の本体11の下面11cは、第４
図に示すように、基板20に対して密着されないため、応
力が本体11内のトランジスタチップ15に直接加わらな
い。In this resin coating, when the applied resin cools and contracts, stress is generated by the substrate 20 and the like, but as described above, the lower surface 11c of the main body 11 of the power transistor 10 is
As shown in the figure, stress is not directly applied to the transistor chip 15 in the main body 11 because the stress is not adhered to the substrate 20.
以上説明したように、本実施例によれば、コレクタ端子
12取付用電極21aを、本体11の下面11cとの対向領域を除
く近接領域に形成したので、半田付けの際に本体下面11
cと基板20との間に半田が回り込まず、本体下面11cに半
田が付着することがなく、また、本体11が基板20に対し
て密着接続されることがない。As described above, according to this embodiment, the collector terminal
12 Since the mounting electrodes 21a are formed in the proximity area excluding the area facing the lower surface 11c of the main body 11, the lower surface 11 of the main body 11 can be soldered.
Solder does not wrap around between c and the substrate 20, solder does not adhere to the lower surface 11c of the main body, and the main body 11 is not closely connected to the substrate 20.
これにより、本体11内に充填されている樹脂RNが熱的に
活性化されることを防止できるとともに、樹脂塗装後
に、樹脂の収縮に起因して発生する基板20等から本体11
に加わる応力を緩和できる。As a result, the resin RN filled in the main body 11 can be prevented from being thermally activated, and after the resin coating, the main body 11 from the substrate 20 or the like generated due to the contraction of the resin.
The stress applied to can be relaxed.
これに伴い、トランジスタチップ15におけるクラック発
生を防止でき、ひいてはハイブリッドICの生産性の向
上、信頼性の向上を図れる利点がある。Along with this, it is possible to prevent the occurrence of cracks in the transistor chip 15, and thus it is possible to improve productivity and reliability of the hybrid IC.
（発明の効果） 以上説明したように、本発明によれば、一の電極を、基
板上における電子部品本体との対向領域を除く領域に形
成したので、基板に電子部品を半田付けした後、電子部
品本体と基板とが密着し接続されることがなく、半田が
電子部品本体に付着することがない。(Effects of the Invention) As described above, according to the present invention, since one electrode is formed in a region on the substrate other than the region facing the electronic component body, after soldering the electronic component to the substrate, The electronic component body and the substrate are not in close contact with each other and connected, and the solder does not adhere to the electronic component body.
従って、半田付けの際の半田の熱が電子部品本体に直接
伝わることを防止でき、また、樹脂塗装を行った後に発
生する熱ストレスによる樹脂の収縮による応力が、電子
部品本体内に搭載されたチップ等に対して直接加わるこ
とを緩和できる。Therefore, it is possible to prevent the heat of the solder during the soldering from being directly transmitted to the electronic component body, and the stress due to the shrinkage of the resin due to the thermal stress generated after the resin coating is mounted inside the electronic component body. It is possible to reduce the direct addition to the chip.
このため、チップにおける水平クラックの発生を防止で
き、ひいてはハイブリッドIC等の生産性の向上、信頼性
の向上を図れる利点がある。Therefore, there is an advantage that horizontal cracks can be prevented from being generated in the chip, and thus productivity and reliability of the hybrid IC and the like can be improved.
第１図は本発明に係るハイブリッドICにおける電子部品
搭載用基板の電極構造の一実施例を示す斜視図、第２図
は従来のハイブリッドICにおける電子部品搭載用基板の
電極構造を示す斜視図、第３図は従来の電子部品搭載状
態を示す断面図、第４図は本発明に係る電子部品搭載状
態を示す断面図である。 図中、10……パワートランジスタ（電子部品）、11……
本体、12……コレクタ端子、13……エミッタ端子、14…
…ベース端子、15……トランジスタチップ、20……電子
部品搭載用基板、21a……コレクタ端子取付用電極、22
……エミッタ端子取付用電極、23……ベース端子取付用
電極。FIG. 1 is a perspective view showing an embodiment of an electrode structure of an electronic component mounting substrate in a hybrid IC according to the present invention, and FIG. 2 is a perspective view showing an electrode structure of an electronic component mounting substrate in a conventional hybrid IC, FIG. 3 is a sectional view showing a conventional electronic component mounted state, and FIG. 4 is a sectional view showing an electronic component mounted state according to the present invention. In the figure, 10 …… power transistor (electronic component), 11 ……
Main unit, 12 ... Collector terminal, 13 ... Emitter terminal, 14 ...
… Base terminal, 15 …… Transistor chip, 20 …… Electronic component mounting board, 21a …… Collector terminal mounting electrode, 22
...... Emitter terminal mounting electrode, 23 …… Base terminal mounting electrode.
Claims (1)
部品本体の側面から突出した幅広の一端子を含む複数の
端子を半田付けするための電極が複数形成され、かつ、
これらの電極のうち該一端子に対応する一の電極が、該
一端子の下面に対向するよう形成された電子部品搭載用
基板の電極構造において、 前記一の電極を、前記電子部品搭載用基板上における前
記電子部品本体との対向領域を除く領域に形成した ことを特徴とする電子部品搭載用基板の電極構造。1. A plurality of electrodes for soldering a plurality of terminals including one wide terminal extending from a lower surface of an electronic component body and protruding from a side surface of the electronic component body, and
Of the electrodes, one electrode corresponding to the one terminal has an electrode structure of an electronic component mounting substrate formed so as to face a lower surface of the one terminal, wherein the one electrode is the electronic component mounting substrate. An electrode structure of an electronic component mounting substrate, which is formed in a region excluding a region facing the electronic component main body above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2083870A JPH0728119B2 (en) | 1990-03-30 | 1990-03-30 | Electrode structure of electronic component mounting board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2083870A JPH0728119B2 (en) | 1990-03-30 | 1990-03-30 | Electrode structure of electronic component mounting board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03283560A JPH03283560A (en) | 1991-12-13 |
| JPH0728119B2 true JPH0728119B2 (en) | 1995-03-29 |
Family
ID=13814700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2083870A Expired - Fee Related JPH0728119B2 (en) | 1990-03-30 | 1990-03-30 | Electrode structure of electronic component mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0728119B2 (en) |
-
1990
- 1990-03-30 JP JP2083870A patent/JPH0728119B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03283560A (en) | 1991-12-13 |
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