JPH07107901B2 - Tape forming method by reduction projection exposure method - Google Patents
Tape forming method by reduction projection exposure methodInfo
- Publication number
- JPH07107901B2 JPH07107901B2 JP62097758A JP9775887A JPH07107901B2 JP H07107901 B2 JPH07107901 B2 JP H07107901B2 JP 62097758 A JP62097758 A JP 62097758A JP 9775887 A JP9775887 A JP 9775887A JP H07107901 B2 JPH07107901 B2 JP H07107901B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- layer
- resist layer
- hole
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体の製造方法に関し、特に下側導電層上に
絶縁層を介して上側導電層を形成する際のコンタクト部
における上側導電層の断線を防止した半導体装置の製造
方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor, and particularly to a method for forming an upper conductive layer in a contact portion when an upper conductive layer is formed on a lower conductive layer via an insulating layer. The present invention relates to a method for manufacturing a semiconductor device in which disconnection is prevented.
半導体装置ではシリコン基板や下側配線層等の下側導電
層と、この上側に絶縁層を介して形成した配線層等の上
側導電層との相互接続を図るために、絶縁層にコンタク
ト用の透孔を開設し、この透孔を通して両者の電気的接
続を行っている。In a semiconductor device, a lower conductive layer such as a silicon substrate or a lower wiring layer and an upper conductive layer such as a wiring layer formed on the upper side of the insulating layer via an insulating layer are interconnected in order to make contact with the insulating layer. A through hole is opened, and the two are electrically connected through this through hole.
ところで、この絶縁層に形成する透孔が断面急峻な形状
であると、上側導電層を形成する際のカバレッジ性によ
り断線が生じることがある。このため、前記透孔は断面
の傾斜を可及的に緩和することが必要であり、従来では
異方性エッチングと等方性エッチングとを併用する方法
を用いて透孔の開設を行っている。By the way, if the through hole formed in this insulating layer has a steep cross-section, disconnection may occur due to the coverage when forming the upper conductive layer. Therefore, it is necessary to reduce the inclination of the cross section of the through hole as much as possible. Conventionally, the through hole is formed by using a method that uses both anisotropic etching and isotropic etching. .
第２図（ａ）〜（ｅ）はこの種の従来方法であり、シリ
コン基板11とその上に形成する上側導電層との電気的接
続を行う例を示している。FIGS. 2A to 2E show a conventional method of this kind, and show an example of electrically connecting the silicon substrate 11 and the upper conductive layer formed thereon.
即ち、同図（ａ）のように、シリコン基板11上にPSG
（リンガラス）等の絶縁層12を形成した後、その上にポ
ジ型フォトレジスト13を塗布し、しかる上でこれを同図
（ｂ）のように所要のパターンを形成して透孔形成箇所
を開孔する。That is, as shown in FIG.
After forming an insulating layer 12 such as (phosphorus glass), a positive type photoresist 13 is applied thereon, and then a desired pattern is formed as shown in FIG. To open a hole.
次いで、ポジ型フォトレジスト13をマスクとし、バッフ
ァード弗酸を用いた湿式エッチング法等の等方性エッチ
ングにより同図（ｃ）のように絶縁層12の約半分までエ
ッチングし、サイドエッチングされた凹部14を形成す
る。Next, using the positive photoresist 13 as a mask, isotropic etching such as a wet etching method using buffered hydrofluoric acid is performed up to about half of the insulating layer 12 as shown in FIG. 7C, and side etching is performed. The recess 14 is formed.
続いて、CHF3＋O2またはCF4＋H2をエッチングガスとし
て用いる反応性イオンエッチング等の異方性エッチング
により絶縁層12を前厚さに亘るまでエッチングし、同図
（ｄ）のように前記凹部14の下に透孔15を形成する。し
かる上で、前記ポジ型フォトレジスト13を除去すれば、
断面の特に開口縁部の傾斜が緩和された透孔16を開設で
き、この上にアルミニウム等の上側導電層17を形成する
ことにより、同図（ｅ）のようにシリコン基板11と配線
層17の電気接続構造を形成できる。Then, the insulating layer 12 is etched to the previous thickness by anisotropic etching such as reactive ion etching using CHF 3 + O 2 or CF 4 + H 2 as an etching gas, and as shown in FIG. A through hole 15 is formed below the recess 14. Then, if the positive photoresist 13 is removed,
It is possible to form a through hole 16 in which the inclination of the cross-section, especially at the edge of the opening, is relaxed, and by forming an upper conductive layer 17 of aluminum or the like on this, a silicon substrate 11 and a wiring layer 17 are formed as shown in FIG. The electrical connection structure can be formed.
上述した従来の透孔の開設方法では、先に行う湿式エッ
チング法により形成される凹部14の深さを均一に管理す
ることが難しいため、凹部14下に残される絶縁層12の厚
さが不均一となる。このため、後に続く異方性エッチン
グ時に残り膜厚の小さい箇所では、孔15が開設された後
も暫くの間はプラズマに晒されることになり、シリコン
基板11表面がプラズマダメージを受けて素子特性に悪影
響を生じることがある。In the above-described conventional method of forming a through hole, it is difficult to uniformly control the depth of the recess 14 formed by the wet etching method that is performed first, so that the thickness of the insulating layer 12 left below the recess 14 is not uniform. Be uniform. Therefore, during the subsequent anisotropic etching, the portion with a small remaining film thickness is exposed to the plasma for a while even after the hole 15 is opened, and the surface of the silicon substrate 11 is damaged by the plasma and the device characteristics are deteriorated. May be adversely affected.
また、形成される透孔16は開孔縁部、即ち湿式エッチン
グにより形成された凹部14の傾斜が緩和されても、その
下部の異方性エッチングされた孔15の断面は急峻のまま
であり、プロセスいかんによってはこの部分で上側同電
層17の段切れが生じる恐れがあり、高い信頼性を得るこ
とは難しいという問題もある。Further, even though the through hole 16 formed has an opening edge portion, that is, even if the inclination of the concave portion 14 formed by wet etching is relaxed, the cross section of the anisotropically etched hole 15 thereunder remains steep. Depending on the process, there is a risk that the upper same-electric layer 17 may be disconnected at this portion, and it is difficult to obtain high reliability.
上述した異方性エッチングと等方性エッチングへ併用す
る従来の透孔の開設方法に対し、本発明は、縮小投影露
光法による目合露光時に、フォーカスを任意の値にデフ
ォーカスした状態で、目合露光を行ない開口パターンを
形成するレジスト層の断面形状を、ある範囲内で任意の
角度のテーパー状に形成し、このレジスト層をマスクと
して被エッチング材料を異方性エッチングして、レジス
ト層の開口位置の被エッチング材料に、ある範囲内で任
意の角度のテーパー状の透孔（第３図）を開設する内容
を有する。In contrast to the conventional method of forming a through hole used in combination with the anisotropic etching and the isotropic etching described above, the present invention, in the eye exposure by the reduction projection exposure method, in the state where the focus is defocused to an arbitrary value, The cross-sectional shape of the resist layer that forms the opening pattern by mesh exposure is formed into a taper shape with an arbitrary angle within a certain range, and the material to be etched is anisotropically etched using this resist layer as a mask to form a resist layer. In the material to be etched at the opening position, a tapered through hole (FIG. 3) having an arbitrary angle within a certain range is provided.
本発明は、一導電型半導体基板の表面に絶縁層を形成す
る工程と、前記絶縁層の表面にレジスト層を形成した後
に、縮小投影露光法によりフォーカスを−3.5μｍ以上
０μｍ未満の範囲の任意の値のデフォーカス状態で露光
しかつ現象して前記レジスト層開口の断面形状を任意の
テーパー状に形成する工程と、このレジスト層をマスク
として、前記絶縁層と前記レジスト層とのエッチング速
度比が10〜15の範囲で前記絶縁層を異方性エッチングし
てレジスト層の開口位置の絶縁層にテーパー状の透孔を
開設する工程とを有している。The present invention provides a step of forming an insulating layer on the surface of a one-conductivity-type semiconductor substrate, and, after forming a resist layer on the surface of the insulating layer, an arbitrary focus within a range of −3.5 μm or more and less than 0 μm by a reduced projection exposure method. Exposure in a defocused state of the value of and a phenomenon of forming a cross-sectional shape of the resist layer opening into an arbitrary taper shape, and an etching rate ratio between the insulating layer and the resist layer using the resist layer as a mask. In the range of 10 to 15 to anisotropically etch the insulating layer to form a tapered through hole in the insulating layer at the opening position of the resist layer.
次に、本発明を図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を工程順に示
す断面図である。1 (a) to 1 (d) are sectional views showing an embodiment of the present invention in the order of steps.
先ず、同図（ａ）のように、半導体基板、例えばシリコ
ン基板１の上にCVD法等を用いてボロンリン酸ガラス（B
PSG）からなる絶縁層２を厚さ1.0〜1.5μｍに成長させ
る。その上で、この絶縁層２上にフォトレジスト、例え
ばOFPR−800C（商品名：東京応化社製）を塗布してポジ
型フォトレジスト層３を形成しかつ同図（ｂ）のように
縮小投影露光法によりフォーカスを−3.5μｍ以上０μ
ｍ未満の範囲の任意の値のデフォーカス状態で露光しか
つ現像して所望するコンタクト孔の形状パターンに57〜
80゜のテーパー角を有する開孔４を形成する。開孔４の
形成後は、乾燥空気雰囲気で約30分間のポストベークを
行う。ポストベークの温度は100〜130℃の範囲内の所要
の温度に設定し、±５℃の精度で温度を制御する。First, as shown in FIG. 1A, a boron phosphate glass (B) is formed on a semiconductor substrate, for example, a silicon substrate 1 by using a CVD method or the like.
An insulating layer 2 made of PSG) is grown to a thickness of 1.0 to 1.5 μm. Then, a photoresist, for example, OFPR-800C (trade name: manufactured by Tokyo Ohka Co., Ltd.) is coated on the insulating layer 2 to form a positive type photoresist layer 3 and reduced projection is performed as shown in FIG. Focus is -3.5 μm or more by exposure method
It is exposed to light in a defocused state of an arbitrary value within the range of less than m and is developed to form a desired contact hole shape pattern 57-
An aperture 4 having a taper angle of 80 ° is formed. After the opening 4 is formed, post bake is performed in a dry air atmosphere for about 30 minutes. The temperature of post bake is set to the required temperature within the range of 100 to 130 ° C, and the temperature is controlled with an accuracy of ± 5 ° C.
続いて、弗素系ガスを使用した反応性イオンエッチング
法又は弗素系ガスを使用した平行平板プラズマエッチン
グ法により、前記レジスト層３をマスクとして絶縁層２
をエッチングし透孔５を形成する。この時のエッチング
条件は、プラズマ励起周波数が13.56MHz,高周波電力が8
50〜950W,O2ガス流量が４〜8cc/min,CHF3ガス流量が15
〜25cc/min,エッチング中の反応室内の圧力が７〜13Pa,
基板冷却温度が10〜15℃である。この条件により、絶縁
層２とレジスト層３とのエッチング選択比を10〜15の範
囲の所望の値に設定できる。Subsequently, the insulating layer 2 is masked with the resist layer 3 by a reactive ion etching method using a fluorine-based gas or a parallel plate plasma etching method using a fluorine-based gas.
To form the through holes 5. The etching conditions at this time are as follows: plasma excitation frequency 13.56MHz, high frequency power 8
50 to 950W, O 2 gas flow rate is 4 to 8cc / min, CHF 3 gas flow rate is 15
~ 25cc / min, pressure in the reaction chamber during etching is 7 ~ 13Pa,
Substrate cooling temperature is 10 ~ 15 ℃. Under this condition, the etching selection ratio between the insulating layer 2 and the resist layer 3 can be set to a desired value within the range of 10 to 15.
透孔５を開口後、レジスト層３を除去し、アルミを被着
し配線層６を形成する。After opening the through hole 5, the resist layer 3 is removed and aluminum is applied to form a wiring layer 6.
第４図は本発明の他の実施例の断面図である。シリコン
基板41上に形成された絶縁層42を形成したアルミ等の配
線層46を形成する。その後、前記第１図の実施例と同様
にこの配線層46上にレジストを塗布し、縮小投影露光法
によりフォーカスを任意のデフォーカス状態で露光しか
つ現象して所望するテーパー状のレジスト層43を形成す
る。その後、このレジスト層43をマスクにしてBCl3＋CC
l4＋CF4系の混合ガスを用いる反応性イオンエッチング
を行ない、テーバー状に配線層46′がエッチングされ
る。さらにレジスト層43′を除去しテーパー状の配線層
46′を得る。本実施例では、アルミ等の配線層テーパー
状に形成可能なため、平坦な多層配線構造を実現できる
利点がある。FIG. 4 is a sectional view of another embodiment of the present invention. A wiring layer 46 of aluminum or the like having an insulating layer 42 formed on a silicon substrate 41 is formed. Thereafter, as in the embodiment of FIG. 1, a resist is applied on the wiring layer 46, the focus is exposed in an arbitrary defocus state by the reduction projection exposure method, and a desired tapered resist layer 43 is generated. To form. Then, using this resist layer 43 as a mask, BCl 3 + CC
Reactive ion etching using a mixed gas of l 4 + CF 4 system is performed to etch the wiring layer 46 ′ in a taber shape. Further, the resist layer 43 'is removed to form a tapered wiring layer.
Get 46 '. In the present embodiment, since the wiring layer such as aluminum can be formed in a tapered shape, there is an advantage that a flat multilayer wiring structure can be realized.
以上説明したように本発明は、絶縁層上にレジスト層の
開口断面をテーパー状に形成し、このレジスト層をマス
クとしかつ絶縁層とレジスト層のエッチング速度比を所
要の範囲、好ましくは10〜15の範囲を保持したままで異
方性エッチングとして絶縁層をエッチングし、レジスト
層の開口位置の絶縁層にテーパー状の透孔を開設してい
るので、バラツキの大きい湿式エッチングを不要とし、
半導体基板へのプラズマダメージを抑制して素子特性へ
の悪影響を防止できるとともに、絶縁層の全厚さに亘っ
て緩やかな傾斜の透孔を形成でき、上側導電層における
段切れを防止して半導体装置の信頼性を向上できる。As described above, the present invention forms the opening cross section of the resist layer on the insulating layer in a tapered shape, and uses the resist layer as a mask and the etching rate ratio of the insulating layer and the resist layer in a required range, preferably 10 to Since the insulating layer is etched as anisotropic etching while maintaining the range of 15 and a tapered through hole is formed in the insulating layer at the opening position of the resist layer, wet etching with large variation is unnecessary,
It is possible to prevent plasma damage to the semiconductor substrate to prevent adverse effects on device characteristics, and to form through-holes with a gentle slope over the entire thickness of the insulating layer to prevent disconnection in the upper conductive layer. The reliability of the device can be improved.
また、目合・露光時に縮小投影露光装置のフォーカスを
任意の値にすることにより、絶縁層のテーパー角度を68
゜から90゜まで任意に制御することが可能（第３図）で
あり、絶縁層とレジスト層のエッチング速度比を10〜15
の比較的高い範囲で異方性エッチングを行なっているの
で、レジスト後退去によるテーパー形成技術に比べ異方
性エッチングによるレジスト層の損耗を極めて少なくす
ることが可能なため、絶縁層のパターン寸法およびテー
パー角度を精度良く制御することが可能である。In addition, the taper angle of the insulating layer can be adjusted to 68 by adjusting the focus of the reduction projection exposure device to an arbitrary value during eye contact and exposure.
It can be arbitrarily controlled from 90 ° to 90 ° (Fig. 3), and the etching rate ratio between the insulating layer and the resist layer is 10 to 15
Since anisotropic etching is performed in a relatively high range, it is possible to significantly reduce the wear of the resist layer due to anisotropic etching as compared with the taper formation technology by resist receding. It is possible to accurately control the taper angle.
さらに、従来のように等方性エッチングと異方エッチン
グの両工程を必要とすることなく、透孔製造の工数の削
減を図ることもできる。Further, it is possible to reduce the man-hours for manufacturing the through holes without requiring both the steps of isotropic etching and anisotropic etching as in the conventional case.
第１図（ａ）〜（ｄ）は本発明の製造方法を工程順に示
す断面図、第２図（ａ）〜（ｅ）は従来方法を工程順に
示す断面図、第３図は本発明の製造方法を実施した場合
のステッパーのフォーカスと被エッチング材料の層およ
びレジスト層のテーパー角を示す図、第４図（ａ）〜
（ｄ）は本発明の実施例２を示す断面図である。 1,11,41……半導体基板（シリコン基板）、2,12,42……
絶縁層、3,13,43,43′……レジスト層（ポジ型フォトレ
ジスト）、４……開孔、５……透孔、6,46,46′……配
線層、14……凹部、16……透孔、17……上側導電層、θ
……テーパー角。1 (a) to 1 (d) are sectional views showing the manufacturing method of the present invention in the order of steps, FIGS. 2 (a) to 2 (e) are sectional views showing the conventional method in the order of steps, and FIG. The figure which shows the focus of a stepper at the time of implementing a manufacturing method, and the taper angle of a layer of a material to be etched and a resist layer, FIG.
(D) is sectional drawing which shows Example 2 of this invention. 1,11,41 …… Semiconductor substrate (silicon substrate), 2,12,42 ……
Insulating layer, 3,13,43,43 '... Resist layer (positive photoresist), 4 ... Open hole, 5 ... Through hole, 6,46,46' ... Wiring layer, 14 ... Recessed portion, 16: through hole, 17: upper conductive layer, θ
... taper angle.
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 ５２６ Ｚ Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location 526 Z
Claims (1)
する工程と、前記絶縁層の表面にレジスト層を形成した
後に、縮小投影露光法によりフォーカスを−3.5μｍ以
上０μｍ未満の範囲の任意の値のデフォーカス状態で露
光しかつ現象して前記レジスト層開口の断面形状を任意
のテーパー状に形成する工程と、このレジスト層をマス
クとして、前記絶縁層と前記レジスト層とのエッチング
速度比が10〜15の範囲で前記絶縁層を異方性エッチング
してレジスト層の開口位置の絶縁層にテーパー状の透孔
を開設する工程とを含むことを特徴とする縮小投影露光
法によるテーパー形成方法。1. A step of forming an insulating layer on the surface of a one-conductivity-type semiconductor substrate, and, after forming a resist layer on the surface of the insulating layer, a focus of -3.5 μm or more and less than 0 μm is obtained by reduction projection exposure. Exposing in a defocused state of an arbitrary value and phenomenon to form a sectional shape of the resist layer opening into an arbitrary taper shape; and an etching rate of the insulating layer and the resist layer using the resist layer as a mask A step of anisotropic projection of the insulating layer in the range of 10 to 15 to form a tapered through hole in the insulating layer at the opening position of the resist layer. Forming method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62097758A JPH07107901B2 (en) | 1987-04-20 | 1987-04-20 | Tape forming method by reduction projection exposure method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62097758A JPH07107901B2 (en) | 1987-04-20 | 1987-04-20 | Tape forming method by reduction projection exposure method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63261836A JPS63261836A (en) | 1988-10-28 |
| JPH07107901B2 true JPH07107901B2 (en) | 1995-11-15 |
Family
ID=14200777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62097758A Expired - Lifetime JPH07107901B2 (en) | 1987-04-20 | 1987-04-20 | Tape forming method by reduction projection exposure method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07107901B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02205314A (en) * | 1989-02-03 | 1990-08-15 | Rohm Co Ltd | Manufacture of semiconductor device |
| US6159660A (en) * | 1997-02-03 | 2000-12-12 | Taiwan Semiconductor Manufacturing Company Ltd. | Opposite focus control to avoid keyholes inside a passivation layer |
| KR100363642B1 (en) * | 1999-11-11 | 2002-12-05 | 아남반도체 주식회사 | Method for forming contact hole of semiconductor devices |
| JP4244771B2 (en) * | 2003-05-29 | 2009-03-25 | パナソニック株式会社 | Method for measuring focus deviation and exposure method |
| WO2012096010A1 (en) * | 2011-01-14 | 2012-07-19 | 三菱電機株式会社 | Method of manufacturing semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5984529A (en) * | 1982-11-08 | 1984-05-16 | Nippon Denso Co Ltd | Forming method of pattern |
| JPS61166130A (en) * | 1985-01-18 | 1986-07-26 | Matsushita Electronics Corp | Formation of photoresist pattern |
-
1987
- 1987-04-20 JP JP62097758A patent/JPH07107901B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63261836A (en) | 1988-10-28 |
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