JPS6155939A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6155939A JPS6155939A JP17743984A JP17743984A JPS6155939A JP S6155939 A JPS6155939 A JP S6155939A JP 17743984 A JP17743984 A JP 17743984A JP 17743984 A JP17743984 A JP 17743984A JP S6155939 A JPS6155939 A JP S6155939A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- field
- elements
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に係わり、特に微細な
素子分離の可能なMOa型半導体装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a MOa type semiconductor device that allows fine element isolation.
従来、半導体素子や集積回路素子は、その素子特性の向
上と高集積化の為、素子の縮小化が進んでいる。各々の
チップ上の膨大な数のデノ《イスをチップ上で互いに電
気的に絶縁・分離するのに必要なのが素子分離技術でら
る。素子分離技術の重要な要件は、分離に必要な面積を
できるだけ小さくして、チップ面積を有効に能動素子の
ためlc*供することでらる。さらに分離後に配線をほ
どこすことを考えれば、急峻な段差がない方が良い。2. Description of the Related Art Conventionally, semiconductor devices and integrated circuit devices have been becoming smaller in size due to improved device characteristics and higher integration. Element isolation technology is required to electrically insulate and separate the huge number of devices on each chip from each other. An important requirement for device isolation technology is to minimize the area required for isolation so that the chip area can be effectively dedicated to active devices. Furthermore, considering that wiring will be applied after separation, it is better to have no steep steps.
以上の様々観点から、従来の素子分離技術の主流でおる
チツ化硅素膜を利用した選択酸化法では分離領域が素子
領域に鳥のくちばし状に侵入し素子領域の有効面積が減
少するという欠点が.1新しい素子分離方法がいくつか
提案されている0その一例として埋込酸化膜による素子
分離方法第2図を用いて説明する。From the various viewpoints mentioned above, the selective oxidation method using a silicon dioxide film, which is the mainstream of conventional device isolation technology, has the disadvantage that the isolation region invades the device region in a bird's beak shape, reducing the effective area of the device region. .. 1. Several new element isolation methods have been proposed. 0 An example of this is a method of element isolation using a buried oxide film, which will be explained with reference to FIG.
面方位(100)のP型シリコン基板(1)ニ水酸化カ
リウムのアルコール溶液を用いて面方位(111)の側
面(2)を有する溝を素子分離領域に形成する。この後
OVD法(Ohemical Vapor Depos
ition ) Kよシ二酸化硅素膜(3)を堆積する
(第2図(a))。次に写真蝕刻法によりフォト・レジ
スト(4)を残置し、さら(粘度の低いフォト・レジス
ト(5)を塗布する(第2図(b))。これにフレオン
系ガスを用いた反応性イオン・エツチング法で全面エツ
チングを施し、平坦化する(第2図(C))。しかし、
実際にはレジスト(4)は、写真蝕刻法によシ装置した
ものであるから、例えば第3図(a)に示すようにマス
ク合せが不完全でらると反応性イオン・エツチングを施
しても、エツチング前の形状を反映してフィールド膜(
3)は、平坦にならない(第3図Q)))。フィールド
膜(3)は、この後、数回の弗酸基エツチング液に晒さ
れるのが一般的で膜減シは避けられない。A P-type silicon substrate (1) with a (100) plane orientation is used. A groove having side faces (2) with a (111) plane direction is formed in an element isolation region using an alcohol solution of potassium dihydroxide. After this, OVD method (Ochemical Vapor Depos
tion) Deposit a K silicon dioxide film (3) (FIG. 2(a)). Next, the photoresist (4) is left by photolithography, and then a photoresist (5) with low viscosity is applied (Figure 2 (b)). - Etch the entire surface using an etching method to flatten it (Figure 2 (C)). However,
In reality, the resist (4) is made using a photolithographic method, so if the mask alignment is incomplete, as shown in FIG. The field film (
3) is not flat (Fig. 3 Q))). After this, the field film (3) is generally exposed to a hydrofluoric acid etching solution several times, and thinning of the film is unavoidable.
フィールド膜が薄くなると間接素子との絶縁の効果が充
分に得られない。閘、フィールド領域の面積を大きくと
シ絶縁性の確保を図ることは前述のように高集積化の観
点から考えて好ましくない。If the field film becomes thin, sufficient insulation effect from indirect elements cannot be obtained. As mentioned above, it is undesirable to increase the area of the lock and field regions to ensure insulation from the viewpoint of high integration.
本発明の目的は、上記問題を解決し、素子の縮小化を実
現するとともに、容易な工程で再現性の高い素子分離を
行なう半導体装置の製造方法を提供することにbる。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned problems, achieves miniaturization of devices, and performs device separation with easy steps and high reproducibility.
本発明の骨子は半導体基板上に絶縁膜を形成した後、そ
の凹部に残置させるフォト・レジスト膜に再度液化可能
なものを用いることにより、荒いマスク合せ精度にもか
かわらず、高い平坦性を有する素子分離構造を実現する
こと[6る。これは例えば残置したレジスト膜を高温に
晒し液化し、重力及び表面張力で絶縁膜のくぼみに平坦
に埋め込み、これを例えば紫外線照射によシ硬化させ、
これを反応性イオン・エツチングにより一様にエツチン
グすることにより実現できる。The gist of the present invention is that after an insulating film is formed on a semiconductor substrate, a photoresist film left in the recesses is made of a material that can be liquefied again, thereby achieving high flatness despite rough mask alignment accuracy. Realizing an element isolation structure [6. For example, the remaining resist film is exposed to high temperature and liquefied, buried flat in the depression of the insulating film by gravity and surface tension, and then cured by, for example, UV irradiation.
This can be achieved by uniformly etching using reactive ion etching.
本発明によれば、素子を微細化した場合にも制御性良く
、フィールド絶縁膜を平坦化し良好な素子分離特性可能
ならしめる。また、写真蝕刻工程のマスク合せ精度に対
する要求が緩和され、安価で容易なマスク合せが可能と
なる。According to the present invention, even when the device is miniaturized, the field insulating film can be flattened with good controllability and good device isolation characteristics can be achieved. In addition, the requirements for mask alignment accuracy in the photolithography process are relaxed, and mask alignment becomes possible at low cost and easy.
以下本発明の具体的実施例について、第1図を用い説明
する。先ず、面方位(100) 、比抵抗5〜10Ω−
傷のP型シリコン単結晶基板(6)上に耐エツチングi
スク兼、耐イオン注入マスクとして例えば4000Aの
二酸化硅素膜(7)を形成し1、これを素子領域にのみ
残して、反応性イオン・エツチング法によシ、フィール
ド領域vcO,8μm程度の溝を形成する。続いてB+
イオンを50Kev、 I X 10’ ” an−”
でイオン注入し、チャネルストッパーとなるPit8)
を形成する(第1図(a))。次に酸化膜(力を除去し
た後、基板全面にOVD法による二酸化硅素膜a0を溝
の深さ0.8μm又はこれより厚く堆積する。この後、
酸化膜C11表面の凹部に、高温で液体となり紫外光で
硬化する特性を有するフォト・レジスト膜(9)を写真
蝕刻法で運択的に形成する。凹部を平坦にこのフォト・
レジストで埋め込むためには7オト・レジスト膜(9)
の体積等の制御が重要でちる。A specific embodiment of the present invention will be described below with reference to FIG. First, plane orientation (100), specific resistance 5~10Ω-
Etching resistant i on scratched P-type silicon single crystal substrate (6)
For example, a silicon dioxide film (7) of 4000A is formed as a mask and an ion implantation-resistant mask1, and a trench of about 8 μm is formed in the field region vcO by reactive ion etching, leaving this film only in the element region. Form. followed by B+
ion at 50Kev, I x 10'"an-"
ion implantation to become a channel stopper (Pit8)
(Fig. 1(a)). Next, after removing the oxide film, a silicon dioxide film a0 is deposited on the entire surface of the substrate by the OVD method to a groove depth of 0.8 μm or thicker. After this,
A photoresist film (9), which has the property of becoming liquid at high temperatures and hardening with ultraviolet light, is selectively formed in the recesses on the surface of the oxide film C11 by photolithography. This photo flattens the concave part.
In order to embed with resist, 7 oto resist film (9)
It is important to control the volume etc.
実際には、フォト・レジスト(9)の膜厚を1.5わる
いは1.8μmと厚くし凹部の比較的狭い面積に形成す
るようにし、た方がマスク合せの合ぜ誤差は犬きくとれ
る(第1図(b))。In reality, the photoresist (9) should be made as thick as 1.5 or 1.8 μm to form it in a relatively narrow area of the recess, and the alignment error in mask alignment can be minimized. (Figure 1(b)).
この後、基板の加工面を上に向け、130’Oで15分
間放置しフォト・レジスト(9)を液化する。次にこれ
を室温に冷却し紫外線ランプで硬化する(第1図(C)
)。以上のようにして表面をなだらかにした後、全面を
フレオン系ガスを用いた反応性イオン・エツチング法に
よりエツチングする。この時のエツチング条件は二酸化
硅素膜<1(Iとフォト・レジスト膜(9)のエツチン
グ速度が同等か、二酸化硅素膜(11の方が例えば2倍
程度速くなるように設定する。Thereafter, the processed surface of the substrate is turned upward and left at 130'O for 15 minutes to liquefy the photoresist (9). Next, this is cooled to room temperature and cured with an ultraviolet lamp (Figure 1 (C)).
). After smoothing the surface as described above, the entire surface is etched by reactive ion etching using Freon gas. The etching conditions at this time are set so that the etching speed of the silicon dioxide film <1 (I and the photoresist film (9) is the same, or the silicon dioxide film (11) is about twice as fast as the etching rate of the photoresist film (9).
この結果、フィールド領域ではレジスト膜(9)がエツ
チングに対するストッパの役割シをし、素子形成領域の
基板表面を露出するまでエツチングして不要なレジスト
ff!除去すると、二酸化硅素膜Uωがフィールド領域
に平坦かつ完全に埋め込まれる(第1図は))。As a result, in the field region, the resist film (9) acts as a stopper against etching, and etches until the substrate surface in the element formation region is exposed, leaving unnecessary resist ff! Upon removal, the silicon dioxide film Uω is flat and completely embedded in the field region (as shown in FIG. 1).
この様にして形成さねた素子分離構造は隣接素子との絶
縁が良く、従来の方法に比べ微細化が容易であった。The element isolation structure formed in this manner has good insulation from adjacent elements and is easier to miniaturize than conventional methods.
第1図は本発明における一実施例の製造工程を示す断面
図、第2図は従来の埋込酸化膜による素子分離をf’t
とこい1MO8型半導体装置の製造工程例を示す図、第
3図はマスク合せが不完全な例を示すyi面図でらる。
1・・・P型シリコン基板、2・・・基机側面、3・・
・二酸化硅素膜(OVD法)、4・・レジスト膜、5・
・粘度の低いレジスト膜、6・・・P型シリコン基板、
7・・・二酸化硅素膜(熱酸化)、8・・・P+層(B
+イオン注入)、9・・・レジスト膜、lO・・・二酸
化硅素膜C0VD法)。
(7317)代理人弁理士 則 近 憲 佑 (ほか1
名)−Q
第2図
第3図FIG. 1 is a cross-sectional view showing the manufacturing process of one embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the manufacturing process of an embodiment of the present invention.
FIG. 3 is a diagram showing an example of the manufacturing process of a 1MO8 type semiconductor device, and is a yi plane view showing an example where mask alignment is incomplete. 1... P-type silicon substrate, 2... Base desk side, 3...
・Silicon dioxide film (OVD method), 4...Resist film, 5.
・Low viscosity resist film, 6...P-type silicon substrate,
7...Silicon dioxide film (thermal oxidation), 8...P+ layer (B
+ion implantation), 9...resist film, lO...silicon dioxide film C0VD method). (7317) Representative Patent Attorney Noriyuki Chika (and 1 others)
name)-Q Figure 2 Figure 3
Claims (3)
と、基板上にフィールド絶縁膜を堆積する工程と、フィ
ールド領域の一部にレジスト膜を形成する工程と、この
レジスト膜を再融解ならびに凝固する工程と、絶縁膜と
、レジスト膜を一様に蝕刻する工程とを備えたことを特
徴とする半導体装置の製造方法。(1) A step of forming a groove in the field region of a semiconductor substrate, a step of depositing a field insulating film on the substrate, a step of forming a resist film in a part of the field region, and remelting and solidification of this resist film. 1. A method of manufacturing a semiconductor device, comprising: a step of uniformly etching an insulating film and a resist film.
縁膜として二酸化硅素膜を用いたことを特徴とする前記
特許請求の範囲第1項記載の半導体装置の製造方法。(2) A method of manufacturing a semiconductor device according to claim 1, characterized in that single crystal silicon is used as the semiconductor substrate and a silicon dioxide film is used as the field insulating film.
形成することを特徴とする前記特許請求の範囲第1項記
載の半導体装置の製造方法。(3) A method of manufacturing a semiconductor device according to claim 1, characterized in that a groove having an inclination is formed in a field region of a semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17743984A JPS6155939A (en) | 1984-08-28 | 1984-08-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17743984A JPS6155939A (en) | 1984-08-28 | 1984-08-28 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6155939A true JPS6155939A (en) | 1986-03-20 |
Family
ID=16030961
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17743984A Pending JPS6155939A (en) | 1984-08-28 | 1984-08-28 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6155939A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0334268A2 (en) * | 1988-03-24 | 1989-09-27 | Motorola, Inc. | Means of forming planar isolation |
US5175122A (en) * | 1991-06-28 | 1992-12-29 | Digital Equipment Corporation | Planarization process for trench isolation in integrated circuit manufacture |
JPH08107115A (en) * | 1994-10-04 | 1996-04-23 | Nec Corp | Manufacture of semiconductor device |
-
1984
- 1984-08-28 JP JP17743984A patent/JPS6155939A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0334268A2 (en) * | 1988-03-24 | 1989-09-27 | Motorola, Inc. | Means of forming planar isolation |
US5175122A (en) * | 1991-06-28 | 1992-12-29 | Digital Equipment Corporation | Planarization process for trench isolation in integrated circuit manufacture |
JPH08107115A (en) * | 1994-10-04 | 1996-04-23 | Nec Corp | Manufacture of semiconductor device |
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