JPH04303943A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04303943A JPH04303943A JP3093363A JP9336391A JPH04303943A JP H04303943 A JPH04303943 A JP H04303943A JP 3093363 A JP3093363 A JP 3093363A JP 9336391 A JP9336391 A JP 9336391A JP H04303943 A JPH04303943 A JP H04303943A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- interlayer film
- film
- photoresist
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 239000004065 semiconductor Substances 0.000 title description 5
- 239000010410 layer Substances 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に多層配線間の接続構造を製造する方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a connection structure between multilayer interconnections.
【０００２】0002
【従来の技術】従来の多層配線を有する半導体装置にお
ける異なる配線層間を接続する方法を図６を用いて説明
する。先ず、図６（ａ）のように、絶縁膜１上に第１の
配線２を全面に形成し、この上に第１の配線領域となる
パターンでフォトレジスト３を形成する。次に、図６（
ｂ）のように、フォトレジスト３をマスクとして第１の
配線２を異方性エッチングし、第１の配線のパターンを
形成する。2. Description of the Related Art A method for connecting different wiring layers in a conventional semiconductor device having multilayer wiring will be described with reference to FIG. First, as shown in FIG. 6A, a first wiring 2 is formed on the entire surface of an insulating film 1, and a photoresist 3 is formed thereon in a pattern that will become a first wiring area. Next, Figure 6 (
As shown in b), the first wiring 2 is anisotropically etched using the photoresist 3 as a mask to form a first wiring pattern.
【０００３】次に、図６（ｃ）のように、フォトレジス
ト３を除去し、全面に層間膜５を形成し、第１の配線２
の所定の領域上の層間膜５にビアホール８を開孔する。
次に、図６（ｄ）のように、全面に第２の配線６として
アルミニウムをスパッタリング法により形成し、所定の
形状のフォトレジストをマスクとして第２の配線を異方
性エッチングすることにより、第１の配線２と第２の配
線６とがビアホール８を通じて接続されることになる。Next, as shown in FIG. 6(c), the photoresist 3 is removed, an interlayer film 5 is formed on the entire surface, and the first wiring 2 is formed.
A via hole 8 is formed in the interlayer film 5 on a predetermined region of the via hole 8 . Next, as shown in FIG. 6(d), aluminum is formed as a second wiring 6 on the entire surface by sputtering, and the second wiring is anisotropically etched using a photoresist in a predetermined shape as a mask. The first wiring 2 and the second wiring 6 are connected through the via hole 8.
【０００４】0004
【発明が解決しようとする課題】この従来の多層配線間
の接続方法では、第１の配線と第２の配線が接続される
ビアホール８の部位においては、層間膜５の段部によっ
て第２の配線６のカバレッジ性が悪く、第２の配線６の
膜厚が平坦部の膜厚に比べ非常に薄くなる。このため、
第２の配線６のビアホール８における配線の断面積が小
さくなり、エレクトロマイグレーションに弱くなり、或
いは抵抗が高くなって動作速度の低下をもたらすという
問題が生じる。このような段部における第２の配線６の
形状を良くするためには、ビアホール８の上部を等方性
エッチングで開孔し、或いは層間膜５の膜厚を小さくす
るという対策が考えられるが、前者は第２の配線の微細
化にとって不利であり、また後者は第２の配線の容量が
大きくなり、動作速度の低下につながるという別な問題
が生じることになる。本発明の目的は動作速度を高めか
つ微細化を可能とした半導体装置の製造方法を提供する
ことにある。[Problems to be Solved by the Invention] In this conventional method for connecting multilayer wiring, in the region of the via hole 8 where the first wiring and the second wiring are connected, the step of the interlayer film 5 connects the second wiring. The coverage of the wiring 6 is poor, and the thickness of the second wiring 6 is much thinner than the thickness of the flat portion. For this reason,
A problem arises in that the cross-sectional area of the second wiring 6 in the via hole 8 becomes small, making it susceptible to electromigration or increasing the resistance, resulting in a reduction in operating speed. In order to improve the shape of the second wiring 6 in such a stepped portion, it is possible to open the upper part of the via hole 8 by isotropic etching or to reduce the thickness of the interlayer film 5. The former is disadvantageous for miniaturization of the second wiring, and the latter causes another problem in that the capacitance of the second wiring increases, leading to a reduction in operating speed. An object of the present invention is to provide a method for manufacturing a semiconductor device that increases operating speed and enables miniaturization.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、１層または複数の層よりなる第１の配線を所
定の形状に形成する工程と、この第１の配線の一部をマ
スク材で覆ってこれを膜厚の途中までエッチング除去し
、この第１の配線の一部に柱状突起を形成する工程と、
第１の配線を覆うように全面に層間膜を形成する工程と
、前記柱状突起の上面のみが表れるまで前記層間膜をエ
ッチングする工程と、前記柱状突起の一部または全部を
覆うように前記層間膜上に第２の配線を形成する工程と
を含んでいる。[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a step of forming a first wiring made of one layer or a plurality of layers into a predetermined shape, and a step of forming a part of the first wiring. Covering with a mask material and etching away the mask material to the middle of the film thickness to form a columnar protrusion on a part of the first wiring;
a step of forming an interlayer film on the entire surface so as to cover the first wiring; a step of etching the interlayer film until only the upper surface of the columnar projection is exposed; and a step of etching the interlayer film so as to cover part or all of the columnar projection. The method includes a step of forming a second wiring on the film.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。図１及び図２は本発明の第１実施例を工程順に示す
断面図であり、図１は第１の配線を形成する工程を示し
、図２は第２の配線を形成する工程を示している。先ず
、図１（ａ）のように、絶縁膜１上に第１の配線２とし
てアルミニウム膜を約２μｍ形成する。このアルミニウ
ム膜の膜厚は、第１の配線として最終的に必要な膜厚よ
りは厚くしておく。そして、この第１の配線上に所定の
形状のフォトレジスト３を形成する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. 1 and 2 are cross-sectional views showing the first embodiment of the present invention in the order of steps. FIG. 1 shows the step of forming the first wiring, and FIG. 2 shows the step of forming the second wiring. There is. First, as shown in FIG. 1(a), an aluminum film having a thickness of about 2 μm is formed as a first wiring 2 on an insulating film 1. The thickness of this aluminum film is set to be thicker than the thickness ultimately required for the first wiring. Then, a photoresist 3 having a predetermined shape is formed on this first wiring.
【０００７】次に、図１（ｂ）のように、フォトレジス
ト３をマスクとして第１の配線２を異方性エッチングし
、第１の配線を形成する。そして、フォトレジスト３を
除去した上で、図１（ｃ）のように第１の配線と第２の
配線を接続すべき領域のみにフォトレジスト４を形成す
る。次に、図１（ｄ）のように、フォトレジスト４をマ
スクとして第１の配線２を異方性エッチングする。この
時、第１の配線の膜厚がおよそ１μｍになるように途中
でエッチングを止める。この結果、第１の配線と第２の
配線とが接続する予定領域の第１の配線に約１μｍの柱
状突起７が形成される。Next, as shown in FIG. 1B, the first wiring 2 is anisotropically etched using the photoresist 3 as a mask to form a first wiring. Then, after removing the photoresist 3, a photoresist 4 is formed only in the region where the first wiring and the second wiring are to be connected, as shown in FIG. 1(c). Next, as shown in FIG. 1D, the first wiring 2 is anisotropically etched using the photoresist 4 as a mask. At this time, etching is stopped midway so that the film thickness of the first wiring becomes approximately 1 μm. As a result, a columnar protrusion 7 of about 1 μm is formed on the first wire in the area where the first wire and the second wire are to be connected.
【０００８】次に、第２の配線を形成する工程として、
図２（ａ）のように、フォトレジスト４を除去した後に
、全面に層間膜５を形成する。層間膜は例えば化学的気
相成長法による酸化膜または塗布膜またはこれらを組み
合わせた構成が可能である。次に、図２（ｂ）のように
、第１の配線の上面が現れる程度に層間膜５をエッチン
グする。このエッチングは、層間膜５の表面が平坦に近
い場合は、全面エッチングバックを行えばよい。また層
間膜５の表面が下地の第１の配線２を反映して凹凸であ
る場合は、例えばレジスト等の膜を塗布し表面を平坦に
してからエッチングバックし、後で塗布膜を除去すれば
よい。Next, as a step of forming the second wiring,
As shown in FIG. 2(a), after removing the photoresist 4, an interlayer film 5 is formed on the entire surface. The interlayer film can be, for example, an oxide film formed by chemical vapor deposition, a coating film, or a combination thereof. Next, as shown in FIG. 2(b), the interlayer film 5 is etched to such an extent that the upper surface of the first wiring is exposed. This etching may be performed by etching back the entire surface if the surface of the interlayer film 5 is nearly flat. In addition, if the surface of the interlayer film 5 is uneven reflecting the underlying first wiring 2, for example, apply a film such as a resist to make the surface flat, then etch back, and remove the applied film later. good.
【０００９】しかる上で、図２（ｃ）のように、全面に
第２の配線６としてアルミニウム膜を１μｍ形成し、フ
ォトレジストをマスクとして異方性エッチングすること
により第１の配線２と第２の配線６とが、第１の配線か
ら形成された柱状突起７を介して接続されることになる
。尚、図３は、第１の配線２と第２の配線６とが接続す
る領域の平面図であり、そのＡ−Ａ断面が図２（ｃ）に
相当する。Then, as shown in FIG. 2C, an aluminum film of 1 μm thickness is formed as the second wiring 6 on the entire surface, and anisotropic etching is performed using a photoresist as a mask to form the first wiring 2 and the second wiring 6. The second wiring 6 is connected to the second wiring 6 via the columnar protrusion 7 formed from the first wiring. Note that FIG. 3 is a plan view of a region where the first wiring 2 and the second wiring 6 are connected, and the AA cross section thereof corresponds to FIG. 2(c).
【００１０】この実施例では第２の配線６は平坦部に形
成されるため、第２の配線の膜厚が薄くなる箇所がなく
、電気的信頼性及び電気的性能は改善される。また、第
１の配線２と第２の配線６の接続部のビアホール部は垂
直段であるため、ビアホールに対する第２の配線の覆い
の余裕は小さくてすみ、第２の配線の微細化、高密度化
を容易にするという利点を有する。In this embodiment, since the second wiring 6 is formed in a flat area, there is no part where the thickness of the second wiring becomes thin, and electrical reliability and electrical performance are improved. In addition, since the via hole at the connection between the first wiring 2 and the second wiring 6 is a vertical step, there is only a small margin for covering the via hole with the second wiring, which makes it possible to miniaturize and heighten the second wiring. It has the advantage of facilitating densification.
【００１１】図４及び図５は本発明の第２実施例を工程
順に示す断面図である。先ず、第１の配線の形成工程は
、図４（ａ）のように、絶縁膜１上に第１層配線２Ａと
してアルミニウム膜を１μｍ形成する。更に、この上に
第２層配線２Ｂとしてチタン膜を ０．１μｍ、第３層
配線２Ｃとしてアルミニウム膜を１μｍ形成する。そし
て、第１層目の配線の形状に形成したフォトレジスト３
を形成する。その上で、図４（ｂ）のように、フォトレ
ジストをマスクとして第３層配線２Ｃ、第２層配線２Ｂ
、第１層配線２Ａを異方性エッチングし、第１の配線２
を形成する。FIGS. 4 and 5 are cross-sectional views showing the second embodiment of the present invention in the order of steps. First, in the step of forming the first wiring, as shown in FIG. 4A, an aluminum film of 1 μm thickness is formed as the first layer wiring 2A on the insulating film 1. Furthermore, a titanium film with a thickness of 0.1 μm is formed as a second layer wiring 2B, and an aluminum film is formed with a thickness of 1 μm as a third layer wiring 2C. Then, a photoresist 3 is formed in the shape of the first layer wiring.
form. Then, as shown in FIG. 4(b), the third layer wiring 2C and the second layer wiring 2B are formed using a photoresist as a mask.
, the first layer wiring 2A is anisotropically etched, and the first wiring 2A is anisotropically etched.
form.
【００１２】次に、図４（ｃ）のように、フォトレジス
トを除去し、改めて接続を行う領域にのみフォトレジス
ト４を形成し、このフォトレジスト４をマスクとして、
図４（ｄ）のように、第３層配線２Ｃのみを異方性エッ
チングする。エッチングは第３層配線２Ｃと第２層配線
２Ｂとの選択比が十分大きくなるような条件で行えば、
容易に第３層配線２Ｃのみをエッチングすることができ
る。その後、フォトレジスト４を除去すると、第１の配
線と第２の配線とが接続する領域にのみ、第３層配線２
Ｃで形成された柱状突起７が形成されることになる。Next, as shown in FIG. 4(c), the photoresist is removed and a photoresist 4 is formed only in the area where connections are to be made again, and this photoresist 4 is used as a mask.
As shown in FIG. 4(d), only the third layer wiring 2C is anisotropically etched. If the etching is performed under conditions such that the selectivity between the third layer wiring 2C and the second layer wiring 2B is sufficiently large,
Only the third layer wiring 2C can be easily etched. After that, when the photoresist 4 is removed, the third layer wiring 2 is removed only in the area where the first wiring and the second wiring connect.
A columnar projection 7 made of C is formed.
【００１３】次に、図５（ａ）のように、全面に層間膜
５を形成する。層間膜は第１実施例と同様に、例えば化
学的気相成長法による酸化膜、または塗布膜、またはこ
れらを組み合わせた構成が可能である。そして、図５（
ｂ）のように、柱状突起７の上面が現れる程度に層間膜
５をエッチングする。エッチングは第１実施例に述べた
方法を用いればよい。Next, as shown in FIG. 5(a), an interlayer film 5 is formed on the entire surface. As in the first embodiment, the interlayer film can be, for example, an oxide film formed by chemical vapor deposition, a coating film, or a combination of these. And Figure 5 (
As shown in b), the interlayer film 5 is etched to such an extent that the upper surfaces of the columnar projections 7 are exposed. For etching, the method described in the first embodiment may be used.
【００１４】次に、全面に第２の配線６として例えばア
ルミニウム膜を１μｍ形成し、フォトレジストをマスク
として異方性エッチングを行い、図５（ｃ）のように、
第２の配線６を形成する。この結果、第１の配線２と第
２の配線６とが、第３層配線２Ｃで形成される柱状突起
７を介して接続されることになる。尚、この第２実施例
では、柱状突起７を形成するための第３層配線２Ｃと第
１層配線２Ａとの間にエッチング速度の小さい第２層金
属層２Ｂを挟んでいるため、第３層配線２Ｃのエッチン
グの際に、下層の第１層配線２Ａをエッチングすること
がなく、第１の配線２の膜厚および柱状突起７の高さは
変動が少なく安定しているという利点を有する。Next, for example, an aluminum film of 1 μm thickness is formed as the second wiring 6 on the entire surface, and anisotropic etching is performed using a photoresist as a mask, as shown in FIG. 5(c).
A second wiring 6 is formed. As a result, the first wiring 2 and the second wiring 6 are connected via the columnar protrusion 7 formed by the third layer wiring 2C. In this second embodiment, since the second layer metal layer 2B having a low etching rate is sandwiched between the third layer wiring 2C and the first layer wiring 2A for forming the columnar protrusions 7, When etching the layer wiring 2C, the underlying first layer wiring 2A is not etched, and the film thickness of the first wiring 2 and the height of the columnar protrusions 7 have the advantage of being stable with little variation. .
【００１５】[0015]
【発明の効果】以上説明したように本発明は、第１の配
線の一部に柱状突起を形成し、この柱状突起を利用して
第２の配線に接続させるように製造を行うので、多層配
線間の接続部における第２の配線の膜厚が薄くなること
がなく、上下の配線の接続部におけるエレクトロマイグ
レーションに対する耐性を平坦部における耐性と同等に
向上させることができる。又、第２の配線が平坦に形成
できるので、この上に更に配線を形成する際にも、その
上層の層間膜及び配線を平坦に形成でき、多層配線を形
成する上で有利となる。又、第１の配線と第２の配線の
接続は、垂直な形状の金属層で構成される柱状突起で行
われることになるため、接続部の面積増大がなく、配線
の微細化，高密度化を容易にするという利点がある。こ
の場合、接続は第１の配線の一部を用いて行われるため
、従来の製造工程をそるまま利用して実現できる効果も
ある。更に、層間膜の膜厚は、第１の配線の異方性エッ
チングが安定にできる範囲内で厚くすることが可能であ
るため配線容量は従来例の １／２〜 １／３程度に低
減でき、素子動作速度の向上につながる効果もある。Effects of the Invention As explained above, the present invention forms a columnar protrusion on a part of the first wiring, and manufactures it by using this columnar protrusion to connect it to the second wiring. The film thickness of the second wiring at the connection portion between the wirings does not become thinner, and the resistance to electromigration at the connection portion between the upper and lower wirings can be improved to the same level as the resistance at the flat portion. In addition, since the second wiring can be formed flat, even when further wiring is formed thereon, the upper interlayer film and the wiring can be formed flat, which is advantageous in forming multilayer wiring. In addition, since the connection between the first wiring and the second wiring is made by a columnar protrusion made of a vertically shaped metal layer, there is no increase in the area of the connection part, and it is possible to miniaturize and high-density wiring. It has the advantage of being easy to implement. In this case, since the connection is made using a part of the first wiring, there is an advantage that the conventional manufacturing process can be used without modification. Furthermore, since the thickness of the interlayer film can be increased within a range that allows stable anisotropic etching of the first wiring, the wiring capacitance can be reduced to about 1/2 to 1/3 of that of the conventional example. This also has the effect of improving device operating speed.
【図１】（ａ）乃至（ｄ）は本発明の第１実施例の第１
の配線の製造方法を工程順に示す断面図である。[Fig. 1] (a) to (d) are first embodiments of the present invention.
FIG. 3 is a cross-sectional view showing the method for manufacturing the wiring in order of steps.
【図２】（ａ）乃至（ｃ）は本発明の第１実施例の第２
の配線の製造方法を工程順に示す断面図である。FIG. 2 (a) to (c) are second embodiments of the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the method for manufacturing the wiring in order of steps.
【図３】本発明の第１実施例の完成状態の平面図であり
、そのＡ−Ａ線断面図が図２（ｃ）に相当する図である
。FIG. 3 is a plan view of the completed state of the first embodiment of the present invention, and a cross-sectional view taken along the line A-A corresponds to FIG. 2(c).
【図４】（ａ）乃至（ｄ）は本発明の第２実施例の第１
の配線の製造方法を工程順に示す断面図である。FIG. 4 (a) to (d) are the first embodiment of the second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the method for manufacturing the wiring in order of steps.
【図５】（ａ）乃至（ｃ）は本発明の第２実施例の第２
の配線の製造方法を工程順に示す断面図である。FIG. 5(a) to (c) are the second embodiment of the second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the method for manufacturing the wiring in order of steps.
【図６】（ａ）乃至（ｄ）は従来の配線構造の製造方法
を工程順に示す断面図である。FIGS. 6(a) to 6(d) are cross-sectional views showing a conventional method for manufacturing a wiring structure in the order of steps;
１ 絶縁膜
２ 第１の配線
２Ａ 第１層配線 ２Ｂ 第２層配線 ２Ｃ
第３層配線
３，４ フォトレジスト
５ 層間膜
６ 第２の配線
７ 柱状突起1 Insulating film 2 First wiring 2A First layer wiring 2B Second layer wiring 2C
Third layer wiring 3, 4 Photoresist 5 Interlayer film 6 Second wiring 7 Columnar projection
Claims (1)
線を所定の形状に形成する工程と、この第１の配線の一
部をマスク材で覆ってこれを膜厚の途中までエッチング
除去し、この第１の配線の一部に柱状突起を形成する工
程と、第１の配線を覆うように全面に層間膜を形成する
工程と、前記柱状突起の上面が表れるまで前記層間膜を
エッチングする工程と、前記柱状突起の一部または全部
を覆うように前記層間膜上に第２の配線を形成する工程
とを含むことを特徴とする半導体装置の製造方法。Claim 1: A step of forming a first wiring made of one or more layers into a predetermined shape, and covering a part of the first wiring with a mask material and etching it away to the middle of the film thickness. Then, a step of forming a columnar projection on a part of the first wiring, a step of forming an interlayer film on the entire surface so as to cover the first wiring, and etching the interlayer film until the upper surface of the columnar projection is exposed. and forming a second wiring on the interlayer film so as to cover part or all of the columnar protrusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3093363A JPH04303943A (en) | 1991-03-30 | 1991-03-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3093363A JPH04303943A (en) | 1991-03-30 | 1991-03-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04303943A true JPH04303943A (en) | 1992-10-27 |
Family
ID=14080210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3093363A Pending JPH04303943A (en) | 1991-03-30 | 1991-03-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04303943A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5773365A (en) * | 1996-05-29 | 1998-06-30 | Nec Corporation | Fabrication process of semiconductor device |
| KR20000028094A (en) * | 1998-10-30 | 2000-05-25 | 김영환 | Method for forming wire for semiconductor device |
| KR20020086098A (en) * | 2001-05-11 | 2002-11-18 | 아남반도체 주식회사 | a contact structure for interconnecting multi-level wires and a method for forming the same |
-
1991
- 1991-03-30 JP JP3093363A patent/JPH04303943A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5773365A (en) * | 1996-05-29 | 1998-06-30 | Nec Corporation | Fabrication process of semiconductor device |
| KR20000028094A (en) * | 1998-10-30 | 2000-05-25 | 김영환 | Method for forming wire for semiconductor device |
| KR20020086098A (en) * | 2001-05-11 | 2002-11-18 | 아남반도체 주식회사 | a contact structure for interconnecting multi-level wires and a method for forming the same |
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