JPH06188679A - Phase shift circuit - Google Patents
Phase shift circuitInfo
- Publication number
- JPH06188679A JPH06188679A JP34183392A JP34183392A JPH06188679A JP H06188679 A JPH06188679 A JP H06188679A JP 34183392 A JP34183392 A JP 34183392A JP 34183392 A JP34183392 A JP 34183392A JP H06188679 A JPH06188679 A JP H06188679A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- phase
- phase shift
- capacitance
- resistance element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、振幅位相変調器、復調
器に使われる移相回路、特に集積回路として構成するに
好適な移相回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase shift circuit used in an amplitude / phase modulator and a demodulator, and more particularly to a phase shift circuit suitable for being configured as an integrated circuit.
【0002】[0002]
【従来の技術】従来の移相回路としては図5に示すよう
なブリッジ型の移相回路がよく使われている。図5にお
いて、抵抗素子52と55は等しい抵抗値とし、容量素
子53と54は等しい容量値とした場合に、抵抗素子5
2を流れる電流I1と容量素子54を流れるI2はそれ
ぞれ振幅、位相とも等しくなる。このとき端子57には
電流I2と同位相の電圧が生じるとともに、端子56に
は電流I1と位相が90°異なる電圧が生ずる。したが
って端子56と57の電位を比較すると、周波数によっ
てそれぞれ振幅が変動するものの、互いに位相が90°
異なる信号を得ることができる。2. Description of the Related Art As a conventional phase shift circuit, a bridge type phase shift circuit as shown in FIG. 5 is often used. In FIG. 5, when the resistance elements 52 and 55 have the same resistance value and the capacitance elements 53 and 54 have the same capacitance value, the resistance element 5
The current I1 flowing through 2 and the current I2 flowing through the capacitive element 54 have the same amplitude and phase. At this time, a voltage having the same phase as the current I2 is generated at the terminal 57, and a voltage having a phase difference of 90 ° from the current I1 is generated at the terminal 56. Therefore, comparing the potentials of the terminals 56 and 57, although the amplitudes vary depending on the frequencies, the phases are 90 ° with respect to each other.
Different signals can be obtained.
【0003】しかし、ブリッジ型の位相回路において
は、ブリッジを構成する抵抗素子、容量素子が等しい場
合には、端子56と57との電位差が正確に90°とな
るものの、現実には抵抗素子、容量素子は誤差を持つた
め、必ずしも値が等しくならず、位相差は90°からず
れてしまう。However, in the bridge type phase circuit, when the resistance element and the capacitance element forming the bridge are equal, the potential difference between the terminals 56 and 57 is exactly 90 °, but in reality, the resistance element, Since the capacitive element has an error, the values are not always equal and the phase difference deviates from 90 °.
【0004】集積回路内部に移相器を実現する場合、素
子の相対誤差は小さいとされるが、相対誤差は加工精度
に依存するので、素子の占有面積が小さくなるほど、相
対誤差が大きくなる傾向にある。したがって精度の良い
移相回路を得るには、占有面積が大きな素子を使う必要
がある。これは高集積化の要請に反する。When implementing a phase shifter inside an integrated circuit, the relative error of the element is considered to be small. However, the relative error depends on the processing accuracy, so that the smaller the occupied area of the element, the larger the relative error. It is in. Therefore, in order to obtain a highly accurate phase shift circuit, it is necessary to use an element having a large occupied area. This goes against the demand for higher integration.
【0005】また端子56、57に接続される次段の回
路により、端子56、57からは電流が流出することと
なるが、それぞれの端子から流れ出る電流の大きさが異
なる場合にも、端子56、57に生ずる電位の位相差は
正確に90°とならない。一般に次段に接続される回路
の入力インピーダンスは等しいとは限らないので、接続
される回路により移相回路の出力位相差の精度が保証で
きなくなる恐れがある。Further, currents flow out from the terminals 56 and 57 due to the next-stage circuit connected to the terminals 56 and 57, but even if the magnitudes of the currents flowing out from the respective terminals are different, , 57, the phase difference of the electric potentials generated is not exactly 90 °. Generally, since the input impedance of the circuit connected to the next stage is not always equal, the accuracy of the output phase difference of the phase shift circuit may not be guaranteed depending on the connected circuit.
【0006】また集積回路内において、占有面積が大き
な容量素子は容量値が大きくなるため、振幅の大きな電
圧を得るためには容量値に比例した大きな電流が必要と
なる。これは低消費電力化の要請にも反する。In an integrated circuit, a capacitance element having a large occupied area has a large capacitance value, so that a large current proportional to the capacitance value is required to obtain a voltage with a large amplitude. This goes against the demand for lower power consumption.
【0007】[0007]
【発明が解決しようとする課題】以上説明したように、
従来のブリッジ型の移相回路においては、ブリッジを構
成する抵抗素子、容量素子の素子値が必ずしも等しくな
らないため、出力される信号の位相差が一定とならない
等の問題があった。本発明においては、素子値の誤差が
出力位相差に影響しない位相回路を提供する。As described above,
In the conventional bridge type phase shift circuit, there is a problem that the phase difference of the output signals is not constant because the element values of the resistance element and the capacitance element forming the bridge are not necessarily equal. The present invention provides a phase circuit in which the error in the element value does not affect the output phase difference.
【0008】[0008]
【課題を解決するための手段】本発明においては、抵抗
素子と、その抵抗素子に直列に接続される容量素子と、
前記抵抗素子の両端に接続される第1の振幅制限回路
と、前記容量素子の両端に接続される第2の振幅制限回
路とで構成されることを特徴とする移相回路を提供す
る。According to the present invention, a resistance element and a capacitance element connected in series with the resistance element,
A phase shift circuit comprising a first amplitude limiting circuit connected to both ends of the resistance element and a second amplitude limiting circuit connected to both ends of the capacitance element.
【0009】また、第1の発明において、入力信号を前
記第1、第2の振幅制限回路の動作に必要な振幅にまで
増幅する入力信号増幅回路を備えたことを特徴とする移
相回路を提供する。Also, in the first invention, there is provided a phase shift circuit comprising an input signal amplifier circuit for amplifying an input signal to an amplitude necessary for the operation of the first and second amplitude limiting circuits. provide.
【0010】また、第2の発明においては、抵抗素子
と、その抵抗素子に直列に接続された容量素子と、前記
抵抗素子と前記容量素子との接続点に接続される第1の
緩衝増幅回路と、前記接続点と反対の前記抵抗素子の端
子に接続される第2の緩衝増幅回路と、前記接続点と反
対の前記容量素子の端子に接続される第3の緩衝増幅回
路と、第1の緩衝増幅回路の出力電圧と第2の緩衝増幅
回路の出力電圧の差を入力電圧とする第1の振幅制限回
路と、第1の緩衝増幅回路の出力電圧と第3の緩衝増幅
回路の出力電圧の差を入力電圧とする第2の振幅制限回
路とで構成され、前記第1、第2、第3の緩衝増幅回路
の入力インピーダンスの絶対値が前記第1、第2の振幅
制限回路の入力インピーダンスの絶対値よりも大きいこ
とを特徴とする移相回路を提供する。また、第1、第2
の発明において、前記容量素子の一方の端子を交流的に
接地することを特徴とする移相回路を提供する。Further, in the second invention, the first buffer amplifier circuit is connected to the resistance element, the capacitance element connected in series to the resistance element, and the connection point of the resistance element and the capacitance element. A second buffer amplifier circuit connected to the terminal of the resistance element opposite to the connection point, a third buffer amplifier circuit connected to the terminal of the capacitance element opposite to the connection point, and Amplitude limiting circuit having an input voltage that is the difference between the output voltage of the buffer amplifying circuit and the output voltage of the second buffer amplifying circuit, and the output voltage of the first buffer amplifying circuit and the output of the third buffer amplifying circuit. A second amplitude limiting circuit having a voltage difference as an input voltage, and the absolute values of the input impedances of the first, second and third buffer amplifier circuits are the same as those of the first and second amplitude limiting circuits. Phase shift characterized by being greater than the absolute value of the input impedance To provide the road. Also, the first and second
The invention provides a phase shift circuit in which one terminal of the capacitance element is grounded in an alternating current.
【0011】[0011]
【作用】本発明の移相回路は、抵抗素子と容量素子とを
直列に接続することを特徴とする。直列接続された抵抗
素子と容量素子には振幅と位相とが同一の電流が流れる
ので、この電流の位相を基準として、抵抗素子の両端に
は電流と位相が等しい電圧が発生し、容量素子の両端に
は電流と位相が90°ずれた電圧が発生する。従って抵
抗素子の端子電圧と容量素子の端子電圧とを比較すると
正確に90°位相が異なる信号を生ずることができる。The phase shift circuit of the present invention is characterized in that the resistance element and the capacitance element are connected in series. A current with the same amplitude and phase flows in the resistance element and the capacitance element connected in series, so a voltage with the same current and phase is generated at both ends of the resistance element with the phase of this current as a reference, A voltage with a phase difference of 90 ° from the current is generated at both ends. Therefore, when the terminal voltage of the resistance element and the terminal voltage of the capacitance element are compared, it is possible to generate signals with exactly 90 ° different phases.
【0012】本発明の場合には、抵抗素子、容量素子の
素子値が設計値と異なっても、抵抗素子、容量素子の両
端に生ずる電圧の振幅値が設計値と異なるのみであり、
それぞれの素子の両端の電圧の位相には何等影響を与え
ない。In the case of the present invention, even if the element values of the resistance element and the capacitance element are different from the design values, the amplitude value of the voltage generated across the resistance element and the capacitance element is different from the design value.
It has no effect on the phase of the voltage across each element.
【0013】さらに抵抗素子、容量素子の両端に高入力
インピーダンスの振幅制限回路を設けることにより、移
相回路の次段に接続される回路の如何に関わらず、一定
の電流を抵抗素子、容量素子に与えることができるの
で、より低消費電力化を図ることができる。Further, by providing an amplitude limiting circuit having a high input impedance at both ends of the resistance element and the capacitance element, a constant current is supplied to the resistance element and the capacitance element regardless of the circuit connected to the next stage of the phase shift circuit. Therefore, it is possible to further reduce power consumption.
【0014】[0014]
【実施例】まず、本発明の移相回路の概略を説明する。
本発明においては、直列に接続した抵抗素子、容量素子
を各1個を用いる。すなわち、正弦波の入力信号を増幅
する増幅回路と、増幅器の出力端子に接続された抵抗素
子と、抵抗素子に直列に接続された容量素子と、抵抗素
子の両端の電圧を入力とし、一定の振幅に増幅して出力
する振幅制限回路と、容量素子の両端の電圧を入力と
し、一定の振幅に増幅して出力する振幅制限回路より成
る。First, the outline of the phase shift circuit of the present invention will be described.
In the present invention, one resistance element and one capacitance element connected in series are used. That is, an amplification circuit that amplifies a sine wave input signal, a resistance element connected to the output terminal of the amplifier, a capacitive element connected in series with the resistance element, and a voltage across the resistance element are input, It is composed of an amplitude limiting circuit that amplifies and outputs the amplitude, and an amplitude limiting circuit that inputs the voltage across the capacitive element and amplifies and outputs it to a constant amplitude.
【0015】例えば、正弦波信号源より入力された信号
は、直列に接続された抵抗値がRの抵抗素子と容量値が
Cの容量素子3に供給されるものとする。抵抗値Rの抵
抗素子の両端には第一の振幅制限回路が接続され、容量
値Cの容量素子の両端には第二の振幅制限回路が接続さ
れる。すなわち十分大きな入力インピーダンスの第一、
第二の振幅制限回路は、それぞれ抵抗素子の端子間電
圧、容量素子の端子間電圧を入力とし、抵抗素子の端子
間電圧、容量素子の端子間電圧をそれぞれ一定の振幅に
まで増幅し、出力する。このとき、抵抗素子を流れる電
流をIR、抵抗素子の端子間電圧をVRとすると、I
R、VRの関係は式1で表される。For example, a signal input from a sine wave signal source is supplied to a resistance element having a resistance value R and a capacitance element 3 having a capacitance value C, which are connected in series. The first amplitude limiting circuit is connected to both ends of the resistance element having the resistance value R, and the second amplitude limiting circuit is connected to both ends of the capacitance element having the capacitance value C. That is, the first of sufficiently large input impedance,
The second amplitude limiting circuit inputs the voltage between terminals of the resistance element and the voltage between terminals of the capacitance element, respectively, amplifies the voltage between terminals of the resistance element and the voltage between terminals of the capacitance element to a certain amplitude, and outputs it. To do. At this time, if the current flowing through the resistance element is IR and the terminal voltage of the resistance element is VR, I
The relationship between R and VR is expressed by Equation 1.
【0016】[0016]
【数1】 [Equation 1]
【0017】また直列接続された抵抗素子と容量素子と
の接続点から流れ出る信号電流をΔi、容量素子の端子
間電圧をVCとすると、ΔiとVCとの関係は式2のよ
うになる。When the signal current flowing from the connection point between the resistance element and the capacitance element connected in series is Δi and the voltage between the terminals of the capacitance element is VC, the relation between Δi and VC is expressed by the equation (2).
【0018】[0018]
【数2】 また抵抗素子の端子間電圧VRと容量素子の端子間電圧
VCの移相差をφとすると、φは式3で表わせる。[Equation 2] Further, when the phase shift difference between the voltage VR between terminals of the resistance element and the voltage VC between terminals of the capacitance element is φ, φ can be expressed by Equation 3.
【0019】[0019]
【数3】 ここでΔiが抵抗素子を流れる電流IRより十分小さい
場合は、VRとVCの位相差の90°からのずれをΔφ
とすると、Δφは式4の様に近似できる。[Equation 3] Here, when Δi is sufficiently smaller than the current IR flowing through the resistance element, the deviation of the phase difference between VR and VC from 90 ° is Δφ.
Then, Δφ can be approximated by Equation 4.
【0020】[0020]
【数4】 [Equation 4]
【0021】すなわち、寄生容量等も含めた振幅制限回
路の入力インピーダンスが分かれば、端子間電圧におけ
る位相誤差を目標値以内にするために必要な容量素子と
抵抗素子の素子値を決定できる。That is, if the input impedance of the amplitude limiting circuit including the parasitic capacitance and the like is known, the element values of the capacitive element and the resistive element necessary for keeping the phase error in the terminal voltage within the target value can be determined.
【0022】本発明においては、抵抗素子、容量素子と
もただ一つのみであるので相対精度の影響を受けない。
抵抗値、容量値は、所望の周波数で、振幅が揃うように
設定されるが、その誤差は端子間電圧の差にのみ影響し
位相誤差には影響しない。さらに端子間電圧の振幅差は
それぞれ接続された振幅制限回路により吸収されるの
で、素子値の誤差は出力に無関係となる。In the present invention, since there is only one resistance element and one capacitance element, there is no influence of relative accuracy.
The resistance value and the capacitance value are set so that the amplitudes are uniform at a desired frequency, but the error affects only the difference between the terminal voltages and does not affect the phase error. Further, since the amplitude difference of the voltage between the terminals is absorbed by the connected amplitude limiting circuits, the error of the element value becomes irrelevant to the output.
【0023】このような抵抗、容量の直列回路では、差
動信号として出力を取り出す必要があるが、集積回路で
は、アンプは通常差動増幅回路が用いられ、かつ変復調
器に用いられるアナログ乗算回路も通常は差動入力が要
求されるのでかえって好都合である。また、後述するよ
うに高入力インピーダンスの振幅制限回路を利用すれ
ば、抵抗素子と容量素子との接続点から流出する電流を
微少とすることが可能となり、位相誤差は飛躍的に小さ
くすることができる。ブリッジ型の位相回路に比べる
と、素子の相対精度の問題がなく、かつ抵抗素子、容量
素子とも各1個ずつなので、信号電力の利用効率が高
く、それだけ低消費電力化が図れる。In such a series circuit of resistors and capacitors, it is necessary to take out an output as a differential signal, but in an integrated circuit, an amplifier is usually a differential amplifier circuit and an analog multiplication circuit used in a modulator / demodulator. Also, since differential input is usually required, it is rather convenient. Further, as described later, if an amplitude limiting circuit with high input impedance is used, it is possible to make the current flowing out from the connection point between the resistance element and the capacitance element extremely small, and the phase error can be dramatically reduced. it can. Compared to the bridge type phase circuit, there is no problem of relative accuracy of the elements, and since each of the resistance element and the capacitance element has one, the utilization efficiency of the signal power is high and the power consumption can be reduced accordingly.
【0024】この回路を集積回路として実現する場合、
容量素子は半導体基板と平行な2つの電極を対向させる
ことによって実現されることが多い。特にシリコン半導
体の場合、基板を直流電源の正または負の電位に保つの
で、容量素子の両電極の対地寄生容量に大きな違いがあ
る。式4に示すように、図1の回路はΔiが小さいほど
位相誤差が小さくなる。Δiには抵抗素子と容量素子の
接続点における寄生容量に流れる電流も含まれる。した
がって、容量素子の2つの電極のうち、対地寄生容量が
小さい電極を抵抗に接続したほうが位相誤差が小さい位
相回路ができる。以下本発明の移相回路の構成例を図面
を用いて説明する。When this circuit is realized as an integrated circuit,
A capacitive element is often realized by facing two electrodes parallel to a semiconductor substrate. Particularly in the case of a silicon semiconductor, since the substrate is maintained at the positive or negative potential of the DC power supply, there is a large difference in the parasitic capacitance between the two electrodes of the capacitive element. As shown in Expression 4, in the circuit of FIG. 1, the smaller Δi is, the smaller the phase error is. Δi also includes the current flowing in the parasitic capacitance at the connection point between the resistance element and the capacitance element. Therefore, of the two electrodes of the capacitive element, a phase circuit having a smaller phase error can be obtained by connecting the electrode having the smaller parasitic capacitance to ground to the resistor. Hereinafter, a configuration example of the phase shift circuit of the present invention will be described with reference to the drawings.
【0025】図1は本発明の移相回路の第一の実施例で
ある。この様に容量素子の電極の一方を接地すると、容
量素子と抵抗素子の接続点における対地寄生容量7に流
れる電流の位相が抵抗素子に流れる電流IRの位相と等
しくなる。式4より、IRと位相が等しいΔiの成分は
位相誤差に影響しないので、対地寄生容量7の位相誤差
への影響を回避できる。この場合に容量素子の両端子の
うち、対地寄生容量の小さい端子に抵抗素子を接続する
ことにより、さらに高精度の移相回路を構成することが
できる。FIG. 1 shows a first embodiment of the phase shift circuit of the present invention. When one of the electrodes of the capacitive element is grounded in this way, the phase of the current flowing through the parasitic capacitance 7 to the ground at the connection point between the capacitive element and the resistive element becomes equal to the phase of the current IR flowing through the resistive element. From Equation 4, since the component of Δi having the same phase as IR does not affect the phase error, it is possible to avoid the influence of the ground parasitic capacitance 7 on the phase error. In this case, by connecting the resistance element to one of the terminals of the capacitive element having a smaller parasitic capacitance to ground, a more accurate phase shift circuit can be configured.
【0026】図2は本発明の移相回路の第二の実施例で
ある。特に高周波の集積回路の場合、入出力のアイソレ
ーションを取ることが難しくなるので、小さな入力信号
で、大きな信号出力を求められることが多い。抵抗素子
と容量素子の端子間電圧が小さい場合、振幅制限回路に
多段アンプを用いるなど、利得を大きくすることで信号
の振幅に対する要求は満たす事が考えられるが、振幅制
限回路における位相のずれが問題となる。FIG. 2 shows a second embodiment of the phase shift circuit of the present invention. Particularly in the case of a high-frequency integrated circuit, it is difficult to obtain input / output isolation, so that a large input signal is often required with a small input signal. If the voltage between the terminals of the resistance element and the capacitance element is small, it may be possible to satisfy the signal amplitude requirement by increasing the gain by using a multi-stage amplifier in the amplitude limiting circuit, but there is a phase shift in the amplitude limiting circuit. It becomes a problem.
【0027】この問題は、図2のように抵抗素子と容量
素子の直列回路に入力する信号を大きくするために入力
信号増幅回路8を用い、振幅制限回路は位相のずれが少
ない簡略な構成のものを採用することにより回避でき
る。The problem is that the input signal amplifying circuit 8 is used to increase the signal input to the series circuit of the resistance element and the capacitance element as shown in FIG. 2, and the amplitude limiting circuit has a simple structure with little phase shift. It can be avoided by adopting one.
【0028】図3は本発明の移相回路の第三の実施例で
ある。振幅制限回路の入力インピーダンスが十分大きく
ない場合、抵抗素子と容量素子の直列回路のインピーダ
ンスを小さくして、位相誤差を抑える方法もあるが、エ
ミッタホロア回路などの高入力インピーダンスの緩衝増
幅回路9、10、11を用いることでも対応できる。FIG. 3 shows a third embodiment of the phase shift circuit of the present invention. When the input impedance of the amplitude limiting circuit is not sufficiently large, there is a method of reducing the impedance of the series circuit of the resistance element and the capacitance element to suppress the phase error. However, the buffer amplifier circuits 9 and 10 having a high input impedance such as the emitter follower circuit are available. , 11 can also be used.
【0029】図4は本発明の移相回路の第五の実施例で
ある。エミッタホロア回路などの緩衝増幅回路に配線寄
生容量などの容量性負荷が付いた場合、特に高周波で出
力の位相が入力信号の位相より遅れてしまうことがあ
る。図4に示すように、緩衝増幅回路12、13、1
4、15の出力端子の配線寄生容量も含めた負荷を揃え
ることによって、各緩衝増幅回路に置ける位相遅れを揃
えることができ、位相誤差の削減を図る事ができる。以
上、本発明によれば、移相回路の消費電流を小さくする
ことができ、また回路設計段階での位相誤差の見積もり
が容易になる。FIG. 4 shows a fifth embodiment of the phase shift circuit of the present invention. When a buffer amplifier circuit such as an emitter follower circuit is provided with a capacitive load such as a wiring parasitic capacitance, the output phase may be delayed from the input signal phase particularly at high frequencies. As shown in FIG. 4, buffer amplifier circuits 12, 13, 1
By aligning the loads including the wiring parasitic capacitances of the output terminals 4 and 15, the phase delays in the buffer amplifier circuits can be aligned, and the phase error can be reduced. As described above, according to the present invention, the current consumption of the phase shift circuit can be reduced, and the phase error can be easily estimated at the circuit design stage.
【0030】[0030]
【発明の効果】前述の通り、本発明によれば抵抗素子、
容量素子の誤差の影響が小さい移相器を構成できる。ま
た、抵抗素子、容量素子が各1個のみなので、最低でも
2個ずつ必要なブリッジ型移相回路に比べて電力の利用
効率が良く、移相回路の消費電流を小さくできる。さら
に回路設計段階での移相誤差の見積もりが容易になると
いう利点もある。As described above, according to the present invention, the resistance element,
A phase shifter that is less affected by the error of the capacitive element can be configured. Further, since there is only one resistive element and one capacitive element, the power use efficiency is better and the current consumption of the phase shift circuit can be reduced compared to a bridge type phase shift circuit that requires at least two. There is also an advantage that the phase shift error can be easily estimated at the circuit design stage.
【図1】本発明に係わる移相回路の第一の実施例。FIG. 1 shows a first embodiment of a phase shift circuit according to the present invention.
【図2】本発明に係わる移相回路の第二の実施例。FIG. 2 is a second embodiment of the phase shift circuit according to the present invention.
【図3】本発明に係わる移相回路の第三の実施例。FIG. 3 shows a third embodiment of the phase shift circuit according to the present invention.
【図4】本発明に係わる移相回路の第四の実施例。FIG. 4 is a fourth embodiment of the phase shift circuit according to the present invention.
【図5】従来の移相回路。FIG. 5 is a conventional phase shift circuit.
1 信号源 2 抵抗素子 3 容量素子 4、5 振幅制限回路 1 signal source 2 resistance element 3 capacitance element 4, 5 amplitude limiting circuit
Claims (4)
れる容量素子と、前記抵抗素子の両端に接続される第1
の振幅制限回路と、前記容量素子の両端に接続される第
2の振幅制限回路とで構成されることを特徴とする移相
回路。1. A resistive element, a capacitive element connected in series to the resistive element, and a first element connected to both ends of the resistive element.
And a second amplitude limiting circuit connected to both ends of the capacitive element.
の動作に必要な振幅にまで増幅する入力信号増幅回路を
備えたことを特徴とする請求項1の移相回路。2. The phase shift circuit according to claim 1, further comprising an input signal amplifier circuit for amplifying an input signal to an amplitude required for the operation of the first and second amplitude limiting circuits.
れた容量素子と、前記抵抗素子と前記容量素子との接続
点に接続される第1の緩衝増幅回路と、前記接続点と反
対の前記抵抗素子の端子に接続される第2の緩衝増幅回
路と、前記接続点と反対の前記容量素子の端子に接続さ
れる第3の緩衝増幅回路と、第1の緩衝増幅回路の出力
電圧と第2の緩衝増幅回路の出力電圧の差を入力電圧と
する第1の振幅制限回路と、第1の緩衝増幅回路の出力
電圧と第3の緩衝増幅回路の出力電圧の差を入力電圧と
する第2の振幅制限回路とで構成され、前記第1、第
2、第3の緩衝増幅回路の入力インピーダンスの絶対値
が前記第1、第2の振幅制限回路の入力インピーダンス
の絶対値よりも大きいことを特徴とする移相回路。3. A resistance element, a capacitance element connected in series to the resistance element, a first buffer amplifier circuit connected to a connection point between the resistance element and the capacitance element, and a connection point opposite to the connection point. A second buffer amplifier circuit connected to the terminal of the resistance element, a third buffer amplifier circuit connected to the terminal of the capacitance element opposite to the connection point, and an output voltage of the first buffer amplifier circuit And a first amplitude limiting circuit that uses the difference between the output voltages of the second buffer amplifier circuit as an input voltage, and the difference between the output voltage of the first buffer amplifier circuit and the output voltage of the third buffer amplifier circuit as the input voltage. And a second amplitude limiting circuit, the absolute value of the input impedance of the first, second, and third buffer amplifier circuits is greater than the absolute value of the input impedance of the first and second amplitude limiting circuits. Phase shift circuit characterized by being large.
することを特徴とする請求項1、2または3記載の移相
回路。4. The phase shift circuit according to claim 1, wherein one terminal of the capacitance element is grounded in an alternating current.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34183392A JPH06188679A (en) | 1992-12-22 | 1992-12-22 | Phase shift circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34183392A JPH06188679A (en) | 1992-12-22 | 1992-12-22 | Phase shift circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06188679A true JPH06188679A (en) | 1994-07-08 |
Family
ID=18349108
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP34183392A Pending JPH06188679A (en) | 1992-12-22 | 1992-12-22 | Phase shift circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06188679A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11222910B2 (en) | 2017-11-07 | 2022-01-11 | Takeharu Etoh | High-speed image sensor |
-
1992
- 1992-12-22 JP JP34183392A patent/JPH06188679A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11222910B2 (en) | 2017-11-07 | 2022-01-11 | Takeharu Etoh | High-speed image sensor |
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