JPH05259615A - Formation of circuit conductor - Google Patents
Formation of circuit conductorInfo
- Publication number
- JPH05259615A JPH05259615A JP8990892A JP8990892A JPH05259615A JP H05259615 A JPH05259615 A JP H05259615A JP 8990892 A JP8990892 A JP 8990892A JP 8990892 A JP8990892 A JP 8990892A JP H05259615 A JPH05259615 A JP H05259615A
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- conductor
- circuit
- forming
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、多層導体を用いた回路
導体の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a circuit conductor using a multilayer conductor.
【０００２】[0002]
【従来の技術】従来、セラミック等の絶縁材料で形成さ
れた回路基板に銀ペースト等の導体を印刷することによ
り導体パターンを形成し、その上に銅めっきを施し、導
体パターンの導体抵抗を低減させた厚膜集積回路が実用
化されている。2. Description of the Related Art Conventionally, a conductor pattern is formed by printing a conductor such as silver paste on a circuit board formed of an insulating material such as ceramic, and copper plating is applied on the conductor pattern to reduce the conductor resistance of the conductor pattern. The thick film integrated circuit is put into practical use.
【０００３】図３は、従来の回路導体の形成方法を示し
ている。この形成方法では、図３の（Ａ）に示すよう
に、セラミック等の絶縁材料で回路基板２が形成され、
次に、図３の（Ｂ）に示すように、この回路基板２の表
面に導体パターンを成す導体層４１が導体ペーストの印
刷処理で形成され、次に、図３の（Ｃ）に示すように、
導体層４１の上にめっき処理で導体層４２が形成され
る。即ち、この形成方法では、印刷処理及びめっき処理
の２工程によって所望のパターンを成す一つの回路導体
４が形成されている。FIG. 3 shows a conventional method for forming a circuit conductor. In this forming method, as shown in FIG. 3A, the circuit board 2 is formed of an insulating material such as ceramic,
Next, as shown in FIG. 3 (B), a conductor layer 41 forming a conductor pattern is formed on the surface of the circuit board 2 by printing a conductor paste, and then as shown in FIG. 3 (C). To
The conductor layer 42 is formed on the conductor layer 41 by plating. That is, in this forming method, one circuit conductor 4 having a desired pattern is formed by the two steps of printing and plating.
【０００４】[0004]
【発明が解決しようとする課題】ところで、このような
回路導体では、図４に示すように、導体層４１の幅を
Ｄ、導体層４２の厚さをｄとすると、回路導体４が持つ
幅はＤ＋２ｄとなる。厚さｄはめっき厚であるから、導
体層４１の幅Ｄが大きい場合には、問題にならないが、
高精細化のために、導体層４１の幅Ｄを小さくすれば、
回路導体４の幅（Ｄ＋２ｄ）に対する導体層４２の厚さ
２ｄの割合が大きくなる。このため、回路導体４の精度
を高く設定しようとすると、導体層４１の幅Ｄ及び導体
層４２の厚さｄの双方を制御することが必要となり、導
体層４１の幅Ｄは印刷精度に依存するので、高精細化は
困難である上、導体層４２の厚さ２ｄが誤差として作用
し、回路導体４の精度が低下することになる。In such a circuit conductor, as shown in FIG. 4, when the width of the conductor layer 41 is D and the thickness of the conductor layer 42 is d, the width of the circuit conductor 4 is Becomes D + 2d. Since the thickness d is the plating thickness, it does not matter if the width D of the conductor layer 41 is large.
If the width D of the conductor layer 41 is reduced for high definition,
The ratio of the thickness 2d of the conductor layer 42 to the width (D + 2d) of the circuit conductor 4 increases. Therefore, in order to set the accuracy of the circuit conductor 4 to be high, it is necessary to control both the width D of the conductor layer 41 and the thickness d of the conductor layer 42, and the width D of the conductor layer 41 depends on the printing accuracy. Therefore, it is difficult to achieve high definition, and the thickness 2d of the conductor layer 42 acts as an error, which reduces the accuracy of the circuit conductor 4.
【０００５】また、銀印刷等で形成された導体層４１か
らなるアイランドパターンに導体層４２をめっき処理す
ることは、回路パターンの低インピーダンス化が可能に
なるが、アイランドパターンにめっき処理を行うこと
は、導体層４１に部分的にめっき層が形成されない部
分、即ち、導体層４２が析出しない部分が生じる等の不
良発生も無視することができない。Further, although the island pattern made of the conductor layer 41 formed by silver printing or the like is plated with the conductor layer 42, the impedance of the circuit pattern can be lowered, but the island pattern is plated. Cannot be neglected even if a defect such as a portion where the plated layer is not partially formed on the conductor layer 41, that is, a portion where the conductor layer 42 is not deposited occurs.
【０００６】そこで、本発明は、フォトレジスト法を応
用して高密度及び高精細度化を実現した回路導体の形成
方法を提供することを目的とする。Therefore, it is an object of the present invention to provide a method for forming a circuit conductor which realizes high density and high definition by applying a photoresist method.
【０００７】[0007]
【課題を解決するための手段】本発明の回路導体の形成
方法は、絶縁材料で形成された回路基板（２）の表面に
印刷によって第１の導体層（６１）を形成する工程と、
前記第１の導体層の上に所望のパターンを成すめっきレ
ジスト膜（８）を形成する工程と、前記めっきレジスト
膜から露出する前記第１の導体層の上にめっき処理によ
って第２の導体層（６２）を形成する工程と、前記めっ
きレジスト膜を除去する工程と、前記第２の導体層をマ
スクにし、前記第２の導体層から露出する前記第１の導
体層を除去する工程とを備えたことを特徴とする。A method of forming a circuit conductor according to the present invention comprises a step of forming a first conductor layer (61) on a surface of a circuit board (2) made of an insulating material by printing.
A step of forming a plating resist film (8) forming a desired pattern on the first conductor layer, and a second conductor layer by plating on the first conductor layer exposed from the plating resist film. A step of forming (62), a step of removing the plating resist film, and a step of removing the first conductor layer exposed from the second conductor layer using the second conductor layer as a mask. It is characterized by having.
【０００８】[0008]
【作用】この回路導体の形成方法では、回路基板の表面
に第１の導体層を形成し、その上に所望のパターンを成
すめっきレジスト膜を形成する。その上から、めっき処
理によって第２の導体層を形成する。この導体層は、所
望の回路パターンを構成するものである。In this circuit conductor forming method, the first conductor layer is formed on the surface of the circuit board, and the plating resist film having a desired pattern is formed thereon. Then, a second conductor layer is formed by plating. This conductor layer constitutes a desired circuit pattern.
【０００９】そして、めっきレジスト膜を除くと、その
部分から第１の導体層が露出する。この状態で第２の導
体層をマスクとして利用し、その上からエッチング処理
を施し、第１の導体層を除去する。この結果、第２の導
体層からなる回路パターン以外の部分が除去され、第２
の導体層で支配された第１の導体層が第２の導体層とと
もに残ることになる。When the plating resist film is removed, the first conductor layer is exposed from that part. In this state, the second conductor layer is used as a mask and an etching process is performed on the mask to remove the first conductor layer. As a result, portions other than the circuit pattern formed of the second conductor layer are removed, and the second conductor layer is removed.
The first conductor layer dominated by the second conductor layer remains together with the second conductor layer.
【００１０】このように、本発明の回路導体の形成方法
は、従来の印刷及びめっき処理による膜を加算的に重ね
合わせる方法と異なり、精度の高いマスクを基準にして
膜を減算的に除去する方法である。したがって、回路導
体の高密度化、高精細度化が可能になるとともに、導体
層の密着度が高く、しかも、めっき不良による回路導体
の信頼性低下も回避できるものである。As described above, the circuit conductor forming method of the present invention is different from the conventional method of additively superposing films by printing and plating, and subtractively removes films with a highly accurate mask as a reference. Is the way. Therefore, it is possible to achieve high density and high definition of the circuit conductor, high adhesion of the conductor layer, and avoiding deterioration of reliability of the circuit conductor due to defective plating.
【００１１】[0011]
【実施例】以下、本発明を図面に示した実施例を参照し
て詳細に説明する。The present invention will be described in detail below with reference to the embodiments shown in the drawings.
【００１２】図１及び図２は、本発明の回路導体の形成
方法の一実施例を示している。図１の（Ａ）は、所望の
パターンを成す回路導体を形成すべき回路基板２を示し
ており、この回路基板２は、アルミナ、セラミック等の
絶縁材料で形成する。1 and 2 show an embodiment of the method for forming a circuit conductor of the present invention. FIG. 1A shows a circuit board 2 on which a circuit conductor having a desired pattern is to be formed. The circuit board 2 is made of an insulating material such as alumina or ceramic.
【００１３】この回路基板２の表面を洗浄した後、図１
の（Ｂ）に示すように、その表面に第１の導体層６１を
印刷によって形成する。この導体層６１は銀、白金等の
導体ペーストを以て形成する。この導体層６１は下部導
体を成す。After cleaning the surface of the circuit board 2, as shown in FIG.
(B), the first conductor layer 61 is formed on the surface by printing. The conductor layer 61 is formed by using a conductor paste such as silver or platinum. The conductor layer 61 forms a lower conductor.
【００１４】次に、この導体層６１の表面にフォトレジ
スト法により、図１の（Ｃ）に示すように、所望のパタ
ーンを成すめっきレジスト膜８を形成する。このめっき
レジスト膜８は、スクリーン印刷によって形成され、空
部分１０が実回路部を示している。Next, as shown in FIG. 1C, a plating resist film 8 having a desired pattern is formed on the surface of the conductor layer 61 by the photoresist method. The plating resist film 8 is formed by screen printing, and the empty portion 10 shows the actual circuit portion.
【００１５】次に、図２の（Ｄ）に示すように、めっき
レジスト膜８から露出している導体層６１の表面に無電
解めっき処理によって表面導体である第２の導体層６２
を形成する。この導体層６２は、低インピーダンス化の
ため、導体抵抗の低い金属、例えば銅で形成する。この
導体層６２が最終的な回路パターンの形態を成してい
る。Next, as shown in FIG. 2D, the surface of the conductor layer 61 exposed from the plating resist film 8 is subjected to electroless plating to form a second conductor layer 62 which is a surface conductor.
To form. The conductor layer 62 is formed of a metal having a low conductor resistance, for example, copper in order to reduce the impedance. The conductor layer 62 forms the final circuit pattern.
【００１６】このめっき処理の後、洗浄を施した回路基
板２を有機溶剤に浸漬することにより、図２の（Ｅ）に
示すように、回路基板２からめっきレジスト膜８を除去
する。After this plating process, the washed circuit board 2 is immersed in an organic solvent to remove the plating resist film 8 from the circuit board 2 as shown in FIG. 2 (E).
【００１７】次に、導体層６２をマスクとして導体層６
１を回路基板２から除去する。即ち、回路基板２をエッ
チング液に浸漬し、導体６２に覆われていない部分の導
体層６１を除去し、導体層６２のパターンで支配される
導体パターンを成す導体層６１を回路基板２上にエッチ
グ処理で形成する。この結果、導体層６１、６２からな
る回路導体６が形成された回路基板２が得られる。Next, the conductor layer 6 is used as a mask to form the conductor layer 6
1 is removed from the circuit board 2. That is, the circuit board 2 is immersed in an etching solution to remove the portion of the conductor layer 61 not covered by the conductor 62, and the conductor layer 61 having a conductor pattern governed by the pattern of the conductor layer 62 is formed on the circuit board 2. Formed by etching process. As a result, the circuit board 2 on which the circuit conductor 6 including the conductor layers 61 and 62 is formed is obtained.
【００１８】以上説明したように、このような回路導体
の形成方法では、膜加算によるパターン形成がなく、し
かも、めっきレジスト膜８はフォトレジスト法によるた
め、高密度及び高精細化されたパターンを形成し、それ
に基づいてエッチング処理を行い、また、導体層６２を
マスクとして導体層６１をエッチング処理で除くため、
極めて高い精度の幅を持つ回路導体６が形成される。As described above, in such a circuit conductor forming method, there is no pattern formation by film addition, and since the plating resist film 8 is formed by the photoresist method, a high density and high definition pattern is formed. In order to remove the conductor layer 61 by etching using the conductor layer 62 as a mask,
The circuit conductor 6 having an extremely high precision width is formed.
【００１９】また、導体層６１は回路基板２上に全面印
刷によって形成できるので、両者の密着強度が高まり、
高密着度の回路導体６を形成することができる。Further, since the conductor layer 61 can be formed on the circuit board 2 by printing the whole surface, the adhesion strength between the two is increased,
The circuit conductor 6 having a high degree of adhesion can be formed.
【００２０】また、従来のように、絶縁材料で形成され
た回路基板２上にめっきを施した場合に比較し、導体層
６１を成す導体ペーストに含まれるガラス成分を接着層
として利用して導体層６１に対するめっき層である導体
層６２の密着強度を高めることができる。そして、導体
層６２のめっき処理は、従来のアイランド化された導体
層上に行うのと異なり、共通の電位を持つ導体層６１上
に導体層６２をめっき処理するため、めっきの析出が良
好になり、めっき不良の発生を防止することができる。
また、最終工程として無電解めっきによってサイドにご
くうすい膜を形成することが可能であり、耐はんだ特
性、耐マイグレーション性を向上させることができる。Further, as compared with the conventional case where the circuit board 2 formed of an insulating material is plated, the glass component contained in the conductor paste forming the conductor layer 61 is used as an adhesive layer to form a conductor. The adhesion strength of the conductor layer 62, which is the plating layer, to the layer 61 can be increased. The conductor layer 62 is plated on the conductor layer 61 having a common potential, unlike the conventional island-shaped conductor layer. Therefore, it is possible to prevent the occurrence of defective plating.
Further, as a final step, it is possible to form a very thin film on the side by electroless plating, and it is possible to improve solder resistance and migration resistance.
【００２１】なお、実施例では、無電解めっき処理を例
にとって説明したが、本発明では、導体層６１の電位を
共通化できるので、無電解めっき処理以外のめっき処理
を用いても同様の効果が期待できる。In the embodiment, the electroless plating process is taken as an example. However, in the present invention, since the potential of the conductor layer 61 can be made common, the same effect can be obtained by using a plating process other than the electroless plating process. Can be expected.
【００２２】[0022]
【発明の効果】以上説明したように、本発明によれば、
回路導体の高密度化、高精細度化を図ることができると
ともに、導体層と回路基板、導体層間の密着度を高める
ことができ、めっき不良の回避によって回路導体の信頼
性を高めることができ、厚膜集積回路の信頼性向上及び
高密度化に寄与することができる。As described above, according to the present invention,
It is possible to achieve high density and high definition of the circuit conductor, increase the degree of adhesion between the conductor layer, the circuit board, and the conductor layer, and improve reliability of the circuit conductor by avoiding defective plating. It is possible to contribute to the improvement of reliability and the increase in density of the thick film integrated circuit.
【図１】本発明の回路導体の形成方法の一実施例を示す
断面図である。FIG. 1 is a cross-sectional view showing an example of a method for forming a circuit conductor of the present invention.
【図２】本発明の回路導体の形成方法の一実施例を示す
断面図である。FIG. 2 is a cross-sectional view showing an example of a method for forming a circuit conductor of the present invention.
【図３】従来の回路導体の形成方法を示す断面図であ
る。FIG. 3 is a cross-sectional view showing a conventional method for forming a circuit conductor.
【図４】従来の回路導体の形成方法で形成された回路導
体を示す断面図である。FIG. 4 is a cross-sectional view showing a circuit conductor formed by a conventional method for forming a circuit conductor.
２ 回路基板 ８ めっきレジスト膜 ６１ 第１の導体層 ６２ 第２の導体層 2 circuit board 8 plating resist film 61 first conductor layer 62 second conductor layer
Claims (1)
印刷によって第１の導体層を形成する工程と、 前記第１の導体層の上に所望のパターンを成すめっきレ
ジスト膜を形成する工程と、 前記めっきレジスト膜から露出する前記第１の導体層の
上にめっき処理によって第２の導体層を形成する工程
と、 前記めっきレジスト膜を除去する工程と、 前記第２の導体層をマスクにし、前記第２の導体層から
露出する前記第１の導体層を除去する工程と、 を備えたことを特徴とする回路導体の形成方法。1. A step of forming a first conductor layer on a surface of a circuit board made of an insulating material by printing, and a step of forming a plating resist film having a desired pattern on the first conductor layer. A step of forming a second conductor layer on the first conductor layer exposed from the plating resist film by a plating process, a step of removing the plating resist film, and a mask of the second conductor layer. And a step of removing the first conductor layer exposed from the second conductor layer, the method for forming a circuit conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8990892A JPH05259615A (en) | 1992-03-13 | 1992-03-13 | Formation of circuit conductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8990892A JPH05259615A (en) | 1992-03-13 | 1992-03-13 | Formation of circuit conductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05259615A true JPH05259615A (en) | 1993-10-08 |
Family
ID=13983823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8990892A Pending JPH05259615A (en) | 1992-03-13 | 1992-03-13 | Formation of circuit conductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05259615A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013021366A (en) * | 2009-04-24 | 2013-01-31 | Sumitomo Electric Ind Ltd | Substrate for printed wiring board, printed wiring board, and method for manufacturing substrate for printed wiring board |
| JP2015222841A (en) * | 2015-09-15 | 2015-12-10 | 株式会社トクヤマ | Metallized ceramic via substrate and manufacturing method thereof |
| US10076028B2 (en) | 2015-01-22 | 2018-09-11 | Sumitomo Electric Industries, Ltd. | Substrate for printed circuit board, printed circuit board, and method for producing printed circuit board |
| US10076032B2 (en) | 2014-03-20 | 2018-09-11 | Sumitomo Electric Industries, Ltd. | Substrate for printed circuit board, printed circuit board, and method for producing substrate for printed circuit board |
| US10237976B2 (en) | 2014-03-27 | 2019-03-19 | Sumitomo Electric Industries, Ltd. | Substrate for printed circuit board, printed circuit board, and method for producing substrate for printed circuit board |
-
1992
- 1992-03-13 JP JP8990892A patent/JPH05259615A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013021366A (en) * | 2009-04-24 | 2013-01-31 | Sumitomo Electric Ind Ltd | Substrate for printed wiring board, printed wiring board, and method for manufacturing substrate for printed wiring board |
| US10076032B2 (en) | 2014-03-20 | 2018-09-11 | Sumitomo Electric Industries, Ltd. | Substrate for printed circuit board, printed circuit board, and method for producing substrate for printed circuit board |
| US10237976B2 (en) | 2014-03-27 | 2019-03-19 | Sumitomo Electric Industries, Ltd. | Substrate for printed circuit board, printed circuit board, and method for producing substrate for printed circuit board |
| US10076028B2 (en) | 2015-01-22 | 2018-09-11 | Sumitomo Electric Industries, Ltd. | Substrate for printed circuit board, printed circuit board, and method for producing printed circuit board |
| JP2015222841A (en) * | 2015-09-15 | 2015-12-10 | 株式会社トクヤマ | Metallized ceramic via substrate and manufacturing method thereof |
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