JPS5819158B2 - Manufacturing method for high-density multilayer wiring board - Google Patents
Manufacturing method for high-density multilayer wiring boardInfo
- Publication number
- JPS5819158B2 JPS5819158B2 JP51116362A JP11636276A JPS5819158B2 JP S5819158 B2 JPS5819158 B2 JP S5819158B2 JP 51116362 A JP51116362 A JP 51116362A JP 11636276 A JP11636276 A JP 11636276A JP S5819158 B2 JPS5819158 B2 JP S5819158B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring board
- multilayer wiring
- manufacturing
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
本発明は、多層配線基板の製造方法に関し、特に、コン
ピュータ等に用いる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer wiring board, particularly for use in computers and the like.
ＬＳＩ実装用の高密度多層配線基板の製造方法に関する
。The present invention relates to a method of manufacturing a high-density multilayer wiring board for LSI mounting.
従来、どの種の多層配線基板は、導体層およ゛び絶縁′
層とともにスクリーン印刷法＋印刷し、焼成するどとに
よって形成されて□いる。Traditionally, any type of multilayer wiring board has a conductor layer and an insulation layer.
The layers are formed by screen printing + printing and firing.
しかシ、：ズクリーン印刷法では、糟旋および品質上に
限度がある。However, the screen printing method has limitations in terms of processing and quality.
精度上では、スクリーンメツシュを通してパターンを印
刷するため、導体層の配線線中が１０゛０μｍ以下番ど
なると、印刷力梱難になる２゜゛また、スクリーン製版
精度に依存するため、１′０〜２０μｍ桓度の誤差が生
じる。In terms of accuracy, since the pattern is printed through a screen mesh, if the wiring line in the conductor layer has an unevenness of less than 10゛0μm, printing power becomes difficult. An error of ~20 μm in accuracy occurs.
゛さらに材料として。厚膜ペースト材料を用いるため、
形成され光導体虐゛は、多孔質で密度の疎′な膜となり
、パターシ亦微細になると１品質篩にも問題が生じる。゛And as a material. Because thick film paste material is used,
The formed photoconductor layer becomes a porous, low-density film, and when the pattern becomes fine, problems arise even with a single-quality sieve.
一本発明の目的は、上述の欠点を除去した高密度
多層配線基板の製木方法を提供することにある。One object of the present invention is to provide a method for manufacturing a high-density multilayer wiring board that eliminates the above-mentioned drawbacks.
この発明の製″造方法でぼ、絶縁性基板上゛に、スパッ
タリングで銅を条面に形成して銅層を荊成゛シ。In the manufacturing method of the present invention, a copper layer is formed on an insulating substrate by sputtering copper into strips.
次に、フォトレジストを用いて、露光、現像お“ｊびエ
ツチングを行ない必要なパターンを得る。Next, using a photoresist, exposure, development and etching are performed to obtain the required pattern.
このよう゛にしてン導体パターンを形成すると、１６６
１μｍ以下の配線線巾が容易に得られる。When a conductor pattern is formed in this way, 166
A wiring line width of 1 μm or less can be easily obtained.
また、精度も、ガラスマスク精度に依存するようになり
、５μｍ以下となる。Furthermore, the accuracy also depends on the glass mask accuracy and is 5 μm or less.
さらに、スパッタリングによって、銅層を形成すること
により均一で緻密な膜が得ら件、品質も向上する。Furthermore, by forming a copper layer by sputtering, a uniform and dense film can be obtained, which improves quality.
このあと、導体パターンが形成された絶縁性基板上に、
スクリーン印刷で絶縁ペースト材料を印刷する。After this, on the insulating substrate on which the conductor pattern was formed,
Print the insulation paste material by screen printing.
次に、１１００ｐｐ以下のごくわずかの酸素を含むチッ
素雰囲気で前記基板全体を９００℃程度の温度で焼成す
ることにより絶縁層を形成するとともに、導体層の基・
板に対する当着を強化する。Next, the entire substrate is fired at a temperature of about 900° C. in a nitrogen atmosphere containing a very small amount of oxygen of 1100 pp or less to form an insulating layer and a base layer for the conductive layer.
Strengthens contact with the board.
従来スパッタリングで導体層を形成する場合、導体層と
基板や絶縁層との間の密着性に問題があり、密着強度を
増すためにンさまざまな工夫が必要であった。Conventionally, when forming a conductor layer by sputtering, there was a problem with the adhesion between the conductor layer and the substrate or insulating layer, and various measures were required to increase the adhesion strength.
本発明では、スパッタした銅をごくわずかな酸素を含む
チッ素雰囲気で９００℃程度で焼成するだけで強固な密
着を得ている。In the present invention, strong adhesion is obtained simply by firing sputtered copper at about 900° C. in a nitrogen atmosphere containing a very small amount of oxygen.
しかも、このプロセスは、絶縁層形成に、必要なプロセ
スであり、密着強化のための新たなプロセスが力ｑわっ
ているわけではない。Moreover, this process is a necessary process for forming an insulating layer, and there is no need for a new process to strengthen adhesion.
このように、密着強度が増すのは上記焼成により、チッ
素雰囲気中にごくわずかに含まれる酸素と銅とが反応し
て、銅の酸化物が、銅と基板もしくは絶縁層との間に形
成され、これが密着の役目をするためである。In this way, the adhesion strength increases because the firing process causes the very small amount of oxygen contained in the nitrogen atmosphere to react with the copper, and copper oxide is formed between the copper and the substrate or insulating layer. This is because it serves as a close contact.
このようにして、銅のスパッタリング、露光、現像およ
びエツチングで導体層を形成する工程と。In this way, a conductor layer is formed by copper sputtering, exposure, development, and etching.
絶縁ペースト材料のスクリーン印刷、焼成で絶縁層を形
成する工程とを、交互に少なくとも１回繰返すことによ
って多層配線基板を得ることができる。A multilayer wiring board can be obtained by alternately repeating the steps of screen printing an insulating paste material and forming an insulating layer by baking at least once.
次に１図面を参照して本発明の詳細な説明する。The present invention will now be described in detail with reference to one drawing.
第１図から第７図は本発明の高密度多層配線基板の製造
方法の工程断面図を示す。1 to 7 show process cross-sectional views of the method for manufacturing a high-density multilayer wiring board according to the present invention.
まず、第１図のように、絶縁性基板１に、スパッタリン
グで銅層２を全面に形成する。First, as shown in FIG. 1, a copper layer 2 is formed over the entire surface of an insulating substrate 1 by sputtering.
必要な銅の膜厚は８μｍ程度であり、スパッタリングの
速度は、１．４μｍ／分の値であり、これにより銅層２
は６分間以下で形成される。The required copper film thickness is about 8 μm, and the sputtering speed is 1.4 μm/min.
is formed in less than 6 minutes.
次に、第２図に示−すように、フォトレジスト３をコー
ティングし。Next, as shown in FIG. 2, a photoresist 3 is coated.
露光、現像して、必要なパターンを形成する。Expose and develop to form the required pattern.
次に第３図に示すように、銅をエツチングして、必要な
パターンを形成し、続いてフォトレジストを剥離して、
第一導体層の形成を完了する。The copper is then etched to form the desired pattern, followed by stripping the photoresist, as shown in Figure 3.
Complete the formation of the first conductor layer.
次に、：第４図に示すように、第１絶縁層４を、スクリ
ーン印刷と基板全体の焼成により形成する。Next, as shown in FIG. 4, the first insulating layer 4 is formed by screen printing and baking the entire substrate.
この焼成は、わずかな酸素を含むチッ素雰囲気中で行な
われ、この結果、第一導体層２の基板１に対する一着が
強化される。This firing is performed in a nitrogen atmosphere containing a small amount of oxygen, and as a result, the adhesion of the first conductor layer 2 to the substrate 1 is strengthened.
第５′ＩＩＩは、前記絶縁層４の上層に、さらに１、銅
層５を全面にスパッタリングした状態を示す。5'III shows a state in which a copper layer 5 is further sputtered on the entire surface of the insulating layer 4.
第６図は１図示されていないフォトレジストによって露
光、現像され、予め定められたパターンに銅層５がエツ
チングされた状態を示す。FIG. 6 shows a state in which the copper layer 5 has been exposed and developed using a photoresist (not shown) and etched into a predetermined pattern.
第７図は、以上の工程を繰り返して完成した高密度配線
基板であり、基板１上に第一導体層２゜第二絶縁層３．
第二導体層５．第二絶縁層６．第三導体層７．第三絶縁
層８および第四導体層９が形成されている。FIG. 7 shows a high-density wiring board completed by repeating the above steps, in which a first conductor layer 2, a second insulating layer 3.
Second conductor layer5. Second insulating layer 6. Third conductor layer7. A third insulating layer 8 and a fourth conductor layer 9 are formed.
以上説明したように１本発明を用いると、スパッタリン
グで形成された銅層をエツチングし、微量の酸素を含む
チッ素雰囲気中で焼成して絶縁層を形成すると同時に、
銅導体層の密着を強化することによって、高密度多層配
線基板の精度および品質の大巾な向上が可能となる。As explained above, when the present invention is used, a copper layer formed by sputtering is etched and fired in a nitrogen atmosphere containing a trace amount of oxygen to form an insulating layer.
By strengthening the adhesion of the copper conductor layer, it is possible to greatly improve the accuracy and quality of high-density multilayer wiring boards.
第１図から第７図まではそれぞれ本発明の一実施例を示
す工程断面図である。
第１図から第１図において、参照数字１は、耐熱絶縁性
基板、参照数字２は、銅層（第一導体層）、参照数字３
はフォトレジスト、参照数字４ζ、ま絶縁層（第一絶縁
層）。
参照数字５は第二導体層、参照数字６は、第二絶縁層、
参照数字７は、第三導体層、参照数字８は。
第三絶縁層、および参照数字９は第四導体層をそれぞれ
示す。FIG. 1 to FIG. 7 are process cross-sectional views showing one embodiment of the present invention. 1 to 1, reference numeral 1 is a heat-resistant insulating substrate, reference numeral 2 is a copper layer (first conductor layer), reference numeral 3 is
is photoresist, reference numeral 4ζ, is insulating layer (first insulating layer). Reference numeral 5 is the second conductor layer, reference numeral 6 is the second insulating layer,
Reference numeral 7 is the third conductor layer, reference numeral 8 is the third conductor layer. The third insulating layer and the reference numeral 9 indicate the fourth conductive layer, respectively.
Claims (1)
された絶縁層表面上に、スパッタリングで銅層を全面に
形成する工程と、前記銅層を所定のパターンにエツチン
グにより形成する工程と、前記銅層が形成された前記基
板表面上または前記絶縁層表面上にスクリーン印刷で絶
縁材料を印刷し１００ｐｐｍ（ｐａｒｔｓ ｐｅｒ ｍ
１ｌｌｉｏｎ、）昼下の酸素を含むチッ素雰囲気で焼成
して絶Ｑを形成する工程とを少なくとも１回以上繰返し
そ多層化したことを特徴とする高密度多層配線基板の製
造方丸、1. A step of forming a copper layer all over the surface of a heat-resistant insulating substrate or an insulating layer formed on the heat-resistant substrate by sputtering, and a step of forming the copper layer in a predetermined pattern by etching. An insulating material is printed by screen printing on the surface of the substrate on which the copper layer is formed or on the surface of the insulating layer at a concentration of 100 ppm (parts per m).
1llion,) A method for manufacturing a high-density multilayer wiring board characterized by repeating the step of firing in a nitrogen atmosphere containing oxygen in the daytime to form an absolute Q at least once or more to form a multilayer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51116362A JPS5819158B2 (en) | 1976-09-28 | 1976-09-28 | Manufacturing method for high-density multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51116362A JPS5819158B2 (en) | 1976-09-28 | 1976-09-28 | Manufacturing method for high-density multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5341765A JPS5341765A (en) | 1978-04-15 |
| JPS5819158B2 true JPS5819158B2 (en) | 1983-04-16 |
Family
ID=14685076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51116362A Expired JPS5819158B2 (en) | 1976-09-28 | 1976-09-28 | Manufacturing method for high-density multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5819158B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6131750A (en) * | 1984-07-25 | 1986-02-14 | Fanuc Ltd | Survo motor output transmitting device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0237103B1 (en) * | 1986-03-11 | 1991-11-21 | Koninklijke Philips Electronics N.V. | Composite body |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4832475A (en) * | 1971-08-27 | 1973-04-28 | ||
| JPS4922552A (en) * | 1972-06-26 | 1974-02-28 | ||
| JPS4941854A (en) * | 1972-08-30 | 1974-04-19 | ||
| JPS49112161A (en) * | 1973-02-28 | 1974-10-25 | ||
| JPS50111A (en) * | 1973-05-11 | 1975-01-06 |
-
1976
- 1976-09-28 JP JP51116362A patent/JPS5819158B2/en not_active Expired
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4832475A (en) * | 1971-08-27 | 1973-04-28 | ||
| JPS4922552A (en) * | 1972-06-26 | 1974-02-28 | ||
| JPS4941854A (en) * | 1972-08-30 | 1974-04-19 | ||
| JPS49112161A (en) * | 1973-02-28 | 1974-10-25 | ||
| JPS50111A (en) * | 1973-05-11 | 1975-01-06 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6131750A (en) * | 1984-07-25 | 1986-02-14 | Fanuc Ltd | Survo motor output transmitting device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5341765A (en) | 1978-04-15 |
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