JPS6085595A - Method of producing wiring circuit board - Google Patents
Method of producing wiring circuit boardInfo
- Publication number
- JPS6085595A JPS6085595A JP19363783A JP19363783A JPS6085595A JP S6085595 A JPS6085595 A JP S6085595A JP 19363783 A JP19363783 A JP 19363783A JP 19363783 A JP19363783 A JP 19363783A JP S6085595 A JPS6085595 A JP S6085595A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- hole
- film
- board
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、配線回路基板の製造方法に係り、特に、基板
の表面および裏面に形成された配線・ぐターンを、スル
ーホールを介して電気的に接続するための方法に関する
。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for manufacturing a printed circuit board, and in particular, to a method for manufacturing a printed circuit board, and in particular, to electrically connect wiring/guts formed on the front and back surfaces of the board through through holes. related to a method for connecting to
基板の表面および裏面に形成された配線パターンを、電
気的に接続する方法の１つとして、基板の所定部分にス
ルーホールと呼ばれる貫通孔をあけ、このスルーホール
を介して、表裏の配線ノやターンを接続する方法が考え
られている。One way to electrically connect the wiring patterns formed on the front and back sides of the board is to make a through hole called a through hole in a predetermined part of the board, and to connect the wiring patterns on the front and back sides through the through hole. A method of connecting the turns has been considered.
たとえば、スクリーン印刷法によって形成される厚膜回
路基板の場合は、スルーホール１を有する基板２上に、
配線パターン３を形成するに際して、スルーホールに対
応する部分にも、インクとしての導電性イーストが塗布
とれるように構成されたスクリーンを使用し、第１図に
示す如く、・ぞターン形成を行なう。この後、導電性ペ
ーストのチクソトロピー性を利用し、スルーホール内部
へ、該導電性イーストを流し込むか、あるいは、セラミ
、２り基板の下方より該導気性ペーストを吸引する等の
方法によって、スルーホールの内壁に導体膜を形成する
という方法がとられている。For example, in the case of a thick film circuit board formed by screen printing, on a substrate 2 having through holes 1,
When forming the wiring pattern 3, a screen configured to be able to apply and remove conductive yeast as an ink is also used in the portion corresponding to the through hole, and as shown in FIG. 1, a turn is formed. After that, the conductive yeast is poured into the through hole using the thixotropic property of the conductive paste, or the conductive paste is sucked from below the ceramic or two-layer substrate. A method has been adopted in which a conductive film is formed on the inner wall of the
しかしながら、この方法ではスルーホール内部で、導電
性ペーストがその表面張力によって、つながったままで
内部には流れず、第２図に示すような状態となり、表裏
の接続が不完全ＶＬ−なる場合が多い。また、表裏の接
続はなされたとしても、導体膜の厚みにばらつきが発生
し易く、抵抗値の増加、あるいは、ピンホールの発生を
もたらすことがしばしばであった。However, with this method, the conductive paste remains connected inside the through hole due to its surface tension and does not flow inside, resulting in a state as shown in Figure 2, which often results in incomplete connection between the front and back sides. . Further, even if the front and back connections are made, variations in the thickness of the conductor film tend to occur, often resulting in an increase in resistance value or the formation of pinholes.
本発明は、前記実情に鑑みてなされたもので、スルーポ
ール全弁して、表裏の配線回路を確実に接続し、信頼性
の高い配線回路基板を提供すること全目的とする。The present invention has been made in view of the above-mentioned circumstances, and its entire purpose is to provide a highly reliable wired circuit board that uses all through-pole valves to reliably connect the wired circuits on the front and back sides.
前記目的を達成するため、本発明の方法は、スルーホー
ルを介して、基板の表面および裏面の配線・ヤターンを
接続するにあたり、無電解メッキによって少なくともス
ルーホール内壁に導体膜を形成する工程を含むことを特
徴とする。In order to achieve the above object, the method of the present invention includes the step of forming a conductive film on at least the inner wall of the through hole by electroless plating when connecting the wiring/wires on the front and back surfaces of the substrate through the through hole. It is characterized by
すなわち、たとえばまず、基板内に形成されたスルーホ
ールおよびその周辺領域のみを除いて、他を１７ノスト
被覆したのち、無電解メッキ法によって、スルーホール
およびその周辺領域に銅、金。That is, for example, first, except for the through-holes formed in the substrate and their surrounding areas, the rest is coated with 17 nods, and then the through-holes and their surrounding areas are coated with copper and gold by electroless plating.
ニッケル等のメッキ生成膜を１〜１０μｍの厚さに形成
する。A plating product film of nickel or the like is formed to a thickness of 1 to 10 μm.
その後、レジストｅ除去し、基板の表面および裏面にス
クリーン印刷法等によυ金、タングステン、モリブデン
等の導電体層を２〜６μｍの厚さに形成し、通常の方法
によって、所望の回路パターン全形成する◇
このようにして形成された配線回路基板は、スルーホー
ル内壁に生成された均一な厚さのメッキ生成膜によって
、両面のパターンが確実に接続されており、極めて信頼
性が高い。Thereafter, the resist e is removed, and a conductive layer of gold, tungsten, molybdenum, etc. is formed on the front and back surfaces of the substrate to a thickness of 2 to 6 μm by screen printing, etc., and a desired circuit pattern is formed by a normal method. Fully formed ◇ The printed circuit board formed in this way has extremely high reliability as the patterns on both sides are reliably connected by the uniformly thick plating film formed on the inner wall of the through hole.
以下、本発明実施例の配線回路基板の製造方法について
、図面を参照しつつ説明する。Hereinafter, a method for manufacturing a printed circuit board according to an embodiment of the present invention will be described with reference to the drawings.
寸ず、第３図に示す如く、セラミック基板１１の所定位
置に、スルーホール１２を形成する。Immediately, as shown in FIG. 3, a through hole 12 is formed in a predetermined position of the ceramic substrate 11.
次いで、スピンコーターを用いて、該セラミック基板の
表面全体にフォトレノストヲ塗布した後、露光処理およ
び現像処理を行ないスルーホール１２の周辺領域１３を
除く部分に第１のレノストパターン１４ｆ：形成する。Next, a photorenost is applied to the entire surface of the ceramic substrate using a spin coater, and then exposure and development are performed to form a first renost pattern 14f in a portion excluding the peripheral area 13 of the through hole 12. .
更に、同様にして、該セラミック基板裏面のスルーホー
ル１２の周辺領域１５を除く部分に第２のレジストパタ
ーン１６を形成する。Furthermore, in the same manner, a second resist pattern 16 is formed on the back surface of the ceramic substrate except for the peripheral area 15 of the through hole 12.
このようにして、スルーホールの周辺領域以外の部分を
レジスト膜によって被覆したセラミック基板１１を、金
ゾγン化カリ、塩化Ｔンモン、クエン酸ソーダ、次亜リ
ン酸ソーダからなる無電解メッキ液に浸漬し、第５図に
示す如く、露呈部に、金のメッキ生成膜１７を形成する
。In this way, the ceramic substrate 11 whose parts other than the peripheral areas of the through-holes are covered with a resist film is coated with an electroless plating solution consisting of gold potassium chloride, tungsten chloride, sodium citrate, and sodium hypophosphite. As shown in FIG. 5, a gold plating film 17 is formed on the exposed portion.
この後、レゾスト膜を除去することにより、第６図に示
す如くスルーホールの周辺領域のみに金のメッキ生成膜
１７を有するセラミック基板を得る。Thereafter, by removing the resist film, a ceramic substrate having a gold plating film 17 only in the peripheral area of the through hole is obtained as shown in FIG.
更に、蒸着法により、前記セラミック基板の表面全体、
次いで裏面全体に第７図に示す如く銅薄膜１８を着膜形
成する。蒸着に際しては、スルーホールおよびその周辺
領域には、この銅薄膜が着膜されないように、たとえば
、感光性レゾストフィルム等を用いて、スルーホールの
表面および裏面を被覆しておく。Furthermore, by a vapor deposition method, the entire surface of the ceramic substrate,
Next, a copper thin film 18 is deposited on the entire back surface as shown in FIG. During vapor deposition, the front and back surfaces of the through hole are covered with, for example, a photosensitive resist film or the like so that the copper thin film is not deposited on the through hole and its surrounding area.
そして、通常の方法で前記セラミック基板の表面および
裏面に夫々第３．第４のレジストパターン１９．２０を
第８図に示す如く形成する。Then, a third layer is applied to the front and back surfaces of the ceramic substrate using a conventional method. Fourth resist patterns 19 and 20 are formed as shown in FIG.
このようにして、レジスト／ぐターンの形成されたセラ
ミック基板を過硫化アンモンと塩化第２水銀とからなる
エツチング液に浸漬したのち、第３゜第４のレジスト・
ぐターンを除去することにより、第９図に示す如く、所
定の銅パターン２１を有する、配線回路基板の形成が行
なわれる。After the ceramic substrate on which the resist pattern was formed in this way was immersed in an etching solution consisting of ammonium persulfide and mercuric chloride, the third and fourth resist layers were immersed.
By removing the traces, a wired circuit board having a predetermined copper pattern 21 is formed as shown in FIG.
このようにして形成された配線回路基板はスルーホール
の内壁が均一なメッキ生成膜によって確実に導体化され
ているため、セラミック基板の表面および裏面に形成さ
れた配線層は確実に接続されており、配線回路基板とし
ての信頼性が極めて高い。In the printed circuit board formed in this way, the inner walls of the through holes are reliably made conductive by the uniform plating film, so the wiring layers formed on the front and back surfaces of the ceramic board are reliably connected. , extremely reliable as a printed circuit board.
なお、実施例においては、配線回路を蒸着法で形成した
薄膜パターンで構成したが、スクリーン印刷法による厚
膜ノ七り−ンで構成にも良いことは言うまでもない。In the embodiment, the wiring circuit is constructed using a thin film pattern formed by a vapor deposition method, but it goes without saying that a thick film pattern formed by a screen printing method may also be used.
また、スルーホール内壁への導体膜の形成は、基板の表
面および裏面への配線ノ４ターンの形成に先立って行な
ったが、必要に応じて、配線・ぐタ−ンの形成後に、無
電解メッキを行なうことも可能である。この場合は、既
に形成されている配線／やターンをレソストフィルム等
によって保護しておくことが大切である。In addition, the conductor film was formed on the inner wall of the through hole prior to the formation of the four turns of wiring on the front and back sides of the board, but if necessary, after the formation of the wiring and patterns, electroless It is also possible to perform plating. In this case, it is important to protect the already formed wiring/turns with a resist film or the like.
加°えて、絶縁フィルム等を介してこの方法によって形
成された配線回路パターンを複数枚重ね、一度にプレス
圧着を施すことに上り、多層基板を形成することも可能
である。In addition, it is also possible to form a multilayer board by stacking a plurality of wiring circuit patterns formed by this method via an insulating film or the like and applying pressure bonding at once.
以上、説明してきたように、本発明の方法によれば、基
板の表面および裏面に形成された導体層を、基板を貫通
するスルーホールを介して接続するにあたり、無電解メ
ッキによって該スルーホールの内壁に導体膜を形成し、
この導体膜を介して表面および裏面の配線パターンとを
接続することにより、信頼性の高い配線回路基板を形成
することが可能となる。As described above, according to the method of the present invention, when connecting the conductor layers formed on the front and back surfaces of the substrate through the through-holes penetrating the substrate, the through-holes are formed by electroless plating. A conductive film is formed on the inner wall,
By connecting the wiring patterns on the front and back surfaces through this conductive film, it is possible to form a highly reliable wired circuit board.
第１図乃至第２図は、従来の厚膜法に基づくスルーホー
ルへの導体膜の形成工程の一部を示すｍ−、第３図乃至
第９図は、本発明実施例の配線回路基板の形成工程を示
す図である。
１・・・スルーホール、 ２・・基板、３・・・配ｍパ
ターン、 １１・・・セラミヴク基板、１２・・・スル
ーホール、１３・・・周辺領域、１４・・・第１のレノ
ストパターン、
１５・・・周辺領域、
１６・・・第２のレノストパターン、
１７・・・メッキ生成膜、１８・・・銅薄膜、１９・・
・第３のレノストパターン。
２０・・・第４のレノストパターン。
２１・・・銅パターン。
第１図
第３図
第７図1 to 2 show part of the process of forming a conductor film in a through hole based on a conventional thick film method, and FIGS. 3 to 9 show a printed circuit board according to an embodiment of the present invention. It is a figure which shows the formation process of. DESCRIPTION OF SYMBOLS 1...Through hole, 2...Board, 3...M pattern, 11...Ceramic board, 12...Through hole, 13...Peripheral area, 14...First renost Pattern, 15... Peripheral area, 16... Second Rennost pattern, 17... Plating generated film, 18... Copper thin film, 19...
-Third Rennost pattern. 20...Fourth Rennost pattern. 21...Copper pattern. Figure 1 Figure 3 Figure 7
Claims (1)
されたスルーホールを介して電気的に接続されている構
造をもつ配線回路基板の製造方法において、無電解メッ
キによって前記スルーホールの内壁に導体膜を形成する
工程を含むことを特徴とする配線回路基板の製造方法。In a method for manufacturing a printed circuit board having a structure in which wiring layers on the front and back sides of the board are electrically connected via through holes formed at predetermined positions on the board, the inner walls of the through holes are coated by electroless plating. A method for manufacturing a printed circuit board, the method comprising the step of forming a conductor film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19363783A JPS6085595A (en) | 1983-10-17 | 1983-10-17 | Method of producing wiring circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19363783A JPS6085595A (en) | 1983-10-17 | 1983-10-17 | Method of producing wiring circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6085595A true JPS6085595A (en) | 1985-05-15 |
Family
ID=16311251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19363783A Pending JPS6085595A (en) | 1983-10-17 | 1983-10-17 | Method of producing wiring circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6085595A (en) |
-
1983
- 1983-10-17 JP JP19363783A patent/JPS6085595A/en active Pending
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