JPS62171194A - Matrix wiring board - Google Patents
Matrix wiring boardInfo
- Publication number
- JPS62171194A JPS62171194A JP1198486A JP1198486A JPS62171194A JP S62171194 A JPS62171194 A JP S62171194A JP 1198486 A JP1198486 A JP 1198486A JP 1198486 A JP1198486 A JP 1198486A JP S62171194 A JPS62171194 A JP S62171194A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating layer
- wiring board
- conductive
- matrix wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 title claims description 13
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000007650 screen-printing Methods 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 4
- 230000007261 regionalization Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
[a業上の利用分野]
本発明は、絶縁層およびその上下に形成された導体層を
有するマトリクス配線板に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application in Industry] The present invention relates to a matrix wiring board having an insulating layer and conductor layers formed above and below the insulating layer.
[従来の技術]
従来、この種のマトリクス配線板では、第1導電層(以
下第1層という)と第2導電層(以下第2層という)と
の間に配される絶縁層は印刷法により形成されるが、こ
の場合、絶縁層に生じつるピンホールによる第1層と第
2層とのショートの発生を防ぐために、絶縁層を2回印
刷している。[Prior Art] Conventionally, in this type of matrix wiring board, an insulating layer disposed between a first conductive layer (hereinafter referred to as the first layer) and a second conductive layer (hereinafter referred to as the second layer) is formed using a printing method. However, in this case, the insulating layer is printed twice to prevent short circuits between the first layer and the second layer due to pinholes formed in the insulating layer.
[発明が解決しようとする問題点コ
しかしながら、第1層と第2層との導通を得るために設
けられる絶縁層のスルーホール部分等において、その部
分に形成される段差部の基板に対しての傾斜が急峻とな
る。特に、第2層が蒸着法あるいはスパッタ法等により
形成された薄膜である場合には、続くパターン形成時の
)才トリソグラフイエ程において、2つの絶縁層で形成
される段差部ではレジストが他の部分に比べて3倍程度
厚くなるため、露光量を他の部分に合わせて調整すると
段差部においてパターンにショートが生じ、−万般差部
に合せて露光量を合せ調整すると他の部分のパターンが
断線部分(オープン)が生じるという問題点があった。[Problems to be Solved by the Invention] However, in the through-hole portion of the insulating layer provided to obtain electrical conduction between the first layer and the second layer, the step portion formed in that portion may be The slope becomes steep. In particular, if the second layer is a thin film formed by vapor deposition or sputtering, the resist may be removed from the resist at the step formed by the two insulating layers during the subsequent trilithography step (during pattern formation). If you adjust the exposure amount to match other parts, a short circuit will occur in the pattern at the step part, and if you adjust the exposure amount to match the difference part, the pattern in other parts will become thicker. However, there was a problem in that disconnections (opens) occurred.
[問題点を解決するための手段]
本発明は、かかる問題点を解決し、第2回目の絶縁層を
形成に際してはそのパターンを第1回目とは異ならせ、
段差部の傾斜形状を緩やかなものとすることにより、第
2層のパターン形成を容易にしかも確実に行い得るマト
リクス配線板を提供することを目的とする。[Means for solving the problem] The present invention solves the problem, and when forming the second insulating layer, the pattern is different from that of the first time,
It is an object of the present invention to provide a matrix wiring board in which pattern formation of a second layer can be easily and reliably performed by making the slope of the stepped portion gentle.
そのため、本発明では、基板上に配置された第1導電層
と、第1導電層上に配置され、その導通部を露出する穴
部を有する第1絶縁層と、第1絶縁層上に配置され、第
1絶縁層の穴部の表面を覆って導通部を露出する穴部を
有する第2絶縁層と、第2絶縁層上に成膜およびフォト
リソグラフィ工程を含む工程により配置され、絶縁部材
の穴部を介して第1導電層の導電部に接触する部分を有
する第2導電層とを具えたことを特徴とする。Therefore, in the present invention, there is provided a first conductive layer disposed on a substrate, a first insulating layer disposed on the first conductive layer and having a hole portion exposing a conductive portion thereof, and a first insulating layer disposed on the first insulating layer. a second insulating layer having a hole that covers the surface of the hole in the first insulating layer and exposes a conductive portion; and a second conductive layer having a portion that contacts the conductive portion of the first conductive layer through the hole.
[作 用コ
すなわち、本発明によれば、第2絶縁層は第1絶縁層の
穴部の表面を覆って基板に対し緩やかな傾斜形状を有す
る穴部をもって配置されているので、第2導電層が容易
かつ確実に形成される。[Function] That is, according to the present invention, the second insulating layer is disposed with the hole having a gentle slope shape with respect to the substrate, covering the surface of the hole in the first insulating layer, so that the second conductive layer Layers are formed easily and reliably.
[実施例] 以下、図面を参照して本発明の詳細な説明する。[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.
第1図は本発明に係るマトリクス配線板の一構成例を示
す。ここで、1はガラスやセラミック等の基板、2は銀
もしくは銅等の導体ペーストを基板1上に印刷した第1
層である。3および4は、それぞれ、第1回目および第
2回目に形成された絶縁体であり、エポキシ樹脂あるい
はポリイミド樹脂を用い、スクリーン印刷により形成で
きる。FIG. 1 shows an example of the structure of a matrix wiring board according to the present invention. Here, 1 is a substrate made of glass or ceramic, etc., and 2 is a first plate made of conductive paste such as silver or copper printed on the substrate 1.
It is a layer. 3 and 4 are insulators formed in the first and second steps, respectively, and can be formed by screen printing using epoxy resin or polyimide resin.
5は成膜およびフォトリソグラフィ工程で形成した第2
層である。5 is the second layer formed by film formation and photolithography process.
It is a layer.
第2図ないし第4図は第1図示のマトリクス配線板を製
造するための順次のプロセスの一例を示す。まず、第2
図に示すように、基板1上に、スクリーン印刷法により
導体ペーストを印刷し、第1層2を得る。FIGS. 2 through 4 show an example of a sequential process for manufacturing the matrix wiring board shown in FIG. First, the second
As shown in the figure, a conductive paste is printed on a substrate 1 by a screen printing method to obtain a first layer 2.
次に、第3図に示すように、スクリーン印刷により、第
1層2と第2層5との導通部分において第1層2と第2
層5とが接触するようにスルーホール3Aを有する絶縁
層3を、絶縁樹脂を用いて形成する。本例では、この絶
縁層3の厚みを15μm〜20μmとした。Next, as shown in FIG. 3, by screen printing, the first layer 2 and the second layer
An insulating layer 3 having a through hole 3A so as to be in contact with layer 5 is formed using an insulating resin. In this example, the thickness of this insulating layer 3 was set to 15 μm to 20 μm.
次に、第4図に示すように、同線にスクリーン印刷によ
りスルーホール4Aを有する絶縁層4を形成する。この
とき、本例にあっては、印刷パターンを第1回目に形成
した絶縁層3の印刷パターンより150μm程度全体に
拡張したものとした。而して、成n莫およびフォトリソ
グラフィ工程により、第2層5を絶縁層4上に形成し、
第1図示のマトリクス配線板を得る。Next, as shown in FIG. 4, an insulating layer 4 having through holes 4A is formed on the same lines by screen printing. At this time, in this example, the printed pattern was expanded to a total area of about 150 μm from the printed pattern of the insulating layer 3 formed the first time. Then, a second layer 5 is formed on the insulating layer 4 by a photolithography process,
The matrix wiring board shown in the first diagram is obtained.
これにより、第5図および第6図に示すように絶縁層1
3に対してパターンを変更しない絶縁層14を設けた場
合よりも、第7図に示すように段差部の傾斜形状が緩や
かとなり、従って第2層形成が容易となるとともに、オ
ープンやショートの発生を防止でき確実なパターン形成
が可能となる。As a result, as shown in FIGS. 5 and 6, the insulating layer 1
As shown in FIG. 7, the slope of the stepped portion becomes gentler than when the insulating layer 14 whose pattern is not changed is provided, making it easier to form the second layer and preventing the occurrence of opens and shorts. This enables reliable pattern formation.
具体的には、パターン変更を行わない場合には基板1の
面から絶縁層上面までの段差部の基板に対する傾斜角度
が約20度であったものが、本例の如くパターンを異な
らせた場合には約6度程度まで緩やかにすることが可能
となる。従って、この後の工程で第2層を蒸着法あるい
はスパッタ法により薄膜で形成する場合に、この第2層
のパターン形成時のフォトリングラフィ工程で絶縁層段
差部でのレジストの厚さを、段差部の傾斜角度が減少し
たことによって従来のような絶縁層形成を行ったものよ
り半分程度とすることが可能となり、以て従来パターニ
ング時に発生したオープンやショートの除去か可能とな
る。Specifically, when the pattern is not changed, the angle of inclination of the stepped portion from the surface of the substrate 1 to the top surface of the insulating layer with respect to the substrate is approximately 20 degrees, but when the pattern is changed as in this example, It is possible to gradually reduce the temperature to about 6 degrees. Therefore, when the second layer is formed as a thin film by vapor deposition or sputtering in a subsequent step, the thickness of the resist at the stepped portion of the insulating layer is By reducing the inclination angle of the stepped portion, it becomes possible to reduce the inclination angle to about half that of the insulating layer formed in the conventional method, thereby making it possible to eliminate opens and shorts that occur during conventional patterning.
なお、本実施例においては、第1層をパターン印刷によ
る厚膜に形成した場合について述へたか、本発明は第1
層を成膜およびフォトリングラフィ工程を含む工程によ
り薄膜に形成したマトリクス配線板にも極めて有効に適
用できるのは勿論である。In addition, in this example, the case where the first layer is formed into a thick film by pattern printing has been described, but the present invention
Of course, the present invention can also be very effectively applied to matrix wiring boards formed into thin films by processes including film formation and photolithography processes.
[発明の効果]
以上説明したように、本発明によれば、第2回目の絶縁
層を形成するに際してはそのパターンを第1回目とは異
ならせ、スルーホール部分等の段差部の傾斜を緩やかな
ものとしたので、第2層のパターン形成を容易に、しか
も確実に行うことができ、以て信頼性の高いマトリクス
配線板を得ることができる。[Effects of the Invention] As explained above, according to the present invention, when forming the second insulating layer, the pattern is different from the first, and the slope of the stepped portion such as the through hole portion is made gentler. As a result, pattern formation of the second layer can be easily and reliably performed, and a highly reliable matrix wiring board can thus be obtained.
第1図は本発明に係るマトリクス配線板の一構成例を示
す断面図、
第2図ないし第4図は第1図示のマトリクス配線板を製
造するための順次のプロセスの一例を示す断面図、
第5図は第2回目の絶縁層形成に際して第1回目の形成
とはパターンを変更しなかった71〜リクス配線板の一
例を示す断面図、
第6図および第7図は、それぞれ、第5図および第1図
に示したマトリクス配線板の段差部分の形状を説明する
ための断面図である。
1・・・基板、
2・・・第1層、
3.13・・・第1回目に形成する絶縁層、4.14・
・・第2回目に形成する絶縁層、5・・・第2層。FIG. 1 is a sectional view showing an example of the structure of a matrix wiring board according to the present invention; FIGS. 2 to 4 are sectional views showing an example of a sequential process for manufacturing the matrix wiring board shown in FIG. 1; FIG. 5 is a cross-sectional view showing an example of a 71-RIX wiring board in which the pattern was not changed from the first formation during the second insulating layer formation, and FIG. 6 and FIG. FIG. 2 is a cross-sectional view for explaining the shape of a stepped portion of the matrix wiring board shown in the drawings and FIG. 1; DESCRIPTION OF SYMBOLS 1... Substrate, 2... First layer, 3.13... Insulating layer formed at the first time, 4.14.
... Insulating layer formed second time, 5... Second layer.
Claims (1)
を有する第1絶縁層と、 該第1絶縁層上に配置され、前記第1絶縁層の穴部の表
面を覆って導通部を露出する穴部を有する第2絶縁層と
、 該第2絶縁層上に成膜およびフォトリソグラフィ工程を
含む工程により配置され、前記絶縁部材の穴部を介して
前記第1導電層の導電部に接触する部分を有する第2導
電層とを具えたことを特徴とするマトリクス配線板。 2)特許請求の範囲第1項記載のマトリクス配線板にお
いて、前記第1および第2絶縁層はスクリーン印刷によ
り形成されることを特徴とするマトリクス配線板。[Scope of Claims] 1) a first conductive layer disposed on a substrate; a first insulating layer disposed on the first conductive layer and having a hole exposing a conductive portion thereof; and the first insulating layer. a second insulating layer disposed on the second insulating layer and having a hole portion that covers the surface of the hole portion of the first insulating layer and exposes a conductive portion; and a step including a film formation and photolithography process on the second insulating layer. and a second conductive layer having a portion disposed in the insulating member and in contact with the conductive portion of the first conductive layer through the hole of the insulating member. 2) The matrix wiring board according to claim 1, wherein the first and second insulating layers are formed by screen printing.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1198486A JPS62171194A (en) | 1986-01-24 | 1986-01-24 | Matrix wiring board |
US08/076,705 US5314788A (en) | 1986-01-24 | 1993-06-15 | Matrix printed board and process of forming the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1198486A JPS62171194A (en) | 1986-01-24 | 1986-01-24 | Matrix wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62171194A true JPS62171194A (en) | 1987-07-28 |
Family
ID=11792859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1198486A Pending JPS62171194A (en) | 1986-01-24 | 1986-01-24 | Matrix wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62171194A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05343853A (en) * | 1992-06-09 | 1993-12-24 | Fujitsu Ltd | Formation through hole in multilayer insulating film |
JP2012069854A (en) * | 2010-09-27 | 2012-04-05 | Cmk Corp | Multilayer printed wiring board and manufacturing method therefor |
-
1986
- 1986-01-24 JP JP1198486A patent/JPS62171194A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05343853A (en) * | 1992-06-09 | 1993-12-24 | Fujitsu Ltd | Formation through hole in multilayer insulating film |
JP2012069854A (en) * | 2010-09-27 | 2012-04-05 | Cmk Corp | Multilayer printed wiring board and manufacturing method therefor |
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