JPH05259456A - 薄膜ｓｏｉ装置 - Google Patents

薄膜ｓｏｉ装置

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Publication number
JPH05259456A
JPH05259456A JP4337036A JP33703692A JPH05259456A JP H05259456 A JPH05259456 A JP H05259456A JP 4337036 A JP4337036 A JP 4337036A JP 33703692 A JP33703692 A JP 33703692A JP H05259456 A JPH05259456 A JP H05259456A
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JP
Japan
Prior art keywords
oxide layer
layer
region
laterally
silicon
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Granted
Application number
JP4337036A
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English (en)
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JP3456716B2 (ja
Inventor
Steven Merchant
マーチャント スティーブン
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Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
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Publication of JPH05259456A publication Critical patent/JPH05259456A/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

(57)【要約】 （修正有） 【目的】 外部電界から生じる問題を受けず、且つ高耐
圧で低いオン抵抗を有するＳＯＩ装置を提供することを
目的とする。 【構成】 本発明はＳＯＩ型の高電圧薄膜トランジスタ
を作るための構造と方法との改善を伴っている。特に、
本発明は、外部電界からドリフト領域を遮蔽し且つオン
状態抵抗を低減するように、ゲート電極７が線型なドー
ピング形態４上に延在して形成されている、この改善さ
れた構造を作るための構造と技術とを述べている。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、埋め込み酸化物層と、
前記埋め込み酸化物層上の横方向に実質的に線型なドー
ピング領域を有する珪素の薄層と、前記珪素の薄層上の
上部酸化物層と、前記薄層の一端におけるゲート領域
と、前記薄層の対向端におけるドレイン領域、及び前記
ゲート領域から横方向に分離されたソース領域を具えて
いる薄膜ＳＯＩ（Silicon-On-Insulator）装置に関する
ものである。
【０００２】
【従来の技術】そのような装置は欧州特許出願第497427
号から既知である。高電圧集積回路技術における主な問
題点は、構成要素と補助回路部分との絶縁の問題に対す
る十分な解答を見出すことである。既知の装置において
は、横方向に線型なドーピング形態がＳＯＩ装置の珪素
層内に形成される。更にその上、既知の装置ではその珪
素層は約 200〜300 nmの厚さを有する珪素の薄層として
設けられる。この構造が高い破壊電圧特性を有するＳＯ
Ｉ半導体装置を形成する。
【０００３】この基本的構造は、ウエファの表面上の湿
気又はその他の塵埃により起こされて、ゲートとドレイ
ンとの間のドリフト領域、すなわち線型なドーピング領
域上に働く、外部電界から生じる問題を受ける。更にそ
の上、従来構造は必要よりも高いオン抵抗を有する。
【０００４】
【発明が解決しようとする課題】本発明はこの従来構造
を改善することを探究するものである。
【０００５】
【課題を解決するための手段】それ故にこの装置は、前
記ゲート領域がゲート電極を含んでおり且つ電界板が前
記横方向に線型なドーピング領域上に前記ゲート領域か
ら延在していることを特徴とする。ゲート電極は上側酸
化物層により覆われているドリフト領域の一方側に形成
される。従って、ゲート電極が珪素層の下にあるドリフ
ト領域の全部を覆うようにこの酸化物層の上部を横方向
にわたってゲート領域から延在する。
【０００６】更にその上、上部酸化物層が絶縁層上の珪
素の下の埋め込み酸化物層と同じ厚さによって作られた
場合に、この構造が大幅に改善されることが見出され
た。形成されるトランジスタのソース領域とドレイン領
域とはこのＳＯＩ層の対向側部に形成される。
【０００７】この構造に付加される利点は、二倍の導電
電荷がこのドリフト領域内に置かれ得るようにドリフト
領域を上部と底部との両方から空乏化する能力である。
これがこの装置のオン抵抗を低減する。
【０００８】この改善された構造を製造する方法は、半
導体基板上に形成されている埋め込み酸化物層と共に埋
め込み酸化物層上に珪素層を形成すること、この珪素層
内に横方向に線型なドーピング領域を形成すること、局
部的酸化（ＬＯＣＯＳ）によりドリフト領域を選択的に
薄くすること、ドリフト領域上の薄い上部酸化物層をそ
のままにすること、及び上部酸化物層のほとんどの部分
上に横方向に延在している部分と共にゲート電極を有す
るゲート領域により上部酸化物層の側部にゲート領域を
形成することを具えており、そこでゲート電極の横方向
の延長が薄い横方向に線型なドーピング領域上にある。
本発明のこの技術が本発明の改善を有する高電圧ＳＯＩ
半導体装置を達成する。
【０００９】
【実施例】以下、図面を参照して、実例によって、本発
明を詳細に説明しよう。図中の同じ符号はそれぞれの図
の相当する部分を確認するために用いられている。
【００１０】本発明の改善されたＳＯＩトランジスタが
図１に図解されている。ここで、あらゆる固有抵抗のｎ
形又はｐ形導電型のいずれであってもよい基板３が与え
られる。酸化物層２はこの基板層の上に堆積される。酸
化物層２の厚さは約１〜1.5μm の範囲にある。酸化物
層２上に線型な横方向ドーピング領域４を有する珪素層
１が形成される。この線型な横方向ドーピング領域の形
成は欧州特許出願第497427号における形成と類似してい
る。今や埋め込み酸化物層２を形成している酸化物層２
によって、この方法でＳＩＯ構造が形成される。ＳＯＩ
装置の範囲は絶縁材料の絶縁領域５により取り囲まれて
いる。珪素層１は標準局部的酸化技術により 100〜200
nmの厚さ範囲へ選択的に薄くされる。これは線型な横方
向ドーピング領域４の周りに窒化珪素のマスクを用いる
こと、及び熱二酸化珪素６の１〜1.5 μm 厚さ層の成長
を伴う。このことがＳＯＩ装置のドリフト領域を与える
横方向の線型なドーピング形態を有する薄くされた層４
を残す。
【００１１】多結晶珪素ゲート電極及び電界板７が熱二
酸化珪素６の側部に約60nmの厚さを有する薄いゲート酸
化物８を最初に成長させることにより形成される。その
後、500nmの多結晶珪素がゲート電極及び電界板領域を
形成するためにその上に堆積される。本発明に従って、
二酸化珪素層６の上側面を露出するように、マスクがゲ
ート電極７を形成する前に設けられるので、ゲート電極
７は電界板領域として上側二酸化珪素層６の表面上へ延
在する。
【００１２】この電界板は薄くされた珪素層４のドリフ
ト領域部分上にゲート電極から延在している。ソース及
びドレイン領域10はその時、例えばゲート及びドリフト
領域の側部に、Ｎ＋導電型で形成される。Ｐ＋ソース領
域11もソース接点12が両領域と接触するように形成され
る。ドレイン接点12′がドレイン領域10と接触して形成
され、一方ゲート接点12″が薄いゲート酸化物８の上に
あるゲート領域７と接触して形成される。上部二酸化珪
素層６は埋め込み酸化物層２と等しい厚さによって形成
される。また、ゲート電極の電界板７がドリフト領域４
上に横方向に延在している。
【００１３】ウエファの表面上の湿気又はその他の荷電
塵埃により生じるあらゆる侵害的な外部電界が、ドリフ
ト領域の上にあるゲート電極の電界板上で終わるので、
よく保護されたドリフト領域４が設けられる。更に、ド
リフト領域が今や上部と底部との両方から空乏化され得
るので、二倍の導電電荷がオン抵抗を低減するためにド
リフト領域上へ置かれ得る。それに加えて、ＳＯＩフイ
ルムはソース及びドレイン領域においては厚く（0.75〜
1.25μm ）、Ｐ型体９は既知の装置におけるように浮動
のまではない。
【００１４】図２は本発明の電界板及びゲート７を有す
る典型的な装置における等静電位線を、コンピュータシ
ュミレートした曲線を示している。そのようなＳＯＩ装
置は約 710ボルトの高い破壊電圧を有する。最良化され
たドリフト領域は、ゲート電極及び電界板７を有しない
同じ構造のドリフト領域の二倍であるドレイン領域の近
くにピークドーピングを有する横方向ドーピング形態ｎ
（ｘ）を有する。ドリフト領域４の最低ドリフト領域ド
ーピング、すなわちゲート構造に向かう最低ドリフト領
域ドーピングも２の係数により増大される。
【図面の簡単な説明】
【図１】本発明による改善された薄膜トランジスタを断
面図で図解している。
【図２】本発明による横方向ゲート延在部を有する装置
におけるコンピュータシュミレートした等静電位線を図
解している。
【符号の説明】
１ 珪素層 ２ 埋め込み酸化物層 ３ 基板 ４ 線型の横方向のドーピング領域 ５ 絶縁領域 ６ 熱二酸化珪素 ７ 多結晶珪素ゲート電極及び電界板 ８ 薄いゲート酸化物 ９ Ｐ型体 10 ソース及びドレイン領域 11 Ｐ＋ソース領域 12 ソース接点 12′ドレイン接点 12″ゲート接点

Claims (10)

    【特許請求の範囲】
  1. 【請求項１】埋め込み酸化物層と、前記埋め込み酸化物
    層上の横方向に実質的に線型なドーピング領域を有する
    珪素の薄層と、前記珪素の薄層上の上部酸化物層と、前
    記薄層の一端におけるゲート領域と、前記薄層の対向端
    におけるドレイン領域、及び前記ゲート領域から横方向
    に分離されたソース領域を具えている薄膜ＳＯＩ装置に
    おいて、 前記ゲート領域がゲート電極を含んでおり且つ電界板が
    前記横方向に線型なドーピング領域上に前記ゲート領域
    から延在していることを特徴とする薄膜ＳＯＩ装置。
  2. 【請求項２】前記埋め込み酸化物層と前記上部酸化物層
    とが同じ厚さを有することを特徴とする請求項１記載の
    薄膜ＳＯＩ装置。
  3. 【請求項３】前記埋め込み酸化物層及び前記上部酸化物
    層が各々約１〜1.5 μm の厚さ範囲を有することを特徴
    とする請求項１記載の薄膜ＳＯＩ装置。
  4. 【請求項４】前記珪素の層が 100〜200 nmの厚さ範囲を
    有することを特徴とする請求項１記載の薄膜ＳＯＩ装
    置。
  5. 【請求項５】前記ゲート電極及び前記電界板が各々500
    nmの厚さを有することを特徴とする請求項１記載の薄膜
    ＳＯＩ装置。
  6. 【請求項６】次のステップ、すなわち、 (a) 埋め込み酸化物層上に珪素層を形成するステップで
    あって、前記埋め込み酸化物層は半導体基板上に形成さ
    れるステップと、 (b) 前記珪素層内に横方向に実質的に線型なドーピング
    領域を形成するステップ と、 (c) 低減された厚さへ前記横方向に線型なドーピング領
    域を同時に薄くし、且つこの薄くされた横方向に線型な
    ドーピング領域上に上部酸化物層を堆積するステップ、
    及び (d) 前記上部酸化物層の側部にゲート領域を形成するス
    テップであって、前記ゲート領域は前記上部酸化物層の
    ほとんどの部分上に横方向に延在する電界板と共にゲー
    ト電極を有し、前記電界板の横方向の延在は前記薄くさ
    れた横方向に線型なドーピング領域上にあるステップ
    と、 を具えている半導体装置を作る方法。
  7. 【請求項７】前記埋め込み酸化物層と前記上部酸化物層
    とが同じ厚さによって形成されることを特徴とする請求
    項６記載の方法。
  8. 【請求項８】前記埋め込み酸化物層と前記上部酸化物層
    とが各々約１〜1.5 μm の厚さにより形成されることを
    特徴とする請求項６記載の方法。
  9. 【請求項９】前記横方向に線型なドーピング領域が約 1
    00〜200 nmの厚さに薄くされることを特徴とする請求項
    ６記載の方法。
  10. 【請求項１０】前記ステップ(a) による珪素層が約0.75
    〜1.25μm の厚さに形成されることを特徴とする請求項
    ６記載の方法。
JP33703692A 1991-12-20 1992-12-17 薄膜ｓｏｉ装置 Expired - Fee Related JP3456716B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/811,554 US5246870A (en) 1991-02-01 1991-12-20 Method for making an improved high voltage thin film transistor having a linear doping profile
US07/811554 1991-12-20

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JPH05259456A true JPH05259456A (ja) 1993-10-08
JP3456716B2 JP3456716B2 (ja) 2003-10-14

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EP (1) EP0549042B1 (ja)
JP (1) JP3456716B2 (ja)
DE (1) DE69218155T2 (ja)

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DE69218155D1 (de) 1997-04-17
US5246870A (en) 1993-09-21
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