JPH05235138A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH05235138A JPH05235138A JP4031173A JP3117392A JPH05235138A JP H05235138 A JPH05235138 A JP H05235138A JP 4031173 A JP4031173 A JP 4031173A JP 3117392 A JP3117392 A JP 3117392A JP H05235138 A JPH05235138 A JP H05235138A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clock signal
- frequency
- integrated circuit
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路に関
し、特に、動作タイミングがクロック信号によって制御
される内部回路を有する半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having an internal circuit whose operation timing is controlled by a clock signal.
【０００２】[0002]
【従来の技術】従来、この種の半導体集積回路は、チッ
プ上で或る一定周期の源発クロック信号を発生し、この
クロック信号でチップ内の内部回路の動作タイミングを
制御する構成となっている。2. Description of the Related Art Conventionally, a semiconductor integrated circuit of this type has a structure in which a source clock signal of a certain fixed period is generated on a chip and the operation timing of an internal circuit in the chip is controlled by this clock signal. There is.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来の半導体
集積回路では、源発クロック信号の周波数が固定されて
いるので、内部回路の動作に伴なう発熱によって、連続
的に使用しているうちにチップの温度が上昇して行くの
を防ぐことが困難である。チップの温度が上昇すると、
集積回路内の素子特性が変化し、例えば、内部回路が誤
動作し集積回路内に組み込まれているプログラムが暴走
してしまうなどの不都合なことが起る。In the conventional semiconductor integrated circuit described above, since the frequency of the source clock signal is fixed, the heat generated by the operation of the internal circuit causes the internal clock to be continuously used. It is difficult to prevent the temperature of the chip from rising. When the temperature of the chip rises,
The element characteristics in the integrated circuit change, which may cause inconveniences such as malfunction of the internal circuit and runaway of the program incorporated in the integrated circuit.
【０００４】又、この集積回路の外装についてみると、
安価なプラスチップモールドパッケージは熱に対して弱
いので、熱容量は大きいけれども高価なセラミックパッ
ケージを使用せざるを得ず、経済的に不利である。Looking at the exterior of this integrated circuit,
Since an inexpensive plus chip mold package is weak against heat, it is economically disadvantageous because it has a large heat capacity but must use an expensive ceramic package.
【０００５】そこで、本発明の目的は、動作タイミング
がクロック信号によって制御される内部回路での発熱を
抑えた、動作の信頼性が高く安価な半導体集積回路を提
供することにある。Therefore, an object of the present invention is to provide a semiconductor integrated circuit which is highly reliable in operation and inexpensive, in which heat generation in an internal circuit whose operation timing is controlled by a clock signal is suppressed.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体集積回路
は、チップの温度上昇を感知しアラーム信号を出力する
温度センサと、この温度センサの出力信号により、クロ
ック信号を切り替えるセレクタ回路とを備えている。A semiconductor integrated circuit according to the present invention comprises a temperature sensor which senses a temperature rise of a chip and outputs an alarm signal, and a selector circuit which switches a clock signal by the output signal of the temperature sensor. ing.
【０００７】又、本発明の半導体集積回路は、チップの
温度上昇を感知しアラーム信号を出力する温度検出回路
と、源発クロック信号を入力して周波数の異なる複数の
クロック信号を出力する分周回路と、この温度検出回路
の出力信号により、クロック信号を切り替えるセレクタ
回路とを備えている。Further, the semiconductor integrated circuit of the present invention includes a temperature detection circuit which detects an increase in chip temperature and outputs an alarm signal, and a frequency division circuit which inputs a source clock signal and outputs a plurality of clock signals having different frequencies. A circuit and a selector circuit that switches the clock signal according to the output signal of the temperature detection circuit are provided.
【０００８】[0008]
【実施例】次に、本発明の最適な実施例について、図面
を参照して説明する。図１（ａ）は、本発明の第１の実
施例のブロック図である。図１（ａ）を参照すると、本
実施例は、チップ１の温度を検出してアラーム信号４を
出力する温度セン２と、源発クロック信号Ａおよび源発
クロック信号Ｂとを入力とし、上記の温度センサ２から
のアラーム信号４により、どちらかのクロック信号を選
択して内部回路６に出力するセレクタ回路３を備えてい
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an optimum embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a block diagram of the first embodiment of the present invention. Referring to FIG. 1A, in the present embodiment, a temperature sensor 2 that detects the temperature of the chip 1 and outputs an alarm signal 4, a source clock signal A and a source clock signal B are input, and A selector circuit 3 for selecting one of the clock signals by the alarm signal 4 from the temperature sensor 2 and outputting it to the internal circuit 6 is provided.
【０００９】以下に本実施例の動作を説明する。今、内
部回路６が周波数の高い源発クロック信号Ａで動作中に
チップ１の温度が上昇すると、温度センサ２がこの温度
変化を感知し、セレクタ回路３にアラーム信号４を送
る。セレクタ回路３は、このアラーム信号４が入力さ
れ、内部回路６へのクロック信号出力を、周波数の高い
源発クロックＡから周波数の低い源発クロックＢに切り
替える。このようにして、チップ１の発熱を抑制し、プ
ログラムの暴走を防ぐことができる。The operation of this embodiment will be described below. Now, when the temperature of the chip 1 rises while the internal circuit 6 is operating with the source clock signal A having a high frequency, the temperature sensor 2 senses this temperature change and sends the alarm signal 4 to the selector circuit 3. The alarm signal 4 is input to the selector circuit 3, and the clock signal output to the internal circuit 6 is switched from the high-frequency source clock A to the low-frequency source clock B. In this way, the heat generation of the chip 1 can be suppressed and the program runaway can be prevented.
【００１０】上記の第１の実施例では、周波数の異なる
２つの源発クロック信号Ａ，Ｂをセレクタ回路３で切り
替える構成について説明したが、図１（ｂ）に示す第２
の実施例のように、１つの源発クロック信号Ａを分周す
ることによっても、内部回路６へのクロック信号の周波
数を切り替えることができる。In the first embodiment described above, the configuration in which the two source clock signals A and B having different frequencies are switched by the selector circuit 3 has been described, but the second embodiment shown in FIG.
The frequency of the clock signal to the internal circuit 6 can be switched by dividing the frequency of one source clock signal A as in the embodiment of FIG.
【００１１】図１（ｂ）は、本発明の第２の実施例のブ
ロック図である。図１（ｂ）を参照すると、本実施例が
第１の実施例と異なるのは、セレクタ回路３の前に分周
回路５が設けられている点である。分周回路５には源発
クロック信号Ａが入力されている。このクロック信号Ａ
は分周され、周波数の低い２つのクロック信号Ｂ，Ｃが
発生される。セレクタ回路３は、温度センサ２からのア
ラーム信号４により、クロック信号Ｂとクロック信号Ｃ
とを切り替えて、内部回路６に出力する。尚、本実施例
においては、２つのクロック信号Ｂ，Ｃのうち周波数の
高い方のクロック信号は、その周波数が源発クロック信
号Ａの周波数と同じであってもよい。本実施例は、源発
クロック信号の数が第１の実施例よりも少ないにも関ら
ず、内部回路へのクロック信号の周波数をよりきめ細か
く替えることができるという利点を持っている。FIG. 1 (b) is a block diagram of the second embodiment of the present invention. Referring to FIG. 1B, the present embodiment is different from the first embodiment in that a frequency dividing circuit 5 is provided before the selector circuit 3. The source clock signal A is input to the frequency dividing circuit 5. This clock signal A
Is divided and two low-frequency clock signals B and C are generated. The selector circuit 3 receives a clock signal B and a clock signal C according to the alarm signal 4 from the temperature sensor 2.
And are switched to output to the internal circuit 6. In this embodiment, the higher frequency clock signal of the two clock signals B and C may have the same frequency as the frequency of the source clock signal A. This embodiment has the advantage that the frequency of the clock signal to the internal circuit can be changed more finely, although the number of source clock signals is smaller than that of the first embodiment.
【００１２】[0012]
【発明の効果】以上説明したように、本発明の半導体集
積回路は、チップの温度上昇を感知しアラーム信号を出
力する温度センサと、このアラーム信号によりクロック
信号を切り替えるセレクタ回路とを有している。このこ
とにより、本発明によれば、内部回路の動作タイミング
を制御するクロック信号の周波数をチップの温度上昇に
応じて低くしてチップの温度上昇を防ぎ、集積回路とし
ての動作を安定させることができる。更に、集積回路の
外装にセラミックパーケージより安価なプラスチックパ
ッケージを用いて、そのコストを低減することができ
る。As described above, the semiconductor integrated circuit of the present invention has a temperature sensor that senses a temperature rise of the chip and outputs an alarm signal, and a selector circuit that switches a clock signal by this alarm signal. There is. Thus, according to the present invention, the frequency of the clock signal for controlling the operation timing of the internal circuit is lowered according to the temperature rise of the chip to prevent the temperature rise of the chip and stabilize the operation as an integrated circuit. it can. Further, the cost can be reduced by using a plastic package, which is cheaper than a ceramic package, for the exterior of the integrated circuit.
【００１３】又、セレクタ回路の前段に分周回路を設
け、この分周回路への源発クロック信号を周波数の低い
クロック信号に分周してセレクタ回路へ入力することに
より、源発クロック信号の数が一つでも、内部回路への
クロック信号の周波数をよりきめ細かく制御することが
できる。Further, a frequency dividing circuit is provided in the preceding stage of the selector circuit, and the source clock signal to this frequency dividing circuit is divided into a clock signal having a low frequency and is input to the selector circuit. Even if the number is one, the frequency of the clock signal to the internal circuit can be controlled more finely.
【図面の簡単な説明】[Brief description of drawings]
【図１】分図（ａ）は、本発明の第１の実施例のブロッ
ク図である。分図（ｂ）は、本発明の第２の実施例のブ
ロック図である。FIG. 1A is a block diagram of a first embodiment of the present invention. Part (b) of the drawing is a block diagram of the second embodiment of the present invention.
１ チップ ２ 温度センサ ３ セレクタ回路 ４ アラーム信号 ５ 分周回路 ６ 内部回路 1 chip 2 temperature sensor 3 selector circuit 4 alarm signal 5 frequency divider circuit 6 internal circuit
Claims (2)
を出力する温度センサと、 この温度センサの出力信号により、クロック信号を切り
替えるセレクタ回路とを備えることを特徴とする半導体
集積回路。1. A semiconductor integrated circuit comprising: a temperature sensor that senses a temperature rise of a chip and outputs an alarm signal; and a selector circuit that switches a clock signal according to an output signal of the temperature sensor.
を出力する温度検出回路と、 源発クロック信号を入力して周波数の異なる複数のクロ
ック信号を出力する分周回路と、 前記温度検出回路の出力信号により、クロック信号を切
り替えるセレクタ回路とを備えることを特徴とする半導
体集積回路。2. A temperature detecting circuit for detecting an increase in temperature of a chip and outputting an alarm signal, a frequency dividing circuit for inputting a source clock signal and outputting a plurality of clock signals having different frequencies, and a temperature detecting circuit for the temperature detecting circuit. A semiconductor integrated circuit, comprising: a selector circuit that switches a clock signal according to an output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4031173A JPH05235138A (en) | 1992-02-19 | 1992-02-19 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4031173A JPH05235138A (en) | 1992-02-19 | 1992-02-19 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05235138A true JPH05235138A (en) | 1993-09-10 |
Family
ID=12324055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4031173A Withdrawn JPH05235138A (en) | 1992-02-19 | 1992-02-19 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05235138A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100337581B1 (en) * | 1997-01-17 | 2002-10-25 | 닛본 덴기 가부시끼가이샤 | Synchronous semiconductor memory device and semiconductor device |
| JP2016138799A (en) * | 2015-01-27 | 2016-08-04 | 株式会社ソシオネクスト | Semiconductor integrated circuit device and semiconductor integrated circuit device testing method |
-
1992
- 1992-02-19 JP JP4031173A patent/JPH05235138A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100337581B1 (en) * | 1997-01-17 | 2002-10-25 | 닛본 덴기 가부시끼가이샤 | Synchronous semiconductor memory device and semiconductor device |
| JP2016138799A (en) * | 2015-01-27 | 2016-08-04 | 株式会社ソシオネクスト | Semiconductor integrated circuit device and semiconductor integrated circuit device testing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7144152B2 (en) | Apparatus for thermal management of multiple core microprocessors | |
| KR100505645B1 (en) | Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information | |
| US6836437B2 (en) | Method of reducing standby current during power down mode | |
| KR910002135A (en) | Phase difference detection circuit | |
| JPH08249085A (en) | Microprocessor, clock control circuit for giving of timing signal to control internal clock frequency of microprocessor and method for control of frequency of internal clock signal to drive microprocessor | |
| US5278457A (en) | Method and apparatus for adjusting clock signal of electronic apparatus | |
| JP2000269417A (en) | Semiconductor device | |
| JPS63116512A (en) | Voltage control oscillator | |
| JPH05235138A (en) | Semiconductor integrated circuit | |
| JPH09102739A (en) | Pll circuit | |
| JPH05211432A (en) | Data output circuit and semiconductor integrated circuit | |
| US7961820B2 (en) | Programmable and pausable clock generation unit | |
| JPH06232703A (en) | Oscillator | |
| JP2000077999A (en) | Semiconductor integrated circuit | |
| JP2000243910A (en) | Semiconductor integrated circuit | |
| JPH103784A (en) | Semiconductor device | |
| KR20030058249A (en) | System clock frequency changing circuit for digital logic | |
| JPH10320071A (en) | Semiconductor integrated circuit | |
| JPH08321773A (en) | Semiconductor integrated circuit | |
| JP2001014057A (en) | Clock generator mounting temperature management function | |
| JPH04275610A (en) | Clock generating circuit | |
| JP2812100B2 (en) | Small computer system interface controller | |
| JPH10107627A (en) | Phase-locked loop circuit | |
| JPH08179849A (en) | Clock output circuit | |
| JPH075948A (en) | Computer system and its clock controlling method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990518 |