JPH0476056U - - Google Patents
Info
- Publication number
- JPH0476056U JPH0476056U JP12058290U JP12058290U JPH0476056U JP H0476056 U JPH0476056 U JP H0476056U JP 12058290 U JP12058290 U JP 12058290U JP 12058290 U JP12058290 U JP 12058290U JP H0476056 U JPH0476056 U JP H0476056U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor encapsulation
- encapsulation device
- semiconductor
- combination
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000005538 encapsulation Methods 0.000 claims description 7
- 238000007789 sealing Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図はこの考案の一実施例である半導体封止
装置の平面図、第２図は第１図の２ケの半導体封
止装置を組み合わせた場合の平面図、第３図は従
来の半導体封止装置の斜視図、第４図は第３図の
プリント基板裏面の配線パターンを示す平面図で
ある。
図において、１はＩＣ１、２，４はリード部、
３はＩＣ２、５はプリント基板を示す。なお、図
中、同一符号は同一、または相当部分を示す。
Fig. 1 is a plan view of a semiconductor encapsulation device which is an embodiment of this invention, Fig. 2 is a plan view of a combination of the two semiconductor encapsulation devices shown in Fig. 1, and Fig. 3 is a plan view of a conventional semiconductor encapsulation device. FIG. 4 is a perspective view of the sealing device and a plan view showing the wiring pattern on the back surface of the printed circuit board shown in FIG. 3. In the figure, 1 is IC1, 2 and 4 are lead parts,
3 represents an IC2, and 5 represents a printed circuit board. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
て、半導体封止装置の外部リード出力部の少なく
とも１辺に凸部または凹部を設け、少なくとも２
ケ以上の上記半導体封止装置を組み合わせたこと
を特徴とする半導体封止装置。 In a semiconductor encapsulation device for storing a semiconductor chip, a convex portion or a concave portion is provided on at least one side of an external lead output portion of the semiconductor encapsulation device, and at least two
A semiconductor encapsulation device comprising a combination of at least one of the semiconductor encapsulation devices described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12058290U JPH0476056U (en) | 1990-11-15 | 1990-11-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12058290U JPH0476056U (en) | 1990-11-15 | 1990-11-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0476056U true JPH0476056U (en) | 1992-07-02 |
Family
ID=31868481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12058290U Pending JPH0476056U (en) | 1990-11-15 | 1990-11-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0476056U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001099189A1 (en) * | 2000-06-19 | 2001-12-27 | Advantest Corporation | Method and apparatus for edge connection between elements of an integrated circuit |
| KR100502119B1 (en) * | 2000-06-19 | 2005-07-19 | 가부시키가이샤 어드밴티스트 | Contact structure and assembly mechanism thereof |
-
1990
- 1990-11-15 JP JP12058290U patent/JPH0476056U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001099189A1 (en) * | 2000-06-19 | 2001-12-27 | Advantest Corporation | Method and apparatus for edge connection between elements of an integrated circuit |
| KR100502119B1 (en) * | 2000-06-19 | 2005-07-19 | 가부시키가이샤 어드밴티스트 | Contact structure and assembly mechanism thereof |
| CN1305181C (en) * | 2000-06-19 | 2007-03-14 | 株式会社鼎新 | Connecting component and its assembling mechanism |