JPH04307943A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH04307943A
JPH04307943A JP3100366A JP10036691A JPH04307943A JP H04307943 A JPH04307943 A JP H04307943A JP 3100366 A JP3100366 A JP 3100366A JP 10036691 A JP10036691 A JP 10036691A JP H04307943 A JPH04307943 A JP H04307943A
Authority
JP
Japan
Prior art keywords
semiconductor chip
pad
pads
lead
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3100366A
Other languages
English (en)
Inventor
Katsunobu Hongo
本郷　勝信
Hideki Shibuya
澁谷　英樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3100366A priority Critical patent/JPH04307943A/ja
Publication of JPH04307943A publication Critical patent/JPH04307943A/ja
Priority to US08/178,344 priority patent/US5455460A/en
Pending legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、半導体装置に関し、特
にパッケージのフレームのリードと接続するためのリー
ドをつなぐパッドに関するものである。
【０００２】
【従来の技術】図５は、従来の半導体装置の一例を示す
図である。同図から明らかなように、ダイパッド１上に
配置された四角形の半導体チップ２上には、その四辺に
沿って複数のパッド３が配設されており、このパッド３
とその両側に配置された例えばＮチャネルＭＯＳトラン
ジスタ，ＰチャネルＭＯＳトランジスタより成るドライ
バ回路４，４とはプリントされた導体５によって接続さ
れている。また、上記ドライバ回路４の一方側には周辺
回路６が接続配置されている。
【０００３】一方、ダイパッド１の外側には銅合金等に
より作製されてパッケージの端子となるフレームのリー
ド７が配設されており、このフレームのリード７と上記
パッド３は、金線等により作製されたリード８により電
気的に接続された構成となっている。すなわち、１個の
端子に対応する半導体チップ２上のパッド３は１個で、
このパッド３は、パッケージの形・大きさと半導体チッ
プ２の大きさ、パッド３の配置を考慮して最適に作られ
たフレームのリード７とをつなぐリード８により電気的
に接続されている。
【０００４】
【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されていたので、１種類の半導体チップ
２で複数種のパッケージを使用する場合、例えばチップ
サイズが小さいとフレームのリード７を長くしかつこの
リード７の先端を細くして密に配置しなければならない
。しかしながら、この場合、フレームの板厚の関係でこ
のリード７の加工ができない場合がある等の理由により
、各フレームにより実現できるリード７先端の位置，形
状が制限される。このため、リード７の先端を半導体チ
ップ２に近づけるのに限界があり、しかもワイヤリング
長，角度にも制限があり、パッド３の配置に最適なフレ
ームのリード７を作製できず、特に半導体チップ２の角
部におけるボンディングができないという問題があった
。また、半導体チップ２上の全てのパッド３を使用せず
端子数を減少させてモールドするとき等においても同様
の問題が生じていた。
【０００５】本発明の目的は上記問題点を解決するため
になされたもので、１種類の半導体チップで複数種類の
パッケージを使用可能とした半導体装置を提供すること
にある。
【０００６】
【課題を解決するための手段】上記目的を達成するため
に、本発明は、半導体チップの角部の周辺におけるパッ
ドに、補助パッドを設け、パッドと補助パッドとを導体
で接続した構成としたものである。
【０００７】
【作用】本発明によれば、半導体チップの角部の周辺に
おいて、１つの端子に対応するパッドを複数個設けてい
るので、１種類の半導体チップで複数種類のパッケージ
に対応することができる。したがって、１種類のチップ
で複数種類のパッケージを用いる場合、特に半導体チッ
プの角部周辺において、各フレームにより実現できるリ
ード先端の位置，形状が制限されることによるパッドと
フレームのリードとのワイヤリング長，角度の制限を緩
和できる。
【０００８】
【実施例】以下、図に示す実施例を用いて本発明の詳細
を説明する。
【０００９】図１は本発明に係わる半導体装置の一実施
例を示す平面図、図２は図１のＡ−Ａ断面図、図３は同
半導体装置の要部拡大平面図である。各図において、ダ
イパッド１０上には半田１０Ａにより四角形の半導体チ
ップ１１が配置固定されており、該半導体チップ１１上
には半導体チップ１１の四辺に沿って複数のパッド１２
が配設されている。また、半導体チップ１１上には複数
の回路、本実施例にあっては内部回路１３，ドライバ回
路１４，１４及び内側のドライバ回路１４に接続された
周辺回路１５が形成されている。ドライバ回路１４，１
４は例えば、ＮチャネルＭＯＳトランジスタ，Ｐチャネ
ルＭＯＳトランジスタより成り、パッド１２の両側に配
置されている。ドライバ回路１４，１４とパッド１２は
導体１６を介して接続されている。１７は薄いフラット
状のパッケージに形成されて第１のパッケージの端子と
なるフレームのリードで、１８はリップタイプのパッケ
ージに形成されて第２のパッケージの端子となるフレー
ムのリードを表わす。これらリード１７，１８は半導体
チップ１１の外側から該半導体チップ１１の中央方向に
向けて延設されており、該リード１７，１８の先端は半
導体チップ１１の外周に対向した構成となっっている。 該リード１７，１８と上記パット１２とは全線等のリー
ド１９により接続されている。
【００１０】上記複数のパッド１２のうち、半導体チッ
プ１１の角部１１Ａ周辺におけるパッド１２Ａには、導
体２０により接続された補助パッド２１が配設されてい
る。この補助パッド２１は半導体チップ１１の角部１１
Ａ側に設けられている。なお、半導体チップ１１の中央
側のパッド１２には補助パッド２１は設けていない。
【００１１】また、パッド１２Ａと補助パッド２１の位
置は、それぞれ第１，第２のパッケージにより実現でき
るフレームの形状に合うように決定されている。さらに
、パッド１２Ａと補助パッド２１を接続する導体２０は
、半導体チップ１１上に長く取れないので、パッド径の
数倍の範囲内に配置されるものとする。なお、図１にお
いて符号２２はグランド線、２３は電源線を示す。
【００１２】このように本実施例構成によれば、半導体
チップ１１の角部１１Ａ周辺に１つの端子に対応する複
数のパッド（パッド１２，補助パッド２１）を設けたの
で、１種類の半導体チップ１１で複数種類のパッケージ
に対応することができる。すなわち、様々に形成された
複数種類のフレームのリード１７，１８によって、接続
するパッド１２，補助パッド２１を任意に選んでボンデ
ィングできる。したがって、特に制限がきつかった半導
体チップ１１の角部１１Ａの制限を緩和できる。
【００１３】また、パッド１２と電気的に接続されてい
る補助パッド２１との間隔は、パッド径の数倍の範囲内
に配置されることにより、パッド１２と補助パッド２１
を用いたとき、この半導体装置の電気的特性が変わる等
の不具合が起きることを防止することができる。
【００１４】図４は本発明に係わる半導体装置の他の実
施例を示すもので、パッド１２Ａと補助パッド２１の位
置をパッケージの種類によって最も適当な配置構成とな
るように変化させたものである。また、その他の構成、
例えばダイパッド１０，半導体チップ１１，ドライバ回
路１４，周辺回路１５，第１，第２のパッケージのフレ
ームのリード１７，１８，リード１９等は上述した第１
実施例と同じであるので、その説明は省略する。
【００１５】なお、上述した実施例では１つの端子に対
応するパッドは２個であったが、別に２個に限定される
ものではなく複数個なら何個でもよいことは言うまでも
ない。
【００１６】
【発明の効果】以上説明したように本発明によれば、半
導体チップの角部の周辺におけるパッドに、補助パッド
を設け、パッドと補助パッドとを導体で接続した構成と
したことにより、１種類の半導体チップで複数種類のパ
ッケージに対応することができるという優れた効果を奏
する。
【図面の簡単な説明】
【図１】本発明に係わる半導体装置の一実施例を示す平
面図である。
【図２】図１のＡ−Ａ断面図である。
【図３】同半導体装置の要部拡大平面図である。
【図４】本発明に係わる半導体装置の他の実施例を示す
要部拡大平面図である。
【図５】従来の半導体装置の一例を示す一部拡大平面図
である。
【符号の説明】
１０　　ダイパッド １１　　半導体チップ １１Ａ　　角部 １２　　パッド １２Ａ　　パッド １７　　リード １８　　リード １９　　リード ２０　　導体 ２１　　補助パッド

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】　　ダイパッド上に配置された四角形の半
    導体チップと、この半導体チップ上に形成された複数の
    各回路に接続されて半導体チップの四辺に沿って配設さ
    れるパッドと、外側から上記半導体チップの中央方向に
    向けて延長され、かつ先端が半導体チップの外周に対向
    するリードと、上記パッドとリードとを接続する金線等
    のリードとより成る半導体装置において、上記半導体チ
    ップの角部の周辺における上記パッドに、補助パッドを
    設け、上記パッドと補助パッドとを導体で接続したこと
    を特徴とする半導体装置。
JP3100366A 1991-04-05 1991-04-05 半導体装置 Pending JPH04307943A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3100366A JPH04307943A (ja) 1991-04-05 1991-04-05 半導体装置
US08/178,344 US5455460A (en) 1991-04-05 1994-01-06 Semiconductor device having complimentary bonding pads

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3100366A JPH04307943A (ja) 1991-04-05 1991-04-05 半導体装置

Publications (1)

Publication Number Publication Date
JPH04307943A true JPH04307943A (ja) 1992-10-30

Family

ID=14272065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3100366A Pending JPH04307943A (ja) 1991-04-05 1991-04-05 半導体装置

Country Status (2)

Country Link
US (1) US5455460A (ja)
JP (1) JPH04307943A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504373A (en) * 1993-05-14 1996-04-02 Samsung Electronics Co., Ltd. Semiconductor memory module
CN112864121A (zh) * 2021-01-14 2021-05-28 长鑫存储技术有限公司 芯片结构、封装结构及其制作方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751015A (en) 1995-11-17 1998-05-12 Micron Technology, Inc. Semiconductor reliability test chip
US5675178A (en) * 1995-11-22 1997-10-07 Cypress Semiconductor Corp. No-bond integrated circuit inputs
US5814892A (en) * 1996-06-07 1998-09-29 Lsi Logic Corporation Semiconductor die with staggered bond pads
JP3565991B2 (ja) * 1996-06-26 2004-09-15 株式会社ルネサステクノロジ 半導体集積回路および半導体集積回路の製造方法
JPH1092857A (ja) * 1996-09-10 1998-04-10 Mitsubishi Electric Corp 半導体パッケージ
US6097098A (en) 1997-02-14 2000-08-01 Micron Technology, Inc. Die interconnections using intermediate connection elements secured to the die face
FR2769131B1 (fr) * 1997-09-29 1999-12-24 St Microelectronics Sa Dispositif semi-conducteur a deux plots de connexion de masse relies a une patte de connexion de masse et procede pour tester un tel dispositif
US6351040B1 (en) * 1998-01-22 2002-02-26 Micron Technology, Inc. Method and apparatus for implementing selected functionality on an integrated circuit device
JP2000021939A (ja) * 1998-06-29 2000-01-21 Mitsubishi Electric Corp 突起電極付半導体チップおよびその検査方法
US6373143B1 (en) 1998-09-24 2002-04-16 International Business Machines Corporation Integrated circuit having wirebond pads suitable for probing
JP2000223657A (ja) * 1999-02-03 2000-08-11 Rohm Co Ltd 半導体装置およびそれに用いる半導体チップ
JP3388202B2 (ja) * 1999-05-26 2003-03-17 ローム株式会社 半導体集積回路装置ならびに装置の組立方法
US6246107B1 (en) 1999-07-07 2001-06-12 Philips Semiconductors, Inc. Semiconductor device arrangement having configuration via adjacent bond pad coding
US6426284B1 (en) 2000-03-20 2002-07-30 Illinois Tool Works Inc. Method of manufacturing wire bond pad
US6858945B2 (en) * 2002-08-21 2005-02-22 Broadcom Corporation Multi-concentric pad arrangements for integrated circuit pads
US7071561B2 (en) * 2004-06-08 2006-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture thereof with two or more bond pad connections for each input/output cell
JP5656644B2 (ja) * 2008-12-19 2015-01-21 株式会社アドバンテスト 半導体装置、半導体装置の製造方法およびスイッチ回路
US10262926B2 (en) 2016-10-05 2019-04-16 Nexperia B.V. Reversible semiconductor die

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364333A (ja) * 1986-09-04 1988-03-22 Toshiba Corp 半導体装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS575887Y2 (ja) * 1976-08-23 1982-02-03
JPS5444881A (en) * 1977-09-16 1979-04-09 Nec Corp Electrode wiring structure of integrated circuit
US4951098A (en) * 1988-12-21 1990-08-21 Eastman Kodak Company Electrode structure for light emitting diode array chip

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364333A (ja) * 1986-09-04 1988-03-22 Toshiba Corp 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504373A (en) * 1993-05-14 1996-04-02 Samsung Electronics Co., Ltd. Semiconductor memory module
CN112864121A (zh) * 2021-01-14 2021-05-28 长鑫存储技术有限公司 芯片结构、封装结构及其制作方法

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