JPH04286163A - Manufacture of semiconductor substrate - Google Patents
Manufacture of semiconductor substrateInfo
- Publication number
- JPH04286163A JPH04286163A JP7473291A JP7473291A JPH04286163A JP H04286163 A JPH04286163 A JP H04286163A JP 7473291 A JP7473291 A JP 7473291A JP 7473291 A JP7473291 A JP 7473291A JP H04286163 A JPH04286163 A JP H04286163A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- resistivity
- semiconductor substrate
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 75
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 49
- 239000010703 silicon Substances 0.000 claims abstract description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 27
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 19
- 239000011574 phosphorus Substances 0.000 claims abstract description 19
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 7
- 238000005498 polishing Methods 0.000 claims abstract description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 8
- 238000001947 vapour-phase growth Methods 0.000 claims description 8
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 9
- 230000000087 stabilizing effect Effects 0.000 abstract 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 12
- 239000007789 gas Substances 0.000 description 8
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 6
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 6
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 4
- 239000005052 trichlorosilane Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、半導体基板の製造方法
に関し、より詳しくは、インバータ、小型電力変換装置
等に使用されるＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａ
ｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）用
に適した半導体基板の製造方法に関する。[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly, to a method for manufacturing a semiconductor substrate, and more particularly, to a method for manufacturing a semiconductor substrate, and more particularly, the present invention relates to a method for manufacturing a semiconductor substrate.
The present invention relates to a method for manufacturing a semiconductor substrate suitable for a Bipolar Transistor.
【０００２】0002
【従来の技術】ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａ
ｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）は
、パワーＭＯＳＦＥＴの高速スイッチング特性及びバイ
ポーラトランジスタの高電力特性を備え、パワー半導体
素子として、例えば、インバータ及び小型電力変換装置
等に使用されている。[Prior art] IGBT (Insulated Ga
The Bipolar Transistor has the high-speed switching characteristics of a power MOSFET and the high power characteristics of a bipolar transistor, and is used as a power semiconductor element in, for example, inverters and small power conversion devices.
【０００３】ＩＧＢＴの基本構造を図５に示す。その動
作原理は次の通りである。FIG. 5 shows the basic structure of an IGBT. Its operating principle is as follows.
【０００４】ゲートに正の電圧を印加するとゲート電極
５の下のｐベース層７の表面にｎチャネルが形成されｎ
− 層８に電子が流入する。その結果、ｐ＋ ドレイン
層１０からｎ− 層８に正孔の注入が起こり、オン抵抗
は低下する。When a positive voltage is applied to the gate, an n channel is formed on the surface of the p base layer 7 under the gate electrode 5.
- electrons flow into layer 8; As a result, holes are injected from the p+ drain layer 10 into the n- layer 8, and the on-resistance decreases.
【０００５】このように、ＩＧＢＴは低オン特性のすぐ
れたＭＯＳ入力形自己ターンオフ素子であるが、ＩＧＢ
Ｔ実用化のポイントはオン抵抗を下げるために導入した
正孔を速やかに消滅させ高速動作をさせることにある。As described above, the IGBT is a MOS input type self-turn-off device with excellent low on-state characteristics.
The key to putting T into practical use is to quickly eliminate the holes introduced to lower the on-resistance, thereby enabling high-speed operation.
【０００６】この高速動作を実現させる手法としてｎ＋
バッファ層９の不純物濃度の精密コントロール技術に
よる正孔注入量の最適化が重要視されるようになってき
た。[0006] As a method for realizing this high-speed operation, n+
Optimization of the amount of holes injected through precise control technology of the impurity concentration of the buffer layer 9 has become important.
【０００７】ＩＧＢＴ用半導体基板は、従来、図６（ａ
）〜（ｃ）に示すようにｐ＋ シリコン基板１１（例え
ばボロン濃度３．７８×１０１８原子／ｃｍ３ ）の裏
面からのボロンの気化を防止するために、該基板の裏面
をＣＶＤ酸化膜１２で保護した後、ｎ＋ バッファ層１
３（例えばリン濃度７．８４×１０１６原子／ｃｍ３
）をエピタキシャル成長させ、次いでその上に低濃度の
ｎ− 層１４（例えばリン濃度４．５×１０１３原子／
ｃｍ３ ）をエピタキシャル成長させて作製されている
。Conventionally, a semiconductor substrate for IGBT is shown in FIG.
) to (c), in order to prevent boron from vaporizing from the back side of a p+ silicon substrate 11 (for example, boron concentration 3.78 x 1018 atoms/cm3), the back side of the substrate is protected with a CVD oxide film 12. After that, n+ buffer layer 1
3 (for example, phosphorus concentration 7.84 x 1016 atoms/cm3
) is epitaxially grown, and then a low concentration n- layer 14 (for example, a phosphorus concentration of 4.5 x 1013 atoms/
cm3) is produced by epitaxial growth.
【０００８】[0008]
【発明が解決しようとする課題】ところが前述の方法で
は、■ｐ＋ シリコン基板に、より低濃度で反対導電型
のｎ＋ バッファ層やｎ− 層をエピタキシャル成長法
により形成させているので、エピタキシャル成長開始時
にｐ＋ シリコン基板の表面からドーパントであるボロ
ンが気化し、この気化したボロンが気相からｎ＋ バッ
ファ層やｎ− 層に混入する、所謂オートドープが発生
するため、ｎ＋ バッファ層やｎ− 層の不純物濃度を
精密にコントロールすることができず、その結果、ｎ＋
バッファ層やｎ− 層の抵抗率が変動し、また時には
ｎ− 層が反対導電型のｐ型に反転することもあり得る
ので、良好な電気特性を有する半導体装置の製造が困難
となる。この他ＩＧＢＴ用半導体基板としては、ｎ＋
シリコン基板上にｐ＋ バッファー層をエピタキシャル
成長させるｐ− ／ｐ＋ ／ｎ＋ 型も考えられるが、
この場合にも上記の場合すなわち、ｎ− ／ｎ＋ ／ｐ
＋ 型の場合と同様に、ｎ＋ シリコン基板からのオー
トドーピング現象により、ｐ＋ ，ｐ− 層の不純物濃
度を精密にコントロールできないという問題を生ずる。However, in the above-mentioned method, ■ an n+ buffer layer or an n- layer of the opposite conductivity type with a lower concentration is formed on a p+ silicon substrate by epitaxial growth. Boron, which is a dopant, vaporizes from the surface of the silicon substrate, and this vaporized boron mixes into the n+ buffer layer and n- layer from the vapor phase, resulting in so-called autodoping, which reduces the impurity concentration of the n+ buffer layer and n- layer. cannot be precisely controlled, and as a result, n+
Since the resistivity of the buffer layer and the n- layer fluctuates, and sometimes the n- layer may be inverted to the opposite conductivity type, the p-type, it becomes difficult to manufacture a semiconductor device with good electrical characteristics. In addition, as a semiconductor substrate for IGBT, n+
A p-/p+/n+ type, in which a p+ buffer layer is epitaxially grown on a silicon substrate, is also considered.
In this case also the above case, that is, n- /n+ /p
As in the + type case, the autodoping phenomenon from the n+ silicon substrate causes the problem that the impurity concentrations of the p+ and p- layers cannot be precisely controlled.
【０００９】また、■ｐ＋ シリコン基板１１上にｎ＋
層やｎ− 層をエピタキシャル成長させる時、基板周
縁及び側端面のシリコン酸化膜１７上にはノジュールと
称する多結晶の突起状異常成長が起こり、基板取り扱い
時にしばしばノジュールが破損分離し、エピタキシャル
成長層を傷付ける。[0009] Also, n+ on the p+ silicon substrate 11
When a layer or an n- layer is grown epitaxially, abnormal growth of protruding polycrystals called nodules occurs on the silicon oxide film 17 at the periphery and side edges of the substrate, and when the substrate is handled, the nodules are often broken and separated, damaging the epitaxially grown layer. .
【００１０】更に、■高品質のエピタキシャル成長層を
必要とするため成長速度が遅くなる等の欠点があった。Furthermore, (1) it requires a high-quality epitaxial growth layer, resulting in a slow growth rate.
【００１１】本発明は上記の点を解決しようとするもの
で、その目的は、ノジュールの発生がなく、かつ各層の
不純物濃度を精密コントロールすることにより抵抗率を
安定化し、さらに成長速度が速くかつ容易に製造できる
半導体基板の製造方法を提供することにある。The present invention aims to solve the above-mentioned problems, and its purpose is to eliminate the generation of nodules, stabilize the resistivity by precisely controlling the impurity concentration of each layer, and further increase the growth rate. An object of the present invention is to provide a method for manufacturing a semiconductor substrate that can be easily manufactured.
【００１２】0012
【課題を解決するための手段】本発明の半導体基板の製
造方法は、抵抗率が３０Ωｃｍ以上の単結晶シリコン基
板の一主表面上に拡散法または気相成長法によって、該
単結晶シリコン基板と同じ導電型を有し、抵抗率が０．
０５〜０．５Ωｃｍである単結晶の第１シリコン層を形
成する工程と、次いで該第１シリコン層と逆の導電型を
有し、抵抗率が第１シリコン層より低く、かつその値が
０．１Ωｃｍ以下の第２シリコン層を形成する工程と、
該単結晶シリコン基板を他方の主表面から所定の厚さま
で研削及び／または研磨加工する工程とを有することを
特徴とする。さらに、本発明は、上記の半導体基板の製
造方法の範疇に含まれ、ｎ− ／ｎ＋ ／ｐ＋ の層構
成を有する半導体基板の製造方法を提供するものであり
、その製造方法は、リン濃度１０１４ｃｍ−３以下のｎ
型単結晶シリコン基板の一主表面上に拡散法または気相
成長法によって、リン濃度１０１６〜１０１８ｃｍ−３
のｎ型単結晶の第１シリコン層を形成する工程と、次い
で該第１シリコン層上に気相成長法にてホウ素濃度が１
０１８ｃｍ−３以上のｐ型の単結晶の第２シリコン層を
形成する工程と、該単結晶シリコン基板を他方の主表面
から所定の厚さまで研削、研磨加工する工程とを有する
ことを特徴としている。[Means for Solving the Problems] The method for manufacturing a semiconductor substrate of the present invention involves forming a single crystal silicon substrate on one main surface of a single crystal silicon substrate having a resistivity of 30 Ωcm or more by a diffusion method or a vapor phase growth method. They have the same conductivity type and a resistivity of 0.
forming a single crystal first silicon layer having a conductivity type of 0.05 to 0.5 Ωcm, and then forming a single crystal first silicon layer having a conductivity type opposite to that of the first silicon layer, having a resistivity lower than that of the first silicon layer, and having a value of 0; .1 Ωcm or less of a second silicon layer;
The method is characterized by comprising a step of grinding and/or polishing the single crystal silicon substrate from the other main surface to a predetermined thickness. Furthermore, the present invention is included in the scope of the above-mentioned method for manufacturing a semiconductor substrate, and provides a method for manufacturing a semiconductor substrate having a layer structure of n-/n+/p+. -n less than or equal to 3
A phosphorus concentration of 1016 to 1018 cm-3 is deposited on one main surface of a type single-crystal silicon substrate by a diffusion method or a vapor phase growth method.
forming a first silicon layer of n-type single crystal, and then forming a boron concentration of 1 on the first silicon layer by vapor phase epitaxy.
The present invention is characterized by comprising a step of forming a p-type single crystal second silicon layer of 0.018 cm -3 or more, and a step of grinding and polishing the single crystal silicon substrate from the other main surface to a predetermined thickness. .
【００１３】次に本発明を、図１に示すようなｎ− シ
リコン基板上にバッファ層としてｎ＋ 層を形成し、最
後にｐ＋ 層を積層した構造のＩＧＢＴ用半導体基板１
を製造する場合を例にとり、詳細に説明する。なお、ｐ
− ／ｐ＋ ／ｎ＋ 型の場合も以下の説明と略同様に
して製造することでできることはいうまでもない。Next, the present invention is applied to a semiconductor substrate 1 for IGBT having a structure in which an n+ layer is formed as a buffer layer on an n- silicon substrate, and a p+ layer is finally laminated on the n- silicon substrate as shown in FIG.
This will be explained in detail by taking the case of manufacturing as an example. In addition, p
It goes without saying that the −/p+/n+ type can also be manufactured by substantially the same method as described below.
【００１４】本発明の半導体基板の製造工程を図２（ａ
）〜（ｄ）に示す。まず、厚さ４００〜７５０μｍ、直
径１００〜１５０ｍｍ、リン濃度１０１４ｃｍ−３以下
（抵抗率５０Ωｃｍ以上）の公知の方法にて鏡面にされ
たｎ− 単結晶シリコン基板２（図２（ａ））の一主表
面上に拡散法または気相成長法にてバッファ層である厚
さ３〜２０μｍで、リン濃度１０１６〜１０１８ｃｍ−
３（抵抗率０．０２５〜０．６Ωｃｍ）のｎ＋ 層３を
形成させる（図２（ｂ））。このとき、気相成長法にお
いては、単結晶シリコン層となるようにｎ＋ 層３をエ
ピタキシャル成長させる。The manufacturing process of the semiconductor substrate of the present invention is shown in FIG. 2(a).
) to (d). First, an n- single-crystal silicon substrate 2 (FIG. 2(a)) with a thickness of 400 to 750 μm, a diameter of 100 to 150 mm, and a phosphorus concentration of 10 cm or less (resistivity of 50 Ω cm or more) is mirror-finished by a known method. A buffer layer with a thickness of 3 to 20 μm is formed on one main surface by diffusion method or vapor phase growth method, with a phosphorus concentration of 1016 to 1018 cm-
3 (resistivity: 0.025 to 0.6 Ωcm) (FIG. 2(b)). At this time, in the vapor phase growth method, the n+ layer 3 is epitaxially grown to become a single crystal silicon layer.
【００１５】ｎ＋ 層３のリン濃度はｎ− 単結晶シリ
コン基板２のリン濃度よりも相当高いので、ｎ＋ 層３
を気相成長法で形成する際、従来法で問題となっている
オートドープの影響が全くなく、ｎ＋ 層３のリン濃度
を精密にコントロールすることができる。Since the phosphorus concentration of the n+ layer 3 is considerably higher than that of the n- single crystal silicon substrate 2, the n+ layer 3
When forming the n+ layer 3 by vapor phase growth, there is no effect of autodoping, which is a problem in conventional methods, and the phosphorus concentration in the n+ layer 3 can be precisely controlled.
【００１６】次に、ｎ＋ 層３上に気相成長法にて厚さ
１００〜４００μｍ、ホウ素濃度１０１８ｃｍ−３以上
（抵抗率０．０２５Ωｃｍ以下）のｐ＋ シリコン層４
を形成する（図２（ｃ））。ｐ＋ シリコン層４は、高
品質を要求されないため、単結晶となる範囲でできるだ
け高速成長させることができる。またｎ＋ 層３のリン
濃度はｐ＋ シリコン層４のホウ素濃度よりも低いため
、ｐ＋シリコン層４の堆積開始時、ｎ＋ 層３の表面か
ら気化したリンによるオードトープの影響は無視できる
。Next, a p+ silicon layer 4 with a thickness of 100 to 400 μm and a boron concentration of 1018 cm-3 or more (resistivity of 0.025 Ωcm or less) is formed on the n+ layer 3 by vapor phase growth.
(Fig. 2(c)). Since the p+ silicon layer 4 is not required to have high quality, it can be grown as fast as possible as long as it becomes a single crystal. Furthermore, since the phosphorus concentration in the n+ layer 3 is lower than the boron concentration in the p+ silicon layer 4, the influence of odetopes caused by phosphorus vaporized from the surface of the n+ layer 3 can be ignored when the p+ silicon layer 4 starts to be deposited.
【００１７】また、本発明においては、ｎ− 単結晶シ
リコン基板２の裏面および側面に酸化膜を設けなくても
裏面からのオートドープの心配がないため、従来の方法
に比べて工程数が短く、またポリシリコンの異常成長に
より生じるノジュールの発生がない。さらにｎ＋ 層３
を拡散法にて形成すれば、従来よりもクラウンの発生を
抑えることができる。Furthermore, in the present invention, there is no need to provide an oxide film on the back and side surfaces of the n- single crystal silicon substrate 2, and there is no fear of autodoping from the back surface, so the number of steps is shorter than in the conventional method. Also, no nodules are generated due to abnormal growth of polysilicon. Further n+ layer 3
If it is formed by a diffusion method, it is possible to suppress the occurrence of a crown compared to the conventional method.
【００１８】最後に図２（ｃ）で得られた基板をｐ＋
シリコン層４を表面が平滑になるまで研磨した後、ｎ−
単結晶シリコン基板２を厚さが５０〜２５０μｍにな
るまで通常の研削、研磨方法により加工することにより
ＩＧＢＴ用半導体基板１を得ることができる。Finally, the substrate obtained in FIG. 2(c) is p+
After polishing the silicon layer 4 until the surface becomes smooth, n-
The semiconductor substrate 1 for IGBT can be obtained by processing the single crystal silicon substrate 2 by a normal grinding and polishing method until the thickness becomes 50 to 250 μm.
【００１９】[0019]
【実施例】次に本発明を実施例及び比較例を挙げて説明
する。
実施例
基板ウェーハとして、ＦＺ法で作成された面方位（１０
０）、リン濃度４．０×１０１３ｃｍ−３，抵抗率１３
０Ωｃｍ、直径１２５ｍｍ，初期厚さ６２５μｍのｎ型
のシリコン基板を用い、縦型エピリアクターのサセプタ
上に並べた。水素雰囲気中で前記シリコン基板を１１５
０℃まで加熱し、その後トリクロロシラン５リットル／
ｍｉｎ、Ｈ２ ８０リットル／ｍｉｎに加えて、水素希
釈のホスフィンガス０．２リットル／ｍｉｎを供給し、
２．０±０．１μｍ／ｍｉｎの成長速度で５分間堆積さ
せて層厚１０±１μｍのｎ＋ バッファ層を形成した。
ホスフィンガスの添加量は、堆積されるシリコン層のリ
ン濃度が８．７×１０１６ｃｍ−３、抵抗率が０．１０
±０．０１Ωｃｍになるように調整した。[Examples] Next, the present invention will be explained with reference to Examples and Comparative Examples. As an example substrate wafer, the surface orientation (10
0), phosphorus concentration 4.0 x 1013 cm-3, resistivity 13
N-type silicon substrates with a diameter of 0 Ωcm, a diameter of 125 mm, and an initial thickness of 625 μm were used and arranged on a susceptor of a vertical epireactor. The silicon substrate was heated at 115 in a hydrogen atmosphere.
Heat to 0°C, then add 5 liters of trichlorosilane/
In addition to H2 80 liters/min, supplying hydrogen-diluted phosphine gas 0.2 liters/min,
Deposition was performed for 5 minutes at a growth rate of 2.0±0.1 μm/min to form an n+ buffer layer with a layer thickness of 10±1 μm. The amount of phosphine gas added is such that the phosphorus concentration of the deposited silicon layer is 8.7 x 1016 cm-3 and the resistivity is 0.10.
It was adjusted to be ±0.01Ωcm.
【００２０】ｎ＋ バッファ層を形成した後、基板の温
度を１１５０℃に保ったまま、水素雰囲気中で１０分間
保持した後、トリクロロシラン１０リットル／ｍｉｎ，
Ｈ２ ８０リットル／ｍｉｎに加えて水素希釈のジボラ
ンガス０．５リットル／ｍｉｎを供給し、４．０±０．
２μｍ／ｍｉｎの成長速度で５２分間堆積させて層厚２
１０±１０μｍのｐ＋ 層を形成した。ジボランガスの
添加量は、堆積されるシリコン層のホウ素濃度が２．２
×１０１９ｃｍ−３、抵抗率が０．００５±０．００１
Ωｃｍになるように調整した。After forming the n+ buffer layer, the temperature of the substrate was kept at 1150° C. and held in a hydrogen atmosphere for 10 minutes, and then trichlorosilane was added at 10 liters/min.
In addition to 80 liters/min of H2, 0.5 liters/min of diborane gas diluted with hydrogen was supplied, and the temperature was 4.0±0.
Deposited for 52 minutes at a growth rate of 2 μm/min to obtain a layer thickness of 2
A p+ layer of 10±10 μm was formed. The amount of diborane gas added is such that the boron concentration of the deposited silicon layer is 2.2.
×1019cm-3, resistivity 0.005±0.001
Adjusted to Ωcm.
【００２１】縦型エピリアクターから取り出した後、ｐ
＋ 層の表面を１０μｍ研磨し、平滑にした後、ｎ型の
シリコン基板を厚さ１９０μｍまで研削、研磨すること
により全体の厚さが４１０μｍのＩＧＢＴ用半導体基板
を得た。得られた半導体基板の各層の厚さと濃度の関係
をＳＲ法で測定した。その結果を図３に示す。After being removed from the vertical epireactor, p
After the surface of the + layer was polished by 10 μm to make it smooth, the n-type silicon substrate was ground and polished to a thickness of 190 μm to obtain a semiconductor substrate for IGBT having a total thickness of 410 μm. The relationship between the thickness and concentration of each layer of the obtained semiconductor substrate was measured by the SR method. The results are shown in FIG.
【００２２】図３よりオートドープの発生がなく、リン
やホウ素の不純物濃度が一定で、各層の抵抗率が安定し
ていることがわかる。It can be seen from FIG. 3 that no autodoping occurs, the impurity concentrations of phosphorus and boron are constant, and the resistivity of each layer is stable.
【００２３】比較例
基板ウェーハとして、ＣＺ法で作成された面方位（１０
０）、ホウ素濃度２．０×１０１９ｃｍ−３、抵抗率０
．００５Ωｃｍ、直径１２５ｍｍ、初期厚さ５５０μｍ
のｐ型のシリコン基板の裏面にＣＶＤシリコン酸化膜１
μｍを堆積させた基板を用い、縦型エピリアクターのサ
セプタ上に並べた。水素雰囲気中で前記シリコン基板を
１１３０℃まで加熱し、その後トリクロロシラン３リッ
トル／ｍｉｎ、Ｈ２ ８０リットル／ｍｉｎに加えて、
水素希釈のホスフィンガス０．２リットル／ｍｉｎを供
給し、１．０±０．０１μｍ／ｍｉｎの成長速度で１０
分間堆積させて層厚１０±１μｍのｎ＋ バッファ層を
形成した。ホスフィンガスの添加量は、堆積されるシリ
コン層のリン濃度が８．７×１０１６ｃｍ−３、抵抗率
が０．１０±０．０１Ωｃｍになるように調整した。As a comparative example substrate wafer, a surface orientation (10
0), boron concentration 2.0 x 1019 cm-3, resistivity 0
．． 005Ωcm, diameter 125mm, initial thickness 550μm
CVD silicon oxide film 1 on the back side of the p-type silicon substrate.
A substrate on which micrometers were deposited was used and arranged on a susceptor of a vertical epireactor. The silicon substrate was heated to 1130° C. in a hydrogen atmosphere, and then trichlorosilane was added at 3 liters/min and H2 at 80 liters/min.
Supply 0.2 liters/min of phosphine gas diluted with hydrogen, and grow at a growth rate of 1.0 ± 0.01 μm/min for 10
An n+ buffer layer with a layer thickness of 10±1 μm was formed by depositing for 1 minute. The amount of phosphine gas added was adjusted so that the phosphorus concentration of the deposited silicon layer was 8.7×10 16 cm −3 and the resistivity was 0.10±0.01 Ωcm.
【００２４】第１のｎ＋ バッファ層を形成した後、基
板の温度を１１３０℃に保ったまま水素雰囲気中で１０
分間保持した後、トリクロロシラン３リットル／ｍｉｎ
、Ｈ２ ８０リットル／ｍｉｎに加えて水素希釈のホス
フィンガス０．０１リットル／ｍｉｎを供給し、１．０
±０．０１μｍ／ｍｉｎの成長速度で１１０分間堆積さ
せて層厚１１０±１０μｍの第２のｎ型シリコン層を形
成した。ホスフィンガスの添加量は、堆積されるシリコ
ン層のリン濃度が５．２×１０１３ｃｍ−３、抵抗率が
１００±１０Ωｃｍになるように調整した。得られたＩ
ＧＢＴ用半導体基板の各層の厚さと正味の濃度の関係を
ＳＲ法で測定した。その結果を図４に示す。After forming the first n+ buffer layer, the substrate was heated for 10 minutes in a hydrogen atmosphere while keeping the temperature of the substrate at 1130°C.
After holding for a minute, trichlorosilane 3 liters/min
, 80 liters/min of H2 and 0.01 liter/min of phosphine gas diluted with hydrogen were supplied,
The second n-type silicon layer was deposited for 110 minutes at a growth rate of ±0.01 μm/min to form a second n-type silicon layer with a layer thickness of 110±10 μm. The amount of phosphine gas added was adjusted so that the deposited silicon layer had a phosphorus concentration of 5.2×10 13 cm −3 and a resistivity of 100±10 Ωcm. Obtained I
The relationship between the thickness of each layer of the GBT semiconductor substrate and the net concentration was measured using the SR method. The results are shown in FIG.
【００２５】図４より、エピタキシャル成長開始時にお
けるｐ型シリコン基板表面からのボロンのオードトープ
の影響が観測され、ｎ＋ 層およびｎ− 層中の正味の
リン濃度が安定せずその結果、両層の抵抗率が変動した
。From FIG. 4, it is observed that the influence of boron odetopes from the surface of the p-type silicon substrate at the start of epitaxial growth is observed, and the net phosphorus concentration in the n+ and n- layers is not stabilized, resulting in a decrease in the resistance of both layers. The rate fluctuated.
【発明の効果】以上の説明で明らかなように，本発明の
半導体基板の製造方法によれば、各層の不純物濃度を精
密にコントロールすることができるので抵抗率を安定さ
せることができ、かつノジュールやクラウンの発生を防
止でき、容易にかつ生産性良好に、殊にＩＧＢＴの用途
に適した半導体基板を製造することが可能となる。[Effects of the Invention] As is clear from the above explanation, according to the method of manufacturing a semiconductor substrate of the present invention, it is possible to precisely control the impurity concentration of each layer, so that the resistivity can be stabilized, and the nodule It is possible to prevent the occurrence of crowns and crowns, and to manufacture a semiconductor substrate particularly suitable for IGBT applications easily and with good productivity.
【図１】本発明の半導体基板の断面図である。FIG. 1 is a cross-sectional view of a semiconductor substrate of the present invention.
【図２】本発明の半導体基板の製造工程を示す断面図で
ある。FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor substrate of the present invention.
【図３】実施例で得られたＩＧＢＴ用半導体基板の不純
物濃度プロファイルを示すグラフである。FIG. 3 is a graph showing an impurity concentration profile of an IGBT semiconductor substrate obtained in an example.
【図４】比較例で得られたＩＧＢＴ用半導体基板の不純
物濃度プロファイルを示すグラフである。FIG. 4 is a graph showing an impurity concentration profile of an IGBT semiconductor substrate obtained in a comparative example.
【図５】ＩＧＢＴの基本構造の断面図である。FIG. 5 is a cross-sectional view of the basic structure of an IGBT.
【図６】従来のＩＧＢＴ用半導体基板の製造工程を示す
断面図である。FIG. 6 is a cross-sectional view showing the manufacturing process of a conventional semiconductor substrate for IGBT.
１ ＩＧＢＴ用半導体基板
２ ｎ− シリコン基板
３ ｎ＋ バッファ層（第１シリコン層）４ ｐ＋
シリコン層（第２シリコン層）５ ゲート電極
６ ソース電極
７ ｐベース層
８ ｎ− シリコン層
９ ｎ＋ バッファ層
１０ ｐ＋ ドレイン層
１１ ｐ＋ シリコン基板
１２ ＣＶＤシリコン酸化膜
１３ ｎ＋ バッファ層
１４ ｎ− シリコン層1 Semiconductor substrate for IGBT 2 n- Silicon substrate 3 n+ Buffer layer (first silicon layer) 4 p+
Silicon layer (second silicon layer) 5 Gate electrode 6 Source electrode 7 P base layer 8 n- Silicon layer 9 n+ Buffer layer 10 p+ Drain layer 11 p+ Silicon substrate 12 CVD silicon oxide film 13 n+ Buffer layer 14 n- Silicon layer
Claims (2)
コン基板の一主表面上に拡散法または気相成長法によっ
て、該単結晶シリコン基板と同じ導電型を有し、抵抗率
が０．０５〜０．５Ωｃｍである単結晶の第１シリコン
層を形成する工程と、次いで該第１シリコン層と逆の導
電型を有し、抵抗率が第１シリコン層より低く、かつそ
の値が０．１Ωｃｍ以下の第２シリコン層を形成する工
程と、該単結晶シリコン基板を他方の主表面から所定の
厚さまで研削及び／または研磨加工する工程とを有する
ことを特徴とする半導体基板の製造方法。Claim: 1. A material having the same conductivity type as the single crystal silicon substrate and having a resistivity of 0.05 to 0.05 is deposited on one main surface of a single crystal silicon substrate having a resistivity of 30 Ωcm or more by a diffusion method or a vapor phase growth method. forming a single-crystal first silicon layer having a resistivity of 0.5 Ωcm, and then having a conductivity type opposite to that of the first silicon layer, having a resistivity lower than that of the first silicon layer, and having a resistivity of 0.1 Ωcm; A method for manufacturing a semiconductor substrate, comprising the following steps of forming a second silicon layer, and grinding and/or polishing the single crystal silicon substrate from the other main surface to a predetermined thickness.
単結晶シリコン基板の一主表面上に拡散法または気相成
長法によって、リン濃度１０１６〜１０１８ｃｍ−３の
ｎ型単結晶の第１シリコン層を形成する工程と、次いで
該第１シリコン層上に気相成長法にてホウ素濃度が１０
１８ｃｍ−３以上のｐ型の単結晶の第２シリコン層を形
成する工程と、該単結晶シリコン基板を他方の主表面か
ら所定の厚さまで研削及び／または研磨加工する工程と
を有することを特徴とする半導体基板の製造方法。2. An n-type single-crystal first silicon layer with a phosphorus concentration of 1016 to 1018 cm-3 is formed on one main surface of an n-type single-crystal silicon substrate with a phosphorus concentration of 1016 to 1018 cm-3 by a diffusion method or a vapor phase growth method. and then a step of forming a boron concentration of 10 on the first silicon layer by vapor phase epitaxy.
It is characterized by comprising a step of forming a p-type single crystal second silicon layer with a thickness of 18 cm or more, and a step of grinding and/or polishing the single crystal silicon substrate from the other main surface to a predetermined thickness. A method for manufacturing a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7473291A JPH04286163A (en) | 1991-03-14 | 1991-03-14 | Manufacture of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7473291A JPH04286163A (en) | 1991-03-14 | 1991-03-14 | Manufacture of semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04286163A true JPH04286163A (en) | 1992-10-12 |
Family
ID=13555700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7473291A Pending JPH04286163A (en) | 1991-03-14 | 1991-03-14 | Manufacture of semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04286163A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0702401A3 (en) * | 1994-08-31 | 1996-07-10 | Shinetsu Handotai Kk | Method for producing a semiconductor substrate suitable for IGBTs |
| DE19829614A1 (en) * | 1998-07-02 | 2000-01-13 | Semikron Elektronik Gmbh | Method for producing a power semiconductor component |
| WO2002061845A1 (en) * | 2001-02-01 | 2002-08-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| JP2004165619A (en) * | 2002-09-26 | 2004-06-10 | Mitsubishi Electric Corp | Semiconductor substrate and manufacturing method thereof, and semiconductor device and manufacturing method thereof |
| CN102054690A (en) * | 2010-11-22 | 2011-05-11 | 复旦大学 | Manufacturing method of semiconductor substrate of high-power device |
| JP2013030539A (en) * | 2011-07-27 | 2013-02-07 | Hitachi Ltd | Power semiconductor device, method of manufacturing power semiconductor device, and power conversion device |
| US20190347894A1 (en) * | 2015-11-19 | 2019-11-14 | Angel Playing Cards Co., Ltd. | Table game management system and game token |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6143474A (en) * | 1984-08-08 | 1986-03-03 | Toshiba Corp | Semiconductor device |
| JPS63205954A (en) * | 1987-02-23 | 1988-08-25 | Meidensha Electric Mfg Co Ltd | Semiconductor device |
| JPS63260176A (en) * | 1987-04-17 | 1988-10-27 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| JPH021985A (en) * | 1988-06-10 | 1990-01-08 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1991
- 1991-03-14 JP JP7473291A patent/JPH04286163A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6143474A (en) * | 1984-08-08 | 1986-03-03 | Toshiba Corp | Semiconductor device |
| JPS63205954A (en) * | 1987-02-23 | 1988-08-25 | Meidensha Electric Mfg Co Ltd | Semiconductor device |
| JPS63260176A (en) * | 1987-04-17 | 1988-10-27 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| JPH021985A (en) * | 1988-06-10 | 1990-01-08 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5696034A (en) * | 1994-08-31 | 1997-12-09 | Shin-Etsu Handotai Co., Ltd. | Method for producing semiconductor substrate |
| EP0702401A3 (en) * | 1994-08-31 | 1996-07-10 | Shinetsu Handotai Kk | Method for producing a semiconductor substrate suitable for IGBTs |
| DE19829614B4 (en) * | 1998-07-02 | 2004-09-23 | Semikron Elektronik Gmbh | Method for producing a power semiconductor component |
| DE19829614A1 (en) * | 1998-07-02 | 2000-01-13 | Semikron Elektronik Gmbh | Method for producing a power semiconductor component |
| US6815767B2 (en) | 2001-02-01 | 2004-11-09 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate transistor |
| JPWO2002061845A1 (en) * | 2001-02-01 | 2004-06-03 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| EP1271654A1 (en) * | 2001-02-01 | 2003-01-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| WO2002061845A1 (en) * | 2001-02-01 | 2002-08-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| US7250345B2 (en) | 2001-02-01 | 2007-07-31 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate transistor |
| EP1271654A4 (en) * | 2001-02-01 | 2008-11-05 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| US7560771B2 (en) | 2001-02-01 | 2009-07-14 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate transistor |
| JP5025071B2 (en) * | 2001-02-01 | 2012-09-12 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP2004165619A (en) * | 2002-09-26 | 2004-06-10 | Mitsubishi Electric Corp | Semiconductor substrate and manufacturing method thereof, and semiconductor device and manufacturing method thereof |
| CN102054690A (en) * | 2010-11-22 | 2011-05-11 | 复旦大学 | Manufacturing method of semiconductor substrate of high-power device |
| JP2013030539A (en) * | 2011-07-27 | 2013-02-07 | Hitachi Ltd | Power semiconductor device, method of manufacturing power semiconductor device, and power conversion device |
| US20190347894A1 (en) * | 2015-11-19 | 2019-11-14 | Angel Playing Cards Co., Ltd. | Table game management system and game token |
| US11783665B2 (en) | 2015-11-19 | 2023-10-10 | Angel Group Co., Ltd. | Table game management system and game token |
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