JP2911694B2 - Semiconductor substrate and method of manufacturing the same - Google Patents
Semiconductor substrate and method of manufacturing the sameInfo
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- JP2911694B2 JP2911694B2 JP31406092A JP31406092A JP2911694B2 JP 2911694 B2 JP2911694 B2 JP 2911694B2 JP 31406092 A JP31406092 A JP 31406092A JP 31406092 A JP31406092 A JP 31406092A JP 2911694 B2 JP2911694 B2 JP 2911694B2
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- silicon layer
- silicon
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- impurity
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Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体基板及びその製
造方法に関し、より詳しくは、インバータ、小型電力変
換装置等に使用されるＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ
Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）の
製造に適した半導体基板及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method of manufacturing the same, and more particularly, to an IGBT (Insulated) used for an inverter, a small power converter, and the like.
The present invention relates to a semiconductor substrate suitable for manufacturing a Gate Bipolar Transistor and a method for manufacturing the same.
【０００２】[0002]
【発明の背景技術】ＩＧＢＴは、パワーＭＯＳＦＥＴの
高速スイッチング特性とバイポーラトランジスタの高電
力特性とを併せ備え、パワー半導体素子として例えばイ
ンバータや小電力変換装置等に使用されている。2. Description of the Related Art An IGBT has both the high-speed switching characteristics of a power MOSFET and the high power characteristics of a bipolar transistor, and is used as a power semiconductor element in, for example, an inverter or a small power converter.
【０００３】ＩＧＢＴは、一般に、ｐ+単結晶シリコン
基板上にｎ+バッファ層及びｎ-層が形成されてなる半導
体基板のｎ-層にベース層やソース層等を形成して製造
される。このうち、ｎ+バッファ層の不純物濃度はＩＧ
ＢＴの動作特性に大きく影響し、ＩＧＢＴの高速動作を
可能にするためにはｎ+バッファ層の不純物濃度を精密
に制御する必要がある。An IGBT is generally manufactured by forming a base layer, a source layer and the like on an n − layer of a semiconductor substrate having an n + buffer layer and an n − layer formed on a p + single crystal silicon substrate. Of these, the impurity concentration of the n + buffer layer is IG
It greatly affects the operation characteristics of the BT, and it is necessary to precisely control the impurity concentration of the n + buffer layer in order to enable high-speed operation of the IGBT.
【０００４】ＩＧＢＴ用の半導体基板は、例えば高濃度
のホウ素をｐ型不純物として含むｐ+単結晶シリコン基
板の一主表面上に、基板の不純物濃度よりも低濃度のｎ
型不純物を含むｎ+バッファ層及びさらに低濃度のｎ型
不純物を含むｎ-層を順次エピタキシャル成長させて形
成する。このように、ｐ+単結晶シリコン基板の不純物
濃度はｎ+バッファ層やｎ-層の不純物濃度よりもはるか
に高いので、エピタキシャル成長を行う際には、基板の
裏面からホウ素が気化してエピタキシャル成長層に入り
込むいわゆるオートドープが起こる。このため、基板の
裏面にＣＶＤ酸化膜を形成し、ホウ素の気化を阻止した
状態でエピタキシャル成長が行われる。[0004] A semiconductor substrate for an IGBT is formed, for example, on one main surface of a p + single crystal silicon substrate containing high-concentration boron as a p-type impurity by forming n-concentration lower than that of the substrate.
An n + buffer layer containing n-type impurities and an n − layer containing n-type impurities at a lower concentration are sequentially grown by epitaxial growth. As described above, since the impurity concentration of the p + single crystal silicon substrate is much higher than the impurity concentration of the n + buffer layer and the n − layer, during epitaxial growth, boron is vaporized from the back surface of the substrate and the epitaxial growth layer The so-called auto doping that enters the film occurs. For this reason, a CVD oxide film is formed on the back surface of the substrate, and epitaxial growth is performed in a state where vaporization of boron is prevented.
【０００５】しかし、上記のようにＣＶＤ酸化膜を基板
の裏面に形成しても、基板の不純物濃度は極めて高いの
で、基板からのオートドープを完全に防ぐことはでき
ず、ｎ+バッファ層の不純物濃度を精密に制御すること
ができない。その結果、ｎ+バッファ層やｎ-層の抵抗率
が変動し、さらにはｎ-層がｐ型に反転することもあり
得るので、良好な電気特性を有する半導体装置の製造が
困難となる。[0005] However, even if the CVD oxide film is formed on the back surface of the substrate as described above, the impurity concentration of the substrate is extremely high, so that auto-doping from the substrate cannot be completely prevented. The impurity concentration cannot be precisely controlled. As a result, the resistivity of the n + buffer layer and the n − layer fluctuates, and the n − layer may be inverted to the p-type, which makes it difficult to manufacture a semiconductor device having good electric characteristics.
【０００６】また、エピタキシャル成長時に基板周縁部
及び側端面のＣＶＤ酸化膜上にノジュールと呼ばれる多
結晶の突起状異常成長が起こり、基板の取り扱い時にこ
のノジュールが破損分離してエピタキシャル成長層を傷
つけることがある。In addition, during the epitaxial growth, abnormal growth of polycrystalline projections called nodules occurs on the CVD oxide film at the peripheral portion and side end surfaces of the substrate, and the nodules are broken and separated during handling of the substrate, which may damage the epitaxial growth layer. .
【０００７】さらに、ｎ-層にはＩＧＢＴのベース層や
ソース層が形成されることから、ｎ-層は高品質のエピ
タキシャル成長層である必要がある。従って、成長速度
をあまり速くすることができず、工程時間が長くなると
いう問題があった。Furthermore, n - since the base layer and the source layer of the IGBT is formed in the layer, n - layer needs to be epitaxially grown layer of high quality. Therefore, there was a problem that the growth rate could not be made too high, and the process time became long.
【０００８】そこで本発明者らは、特願平３−７４７３
２においてＩＧＢＴ用の半導体基板の新たな製造方法を
提案した。この方法は、低濃度のｎ型不純物を含むｎ-
単結晶シリコン基板上にそれよりも高濃度のｎ型不純物
を含むｎ+バッファ層及びさらに高濃度のｐ型不純物を
含むｐ+層を順次形成し、最後に基板の裏面を研削・研
磨加工するものである。ここで、ｐ+層を所定の厚さま
で成長させて基板の総厚を確保することにより、その後
のデバイス工程におけるハンドリングに十分耐えられる
ようにしている。この方法においては、ベース層やソー
ス層は基板裏面側に形成される。[0008] The inventors of the present invention have disclosed in Japanese Patent Application No. 3-7473.
2 proposed a new method of manufacturing a semiconductor substrate for an IGBT. N The method comprising the low-concentration n-type impurity of -
An n + buffer layer containing a higher concentration of n-type impurities and a p + layer containing a higher concentration of a p-type impurity are sequentially formed on a single crystal silicon substrate, and finally, the back surface of the substrate is ground and polished. Things. Here, the p + layer is grown to a predetermined thickness to secure the total thickness of the substrate, so that it can withstand handling in subsequent device processes sufficiently. In this method, the base layer and the source layer are formed on the back side of the substrate.
【０００９】具体的には図４に示すように、ｎ-単結晶
シリコン基板２１（リン濃度１０14ｃｍ-3以下、抵抗率
３０Ωｃｍ以上）に拡散法（例えばＰ０Ｃｌ3を用い
る）又はエピタキシャル成長法（例えばＰＨ3を用い
る）によってｎ+バッファ層２２を形成させ、次いでそ
の上に高濃度のｐ+層２３（ホウ素濃度１０18ｃｍ-3以
上、抵抗率０．１Ωｃｍ以下）をエピタキシャル成長さ
せてＩＧＢＴ用の半導体基板２０を製造する。More specifically, as shown in FIG. 4, a diffusion method (for example, using P0Cl 3 ) or an epitaxial growth method (for example, using P0Cl 3 ) is applied to an n − single-crystal silicon substrate 21 (phosphorus concentration: 10 14 cm −3 or less, resistivity: 30 Ωcm or more). An n + buffer layer 22 is formed by using, for example, PH 3 ), and a high-concentration p + layer 23 (boron concentration of 10 18 cm −3 or more and resistivity of 0.1 Ωcm or less) is epitaxially grown on the n + buffer layer 22 for IGBT. Is manufactured.
【００１０】この方法では、基板の不純物濃度よりも高
濃度の不純物を含むエピタキシャル成長層を順次形成す
るので、エピタキシャル成長時における基板からのオー
トドープの影響を無視することができ、ｎ+バッファ層
の不純物濃度を精密に制御することができる。また、ｐ
+層はベース層やソース層のような高品質シリコン層に
形成されるべき拡散層が形成されないので、特に高品質
を要求されることがなく、多結晶とならない範囲で高速
成長させることができる。さらに、オートドープを防止
するための酸化膜を基板の裏面及び側面に設ける必要が
なくなり、その分だけ工程数が短くなるばかりでなく、
ポリシリコンの異常成長によるノジュールの発生もなく
なる等、種々の効果がある方法である。In this method, an epitaxial growth layer containing an impurity having a higher concentration than the impurity concentration of the substrate is sequentially formed, so that the influence of autodoping from the substrate during epitaxial growth can be neglected, and the impurity of the n + buffer layer can be ignored. The concentration can be precisely controlled. Also, p
Since the + layer does not have a diffusion layer to be formed in a high quality silicon layer such as a base layer or a source layer, high quality is not particularly required, and high-speed growth can be performed within a range that does not become polycrystalline. . Further, it is not necessary to provide an oxide film for preventing autodoping on the back surface and side surfaces of the substrate, which not only shortens the number of steps but also reduces the number of steps.
This is a method having various effects such as no generation of nodules due to abnormal growth of polysilicon.
【００１１】[0011]
【発明が解決しようとする課題】上記の方法では、基板
の総厚を確保するためにｐ+層を数百μｍとかなり厚く
堆積させる必要がある。例えば、直径が５インチ以上の
大口径基板を用いる場合、基板の総厚は４００μｍ以上
必要とされ、そのためにはｐ+層の厚さは少なくとも２
００μｍ以上堆積する必要がある。In the above-mentioned method, it is necessary to deposit a p + layer as thick as several hundred μm to secure the total thickness of the substrate. For example, when using a large-diameter substrate having a diameter of 5 inches or more, the total thickness of the substrate is required to be 400 μm or more, and for that, the thickness of the p + layer is at least 2 μm.
It is necessary to deposit at least 00 μm.
【００１２】しかし、ホウ素のような原子半径がシリコ
ンよりも小さいドーパントを高濃度ｐ+層に用いると、
ｐ+層を厚く成長させた場合には、このホウ素とシリコ
ンの格子間距離の差異により基板のｐ+層を堆積する面
側が凹状に反ってしまうことがある。例えば研削・研磨
加工後の基板の総厚が４００μｍ以上必要とする場合に
は、ｐ+層を少なくとも２００μｍ以上堆積しなければ
ならないが、この場合には１５０μｍ以上の反りが生じ
る。However, when a dopant such as boron having a smaller atomic radius than silicon is used for the high-concentration p + layer,
When the p + layer is grown thick, the difference in the interstitial distance between boron and silicon may cause the surface of the substrate on which the p + layer is deposited to be warped concavely. For example, if the total thickness of the substrate after the grinding and polishing is required to be 400 μm or more, the p + layer must be deposited at least 200 μm or more. In this case, warpage of 150 μm or more occurs.
【００１３】このような反りを持った基板を使用してそ
の後のデバイス製造プロセスを行うと、プロセス不良を
起こし易くなる。例えば、フォトリソ工程で基板にレジ
ストを塗布する際に基板がチャックに吸着しなかった
り、辛うじて吸着されたとしても後にパターンくずれ等
の問題を生じることとなる。When a subsequent device manufacturing process is performed using a substrate having such a warp, a process failure is likely to occur. For example, when a resist is applied to a substrate in a photolithography process, the substrate does not adhere to the chuck, or even if the substrate barely adheres, problems such as pattern collapse will occur later.
【００１４】そこで本発明は、各層の不純物濃度を精密
に制御することができるとともに基板の反りが生じない
半導体基板及びその製造方法を提供することを目的とす
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor substrate capable of precisely controlling the impurity concentration of each layer and preventing the substrate from being warped, and a method of manufacturing the same.
【００１５】[0015]
【課題を解決するための手段】本発明は、特許請求の範
囲の請求項１に記載したように、低濃度の不純物を含む
第１導電型の単結晶シリコン基板と、該単結晶シリコン
基板の一主表面上に形成され、前記単結晶シリコン基板
の不純物濃度よりも高濃度の不純物を含む第１導電型の
第１シリコン層と、該第１シリコン層上に形成され、前
記第１シリコン層の不純物濃度よりも高濃度で原子半径
がシリコンよりも小さい不純物を含む第２導電型の第２
シリコン層と、該第２シリコン層上に形成され、不純物
を全く含まないか又は前記第２シリコン層の不純物濃度
の０．０１６倍以下の不純物を含む第２導電型の第３シ
リコン層とを有することを特徴とする半導体基板を提供
する。According to the present invention, as described in claim 1, a first conductivity type single crystal silicon substrate containing a low concentration impurity is provided. A first conductivity type first silicon layer formed on one main surface and containing an impurity at a higher concentration than an impurity concentration of the single crystal silicon substrate; and the first silicon layer formed on the first silicon layer. Of the second conductivity type containing an impurity having a higher atomic concentration and an atomic radius smaller than that of silicon.
A silicon layer, formed on the second silicon layer and containing no impurities or an impurity concentration of the second silicon layer;
And a third silicon layer of the second conductivity type containing 0.016 times or less of the impurity of the second conductivity type.
【００１６】また本発明は、請求項２に記載したよう
に、前記第２シリコン層に含まれる不純物はホウ素であ
る請求項１に記載の半導体基板を提供する。According to a second aspect of the present invention, there is provided the semiconductor substrate according to the first aspect, wherein the impurity contained in the second silicon layer is boron.
【００１７】また本発明は、請求項３に記載したよう
に、前記単結晶シリコン基板の不純物濃度は１０14ｃｍ
-3以下（抵抗率３０Ωｃｍ以上）、前記第１シリコン層
の不純物濃度は１０16〜１０19ｃｍ-3（抵抗率０．００
６〜０．５Ωｃｍ）、前記第２シリコン層の不純物濃度
は１０18ｃｍ-3以上（抵抗率０．０６Ωｃｍ以下）及び
前記第３シリコン層の不純物濃度は１．６×１０16ｃｍ
-3以下（抵抗率１Ωｃｍ以上）である請求項１又は請求
項２に記載の半導体基板を提供する。According to a third aspect of the present invention, the single crystal silicon substrate has an impurity concentration of 10 14 cm.
-3 or less (resistivity 30 Ωcm or more), and the impurity concentration of the first silicon layer is 10 16 to 10 19 cm -3 (resistivity 0.00
6 to 0.5 Ωcm), the impurity concentration of the second silicon layer is 10 18 cm −3 or more (resistivity 0.06 Ωcm or less), and the impurity concentration of the third silicon layer is 1.6 × 10 16 cm.
The semiconductor substrate according to claim 1, wherein the semiconductor substrate has a resistivity of −3 or less (resistivity of 1 Ωcm or more).
【００１８】また本発明は、請求項４に記載したよう
に、前記第２シリコン層の膜厚は１０〜１２０μｍ、前
記第３シリコン層の膜厚は３０〜２００μｍである請求
項１ないし請求項３のいずれか１項に記載の半導体基板
を提供する。Further, according to the present invention, the second silicon layer has a thickness of 10 to 120 μm, and the third silicon layer has a thickness of 30 to 200 μm. 3. A semiconductor substrate according to any one of the above items 3.
【００１９】また本発明は、請求項５に記載したよう
に、低濃度の不純物を含む第１導電型の単結晶シリコン
基板の一主表面上に前記単結晶シリコン基板の不純物濃
度よりも高濃度の不純物を含む第１導電型の第１シリコ
ン層を形成する工程と、該第１シリコン層上に前記第１
シリコン層の不純物濃度よりも高濃度で原子半径がシリ
コンよりも小さい不純物を含む第２導電型の第２シリコ
ン層を形成する工程と、該第２シリコン層上に不純物を
全く含まないか又は前記第２シリコン層の不純物濃度の
０．０１６倍以下の不純物を含む第２導電型の第３シリ
コン層を形成する工程と、前記単結晶シリコン基板の前
記一主表面とは反対側の他方の主表面を所定の厚さまで
研削及び／又は研磨加工する工程とを有することを特徴
とする半導体基板の製造方法を提供する。According to a fifth aspect of the present invention, there is provided a semiconductor device, comprising: a first conductive type single-crystal silicon substrate containing a low-concentration impurity; Forming a first silicon layer of a first conductivity type containing a first impurity, and forming the first silicon layer on the first silicon layer.
Forming a second silicon layer of the second conductivity type containing an impurity whose concentration is higher than the impurity concentration of the silicon layer and whose atomic radius is smaller than that of silicon; and The impurity concentration of the second silicon layer
Forming a third silicon layer of the second conductivity type containing 0.016 times or less of impurities, grinding and grinding the other main surface of the single crystal silicon substrate opposite to the one main surface to a predetermined thickness; And / or a polishing step.
【００２０】また本発明は、請求項６に記載したよう
に、前記第１シリコン層は拡散法又は気相成長法により
形成し、第２及び第３シリコン層は気相成長法により形
成するものである請求項５に記載の半導体基板の製造方
法を提供する。Further, according to the present invention, the first silicon layer is formed by a diffusion method or a vapor growth method, and the second and third silicon layers are formed by a vapor growth method. A method for manufacturing a semiconductor substrate according to claim 5, wherein
【００２１】また本発明は、請求項７に記載したよう
に、前記第２シリコン層に含まれる不純物はホウ素であ
る請求項５又は請求項６に記載の半導体基板の製造方法
を提供する。The present invention also provides a method of manufacturing a semiconductor substrate according to claim 5 or claim 6, wherein the impurity contained in the second silicon layer is boron.
【００２２】また本発明は、請求項８に記載したよう
に、前記単結晶シリコン基板の不純物濃度は１０14ｃｍ
-3以下（抵抗率３０Ωｃｍ以上）、前記第１シリコン層
の不純物濃度は１０16〜１０19ｃｍ-3（抵抗率０．００
６〜０．５Ωｃｍ）、前記第２シリコン層の不純物濃度
は１０18ｃｍ-3以上（抵抗率０．０６Ωｃｍ以下）及び
第３シリコン層の不純物濃度は１．６×１０16ｃｍ-3以
下（抵抗率１Ωｃｍ以上）である請求項５ないし請求項
７のいずれか１項に記載の半導体基板の製造方法を提供
する。According to the present invention, the single crystal silicon substrate has an impurity concentration of 10 14 cm.
-3 or less (resistivity 30 Ωcm or more), and the impurity concentration of the first silicon layer is 10 16 to 10 19 cm -3 (resistivity 0.00
6 to 0.5 Ωcm), the impurity concentration of the second silicon layer is 10 18 cm -3 or more (resistivity 0.06 Ωcm or less), and the impurity concentration of the third silicon layer is 1.6 × 10 16 cm -3 or less ( The method for manufacturing a semiconductor substrate according to any one of claims 5 to 7, which has a resistivity of 1 Ωcm or more.
【００２３】また本発明は、請求項９に記載したよう
に、前記第２シリコン層の膜厚は１０〜１２０μｍ、前
記第３シリコン層の膜厚は３０〜２００μｍである請求
項５ないし請求項８のいずれか１項に記載の半導体基板
の製造方法を提供する。In the present invention, the thickness of the second silicon layer is 10 to 120 μm, and the thickness of the third silicon layer is 30 to 200 μm. 8. A method for manufacturing a semiconductor substrate according to any one of items 8 to 8.
【００２４】[0024]
【作用】本発明においては、不純物濃度の高いｐ+層の
上にさらに不純物を全く含まない又はｐ+層の不純物濃
度よりも十分に低濃度の不純物を含むｐ-層を十分厚く
成長させ、このｐ-層の厚みによって基板の総厚を確保
するようにしたので、不純物濃度の高いｐ+層を厚く堆
積させる必要がなくなる。しかも、高濃度ｐ+層の上に
低濃度のｐ-層を堆積することにより、基板の堆積側表
層部の原子半径は大きくなる。従って、従来のように原
子半径の小さい不純物を多量に含むｐ+層をｎ型単結晶
シリコン基板の上に厚く堆積させることによる基板の反
りは生じず、その後のデバイス製造プロセスにおける加
工上の不具合を低減することができる。In [act invention, p comprises a sufficiently low concentration of impurity than the impurity concentration of the totally included no or p + layer further impurities on the high impurity concentration p + layer - thick enough to grow a layer, Since the total thickness of the substrate is ensured by the thickness of the p − layer, it is not necessary to deposit a thick p + layer having a high impurity concentration. Moreover, by depositing a low-concentration p − layer on the high-concentration p + layer, the atomic radius of the surface layer on the deposition side of the substrate becomes large. Therefore, unlike the conventional case, the substrate is not warped by thickly depositing the p + layer containing a large amount of impurities having a small atomic radius on the n-type single-crystal silicon substrate, and there is a problem in processing in a subsequent device manufacturing process. Can be reduced.
【００２５】なお、不純物濃度の低いｐ-層はデバイス
完成時には不要な層であるが、従来の基板プロセスにお
いてもデバイス形成プロセス完了後に基板の裏面をバッ
クラップ方式により４５〜２１５μｍ程度研削除去する
ことから、本発明においてもデバイス形成プロセス完了
後にｐ-層を研削除去してｐ+層を露出させることによ
り、最終的に従来の半導体基板を用いた場合と同一構造
のデバイスを得ることができる。すなわち、ｐ-層は最
終的には除去される除去層（削り代分）として形成され
るものである。The p − layer having a low impurity concentration is unnecessary when the device is completed. However, in the conventional substrate process, the back surface of the substrate is ground and removed by about 45 to 215 μm after the device formation process is completed. Therefore, also in the present invention, the device having the same structure as that obtained by using the conventional semiconductor substrate can be finally obtained by grinding and removing the p − layer after the device forming process is completed to expose the p + layer. In other words, the p − layer is formed as a removed layer (a part for shaving) which is finally removed.
【００２６】[0026]
【実施例】以下、本発明の実施例について図を参照して
説明する。図１は、本発明の半導体基板の断面構造の一
例を示す。この半導体基板１０は、ｎ-単結晶シリコン
基板１１上にｎ+バッファ層１２を形成し、最後にｐ+層
１３及びｐ-層１４を積層してなるものである。なお、
図１ではｎ-単結晶シリコン基板１１面が上側を向くよ
うに示してあるが、これは、その後のデバイス形成工程
でｎ型単結晶シリコン基板１１面側にＩＧＢＴのソース
層やベース層が形成されるものであることを表してい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of a cross-sectional structure of a semiconductor substrate of the present invention. This semiconductor substrate 10 is formed by forming an n + buffer layer 12 on an n − single crystal silicon substrate 11 and finally stacking a p + layer 13 and a p − layer 14. In addition,
Although FIG. 1 shows that the n − single-crystal silicon substrate 11 surface faces upward, the source and base layers of the IGBT are formed on the n-type single-crystal silicon substrate 11 surface side in a subsequent device formation process. This is what is done.
【００２７】次に、本発明の半導体基板の基本的な製造
工程を図２（ａ）〜（ｅ）を参照して説明する。まず、
公知の方法にて鏡面加工された厚さ４００〜７５０μ
ｍ、直径１００〜１５０ｍｍ、リン濃度１０14ｃｍ-3以
下（抵抗率３０Ωｃｍ以上）のｎ-単結晶シリコン基板
１１（図２（ａ））の一主表面上に、拡散法又は気相成
長法にて厚さ３〜２５μｍ、リン濃度１０16〜１０19ｃ
ｍ-3（抵抗率０．５５〜０．００６Ωｃｍ）のｎ+バッ
ファ層１２を形成する（図２（ｂ））。Next, a basic manufacturing process of the semiconductor substrate of the present invention will be described with reference to FIGS. First,
400-750μ thickness mirror-finished by a known method
m, a diameter of 100 to 150 mm, and a phosphorus concentration of 10 14 cm −3 or less (resistivity of 30 Ωcm or more) on one main surface of an n − single crystal silicon substrate 11 (FIG. 2A) by a diffusion method or a vapor growth method. 3-25 μm in thickness, phosphorus concentration 10 16 -10 19 c
An n + buffer layer 12 having m −3 (resistivity 0.55 to 0.006 Ωcm) is formed (FIG. 2B).
【００２８】なお、ｎ+バッファ層１２を気相成長法で
形成する場合には、ｎ+バッファ層１２が単結晶シリコ
ン層となるような成長速度でエピタキシャル成長させ
る。この場合、ｎ+バッファ層１２のリン濃度はｎ-単結
晶シリコン基板１１のリン濃度よりも相当高いのでオー
トドープの影響が全くなく、ｎ+バッファ層１２のリン
濃度を精密に制御することができる。When the n + buffer layer 12 is formed by a vapor phase growth method, epitaxial growth is performed at a growth rate such that the n + buffer layer 12 becomes a single crystal silicon layer. In this case, since the phosphorus concentration of the n + buffer layer 12 is considerably higher than the phosphorus concentration of the n − single crystal silicon substrate 11, there is no influence of autodoping, and the phosphorus concentration of the n + buffer layer 12 can be precisely controlled. it can.
【００２９】次に、ｎ+バッファ層１２上に気相成長法
にて厚さ１０〜１００μｍ、ホウ素濃度１０18ｃｍ-3以
上（抵抗率０．０６Ωｃｍ以下）のｐ+層１３を形成す
る（図２（ｃ））。ｐ+層１３は高品質を要求されない
ため、単結晶シリコン層となる範囲で可能な限り高速成
長させることができる。また、ｎ+層１２のリン濃度は
ｐ+層１３のホウ素濃度よりも十分低いため、やはりオ
ートドープの影響を無視することができる。Next, a p + layer 13 having a thickness of 10 to 100 μm and a boron concentration of 10 18 cm −3 or more (resistivity of 0.06 Ωcm or less) is formed on the n + buffer layer 12 by a vapor phase growth method ( (FIG. 2 (c)). Since the p + layer 13 is not required to have high quality, it can be grown as fast as possible within the range of the single crystal silicon layer. Further, since the phosphorus concentration of the n + layer 12 is sufficiently lower than the boron concentration of the p + layer 13, the effect of the autodoping can be ignored.
【００３０】次に、ｐ+層１３上に気相成長法によって
通常の抵抗率１Ωｃｍ以上で厚さが３０〜２００μｍの
ｐ-層１４を形成する（図２（ｄ））。このｐ-層１４も
高品質を要求されないので高速成長させることができ
る。また、最終的に除去される層なので、基板からのオ
ートドープが生じても不都合はない。Next, a p - layer 14 having a normal resistivity of 1 Ωcm or more and a thickness of 30 to 200 μm is formed on the p + layer 13 by a vapor phase growth method (FIG. 2D). Since the p - layer 14 does not require high quality, it can be grown at a high speed. Further, since the layer is finally removed, there is no inconvenience even if autodoping occurs from the substrate.
【００３１】最後に、図２（ｄ）で得られた基板のｐ-
層１４を表面が平滑になるまで破線のように研磨した
後、ｎ-単結晶シリコン基板１１面を厚さが５０〜２５
０μｍになるまで破線のように通常の研削・研磨加工を
することにより、本発明の半導体基板１０を得ることが
できる（図２（ｅ））。ここで、ｎ-単結晶シリコン基
板１１面を上側に向けた場合が図１に示した半導体基板
１０に相当する。[0031] Finally, the substrate obtained in Fig. 2 (d) p -
After the layer 14 is polished as indicated by the broken line until the surface becomes smooth, the surface of the n - single crystal silicon substrate 11 is polished to a thickness of 50 to 25.
The semiconductor substrate 10 of the present invention can be obtained by performing ordinary grinding / polishing processing as shown by a broken line until the thickness becomes 0 μm (FIG. 2E). Here, the case where the n − single-crystal silicon substrate 11 surface faces upward corresponds to the semiconductor substrate 10 shown in FIG.
【００３２】次に、さらに具体的な実施例について説明
する。 ［実施例１］基板ウエーハとして、ＦＺ法で作製された
面方位〈１００〉、リン濃度３×１０13ｃｍ-3、抵抗率
１５０Ωｃｍ、直径１２５ｍｍ、初期厚さ５５０μｍの
ｎ型単結晶シリコン基板を用い、縦型エピタキシャル・
リアクターのサセプタ上に並べた。Next, a more specific embodiment will be described. [Example 1] As a substrate wafer, an n-type single-crystal silicon substrate having a plane orientation <100>, a phosphorus concentration of 3 × 10 13 cm −3 , a resistivity of 150 Ωcm, a diameter of 125 mm, and an initial thickness of 550 μm manufactured by the FZ method was used. Use vertical epitaxial
Arranged on the susceptor of the reactor.
【００３３】次に、水素雰囲気中で上記シリコン基板を
１１５０℃まで加熱し、その後トリクロロシラン５リッ
トル／ｍｉｎ及び水素８０リットル／ｍｉｎに加えて水
素希釈のホスフィン０．２リットル／ｍｉｎを供給し、
２．０±０．１μｍ／ｍｉｎの成長速度で５分間堆積さ
せ、層厚１０±１μｍのｎ+バッファ層を形成した。ホ
スフィンの添加量は、堆積されるシリコン層のリン濃度
が８．７×１０16ｃｍ-3、抵抗率が０．１±０．０１Ω
ｃｍになるように調整した。Next, the silicon substrate is heated to 1150 ° C. in a hydrogen atmosphere, and then, phosphine diluted with hydrogen is supplied at 0.2 l / min in addition to 5 l / min of trichlorosilane and 80 l / min of hydrogen.
Deposition was performed at a growth rate of 2.0 ± 0.1 μm / min for 5 minutes to form an n + buffer layer having a thickness of 10 ± 1 μm. The amount of phosphine added is such that the silicon concentration to be deposited is 8.7 × 10 16 cm −3 and the resistivity is 0.1 ± 0.01Ω.
cm.
【００３４】次に、基板の温度を１１５０℃に保ったま
ま、水素雰囲気中で１０分間保持した後、トリクロロシ
ラン１０リットル／ｍｉｎ及び水素８０リットル／ｍｉ
ｎに加えて水素希釈のジボランガス０．５リットル／ｍ
ｉｎを供給し、４．０±０．２μｍ／ｍｉｎの成長速度
で２５分間堆積させ、１００±１０μｍのｐ+層を形成
した。ジボランガスの添加量は、堆積されるシリコン層
のホウ素濃度が２．２×１０19ｃｍ-3、抵抗率が０．０
０５±０．００１Ωｃｍになるように調整した。Next, after maintaining the substrate temperature at 1150 ° C. in a hydrogen atmosphere for 10 minutes, trichlorosilane 10 liter / min and hydrogen 80 liter / mi
0.5 liter / m of diborane gas diluted with hydrogen in addition to n
In was supplied and deposited at a growth rate of 4.0 ± 0.2 μm / min for 25 minutes to form a p + layer of 100 ± 10 μm. The amount of diborane gas added is such that the boron concentration of the silicon layer to be deposited is 2.2 × 10 19 cm −3 and the resistivity is 0.0
It was adjusted to be 0.05 ± 0.001Ωcm.
【００３５】次に、トリクロロシラン１０リットル／ｍ
ｉｎ及び水素８０リットル／ｍｉｎを供給し、４．０±
０．２μｍ／ｍｉｎの成長速度で４０分間堆積させ、１
００±１０μｍのｐ-層を形成した。Next, trichlorosilane 10 liter / m
in and 80 l / min of hydrogen, and 4.0 ±
Deposited at a growth rate of 0.2 μm / min for 40 minutes,
A p - layer of 00 ± 10 μm was formed.
【００３６】次に、縦型エピタキシャル・リアクターか
ら取り出した後、ｐ-層の表面を１０μｍ研磨して平滑
にし、さらにｎ型単結晶シリコン基板を厚さ１９０μｍ
まで研削・研磨することにより、基板の総厚が４１０μ
ｍのＩＧＢＴ用半導体基板を得た。そして、得られた半
導体基板の反りを測定した（図３参照）。Next, after being taken out of the vertical epitaxial reactor, the surface of the p - layer is polished and smoothed by 10 μm, and the n-type single crystal silicon substrate is further polished to a thickness of 190 μm.
By grinding and polishing to a total thickness of the substrate of 410μ
m of IGBT semiconductor substrates were obtained. Then, the warpage of the obtained semiconductor substrate was measured (see FIG. 3).
【００３７】［実施例２］実施例１と同一のｎ型単結晶
シリコン基板を用い、同一の縦型エピタキシャル・リア
クターのサセプタ上に並べ、同一の処理によってｎ+バ
ッファ層を形成した後、基板の温度を１１５０℃に保っ
たまま、水素雰囲気中で１０分間保持した後、トリクロ
ロシラン１０リットル／ｍｉｎ及び水素８０リットル／
ｍｉｎに加えて水素希釈のジボランガス０．５リットル
／ｍｉｎを供給し、４．０±０．２μｍ／ｍｉｎの成長
速度で２５分間堆積させ、１００±１０μｍのｐ+層を
形成した。ジボランガスの添加量は、堆積されるシリコ
ン層のホウ素濃度が２．２×１０19ｃｍ-3、抵抗率が
０．００５±０．００１Ωｃｍになるように調整した。Example 2 Using the same n-type single-crystal silicon substrate as in Example 1, arranging it on the susceptor of the same vertical epitaxial reactor and forming an n + buffer layer by the same process, After maintaining the temperature of 1150 ° C. in a hydrogen atmosphere for 10 minutes, trichlorosilane 10 liter / min and hydrogen 80 liter / min.
In addition, 0.5 liter / min of hydrogen-diluted diborane gas was supplied in addition to min, and deposition was performed at a growth rate of 4.0 ± 0.2 μm / min for 25 minutes to form a p + layer of 100 ± 10 μm. The addition amount of diborane gas was adjusted so that the silicon concentration of the silicon layer to be deposited was 2.2 × 10 19 cm −3 and the resistivity was 0.005 ± 0.001 Ωcm.
【００３８】次に、トリクロロシラン１０リットル／ｍ
ｉｎ及び水素８０リットル／ｍｉｎに加えて水素希釈の
ジボランガス０．０５リットル／ｍｉｎを供給し、４．
０±０．２μｍ／ｍｉｎの成長速度で３８分間堆積さ
せ、１００±１０μｍのｐ-層を形成した。ジボランガ
スの添加量は、堆積されるシリコン層のホウ素濃度が
２．７×１０15ｃｍ-3、抵抗率が５±１Ωｃｍになるよ
うに調整した。Next, trichlorosilane 10 liter / m
3. Diborane gas diluted with hydrogen is supplied at a rate of 0.05 L / min in addition to the hydrogen gas and hydrogen at 80 L / min.
0 ± 0.2 [mu] m / min to the growth rate in the deposition 38 min, p of 100 ± 10 [mu] m - to form a layer. The amount of diborane gas added was adjusted such that the silicon concentration of the deposited silicon layer was 2.7 × 10 15 cm −3 and the resistivity was 5 ± 1 Ωcm.
【００３９】次に、縦型エピタキシャル・リアクターか
ら取り出した後、実施例１と同一条件で研削研磨し、得
られた半導体基板の反りを測定した（図３参照）。Next, after being taken out of the vertical epitaxial reactor, it was ground and polished under the same conditions as in Example 1, and the warpage of the obtained semiconductor substrate was measured (see FIG. 3).
【００４０】［比較例］実施例１及び２で用いたのと同
一のｎ型単結晶シリコン基板を用い、同一の縦型エピタ
キシャル・リアクターのサセプタ上に並べ、同一の処理
によってｎ+バッファ層を形成した後、基板の温度を１
１５０℃に保ったまま、水素雰囲気中で１０分間保持し
た後、トリクロロシラン１０リットル／ｍｉｎ及び水素
８０リットル／ｍｉｎに加えて水素希釈のジボランガス
０．５リットル／ｍｉｎを供給し、４．０±０．２μｍ
／ｍｉｎの成長速度で５２分間堆積させ、２１０±１０
μｍのｐ+層を形成した。ジボランガスの添加量は、堆
積されるシリコン層のホウ素濃度が２．２×１０19ｃｍ
-3、抵抗率が０．００５±０．００１Ωｃｍになるよう
に調整した。Comparative Example Using the same n-type single-crystal silicon substrate as used in Examples 1 and 2, it was arranged on the susceptor of the same vertical epitaxial reactor, and the n + buffer layer was formed by the same processing. After the formation, the temperature of the substrate is set to 1
After maintaining the temperature at 150 ° C. in a hydrogen atmosphere for 10 minutes, in addition to trichlorosilane (10 L / min) and hydrogen (80 L / min), hydrogen-diluted diborane gas (0.5 L / min) was supplied. 0.2 μm
/ Min at a growth rate of / min.
A μm p + layer was formed. The amount of diborane gas added is such that the boron concentration of the silicon layer to be deposited is 2.2 × 10 19 cm.
−3 , the resistivity was adjusted to be 0.005 ± 0.001 Ωcm.
【００４１】次に、縦型エピタキシャル・リアクターか
ら取り出した後、実施例１及び２と同一条件で研削研磨
し、得られた半導体基板の反りを測定した（図３参
照）。Next, after being taken out of the vertical epitaxial reactor, it was ground and polished under the same conditions as in Examples 1 and 2, and the warpage of the obtained semiconductor substrate was measured (see FIG. 3).
【００４２】実施例１、２及び比較例におけるｐ+層及
びｐ-層の成長条件を表１にまとめた。Table 1 summarizes the growth conditions of the p + layer and the p − layer in Examples 1 and 2 and Comparative Example.
【００４３】[0043]
【表１】 ＴＣＳ Ｈ2 Ｂ2Ｈ6 堆積時間 ρ (l/min) (l/min) (l/min) (min) (Ωｃｍ) 実施例１ ｐ+層 １０ ８０ ０．５ ２５ ０．００５ ｐ-層 １０ ８０ − ４０ ［通常値］ 実施例２ ｐ+層 １０ ８０ ０．５ ２５ ０．００５ ｐ-層 １０ ８０ ０．０５ ３８ ［通常値］ 比較例 ｐ+層 １０ ８０ ０．５ ５２ ０．００５ ＴＣＳ：トリクロロシラン Ｂ2Ｈ6：ジボランTABLE 1 TCS H 2 B 2 H 6 deposition time ρ (l / min) (l / min) (l / min) (min) (Ωcm) Example 1 p + layer 10 80 0.5 25 0.005 p − layer 1080 −40 [normal value] Example 2 p + layer 1080 0.525 0.005 p − layer 1080 0.0538 [normal value] Comparative example p + layer 1080 0.552 0.005 TCS: trichlorosilane B 2 H 6 : diborane
【００４４】図３から分かるように、実施例１及び２の
半導体基板はいずれも反りが５０μｍ以下であったのに
対し、比較例の半導体基板は反りが１５０μｍ程度に達
した。As can be seen from FIG. 3, the warpage of each of the semiconductor substrates of Examples 1 and 2 was 50 μm or less, while the warpage of the semiconductor substrate of the comparative example reached about 150 μm.
【００４５】[0045]
【発明の効果】以上の説明で明らかなように本発明によ
れば、各層の不純物濃度が精密に制御され且つ反りの小
さいＩＧＢＴ用の半導体基板を得ることができる。この
結果、デバイス形成工程でのトラブルが無くなり、これ
に伴い生産性のアップ、コストの低減が図れ、さらにＩ
ＧＢＴの用途に適した半導体基板を提供することが可能
となる。As is apparent from the above description, according to the present invention, it is possible to obtain an IGBT semiconductor substrate in which the impurity concentration of each layer is precisely controlled and the warpage is small. As a result, troubles in the device forming process are eliminated, thereby increasing productivity and reducing costs.
A semiconductor substrate suitable for GBT applications can be provided.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の半導体基板の断面構造の一例を示す断
面図である。FIG. 1 is a sectional view showing an example of a sectional structure of a semiconductor substrate of the present invention.
【図２】本発明の半導体基板の製造工程を示す工程図で
ある。FIG. 2 is a process chart showing a manufacturing process of a semiconductor substrate of the present invention.
【図３】実施例及び比較例のＩＧＢＴ用半導体基板の反
りの程度を示すグラフである。FIG. 3 is a graph showing the degree of warpage of the IGBT semiconductor substrates of the example and the comparative example.
【図４】従来の半導体基板の断面構造を示す断面図であ
る。FIG. 4 is a sectional view showing a sectional structure of a conventional semiconductor substrate.
１０，２０ 半導体基板 １１，２１ ｎ-単結晶シリコン基板 １２，２２ ｎ+バッファ層 １３，２３ ｐ+層 １４ ｐ-層10, 20 Semiconductor substrate 11, 21 n - single crystal silicon substrate 12, 22 n + buffer layer 13, 23 p + layer 14 p - layer
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 29/78 H01L 21/336 H01L 21/205 ──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 29/78 H01L 21/336 H01L 21/205
Claims (9)
晶シリコン基板と、該単結晶シリコン基板の一主表面上
に形成され、前記単結晶シリコン基板の不純物濃度より
も高濃度の不純物を含む第１導電型の第１シリコン層
と、該第１シリコン層上に形成され、前記第１シリコン
層の不純物濃度よりも高濃度で原子半径がシリコンより
も小さい不純物を含む第２導電型の第２シリコン層と、
該第２シリコン層上に形成され、不純物を全く含まない
か又は前記第２シリコン層の不純物濃度の０．０１６倍
以下の不純物を含む第２導電型の第３シリコン層とを有
することを特徴とする半導体基板。1. A single-crystal silicon substrate of a first conductivity type containing a low-concentration impurity, and an impurity formed on one main surface of the single-crystal silicon substrate and having a higher concentration than an impurity concentration of the single-crystal silicon substrate. A first conductivity type first silicon layer including: and a second conductivity type impurity formed on the first silicon layer and having an impurity concentration higher than the impurity concentration of the first silicon layer and smaller in atomic radius than silicon. A second silicon layer of
It is formed on the second silicon layer and contains no impurities or 0.016 times the impurity concentration of the second silicon layer.
And a third silicon layer of the second conductivity type containing the following impurities.
ホウ素である請求項１に記載の半導体基板。2. The semiconductor substrate according to claim 1, wherein the impurity contained in the second silicon layer is boron.
１０14ｃｍ-3以下（抵抗率３０Ωｃｍ以上）、前記第１
シリコン層の不純物濃度は１０16〜１０19ｃｍ-3（抵抗
率０．００６〜０．５Ωｃｍ）、前記第２シリコン層の
不純物濃度は１０18ｃｍ-3以上（抵抗率０．０６Ωｃｍ
以下）及び前記第３シリコン層の不純物濃度は１．６×
１０16ｃｍ-3以下（抵抗率１Ωｃｍ以上）である請求項
１又は請求項２に記載の半導体基板。3. The single-crystal silicon substrate has an impurity concentration of 10 14 cm −3 or less (resistivity of 30 Ωcm or more).
The impurity concentration of the silicon layer is 10 16 to 10 19 cm −3 (resistivity 0.006 to 0.5 Ωcm), and the impurity concentration of the second silicon layer is 10 18 cm −3 or more (resistivity 0.06 Ωcm).
Below) and the impurity concentration of the third silicon layer is 1.6 ×
The semiconductor substrate according to claim 1, wherein the semiconductor substrate has a resistivity of 10 16 cm −3 or less (resistivity of 1 Ωcm or more).
０μｍ、前記第３シリコン層の膜厚は３０〜２００μｍ
である請求項１ないし請求項３のいずれか１項に記載の
半導体基板。4. The thickness of the second silicon layer is 10-12.
0 μm, and the thickness of the third silicon layer is 30 to 200 μm
The semiconductor substrate according to any one of claims 1 to 3, wherein
晶シリコン基板の一主表面上に前記単結晶シリコン基板
の不純物濃度よりも高濃度の不純物を含む第１導電型の
第１シリコン層を形成する工程と、該第１シリコン層上
に前記第１シリコン層の不純物濃度よりも高濃度で原子
半径がシリコンよりも小さい不純物を含む第２導電型の
第２シリコン層を形成する工程と、該第２シリコン層上
に不純物を全く含まないか又は前記第２シリコン層の不
純物濃度の０．０１６倍以下の不純物を含む第２導電型
の第３シリコン層を形成する工程と、前記単結晶シリコ
ン基板の前記一主表面とは反対側の他方の主表面を所定
の厚さまで研削及び／又は研磨加工する工程とを有する
ことを特徴とする半導体基板の製造方法。5. A first silicon of the first conductivity type containing an impurity at a higher concentration than the impurity concentration of the single crystal silicon substrate on one main surface of the single crystal silicon substrate of the first conductivity type containing a low concentration impurity. Forming a layer, and forming a second conductivity type second silicon layer on the first silicon layer, the second silicon layer having an impurity concentration higher than that of the first silicon layer and having an atomic radius smaller than that of silicon. Forming a third silicon layer of the second conductivity type on the second silicon layer, which contains no impurities or contains impurities of 0.016 times or less the impurity concentration of the second silicon layer; Grinding and / or polishing the other main surface of the single crystal silicon substrate opposite to the one main surface to a predetermined thickness.
長法により形成し、第２及び第３シリコン層は気相成長
法により形成するものである請求項５に記載の半導体基
板の製造方法。6. The method according to claim 5, wherein the first silicon layer is formed by a diffusion method or a vapor deposition method, and the second and third silicon layers are formed by a vapor deposition method. Method.
ホウ素である請求項５又は請求項６に記載の半導体基板
の製造方法。7. The method according to claim 5, wherein the impurity contained in the second silicon layer is boron.
１０14ｃｍ-3以下（抵抗率３０Ωｃｍ以上）、前記第１
シリコン層の不純物濃度は１０16〜１０19ｃｍ-3（抵抗
率０．００６〜０．５Ωｃｍ）、前記第２シリコン層の
不純物濃度は１０18ｃｍ-3以上（抵抗率０．０６Ωｃｍ
以下）及び第３シリコン層の不純物濃度は１．６×１０
16ｃｍ-3以下（抵抗率１Ωｃｍ以上）である請求項５な
いし請求項７のいずれか１項に記載の半導体基板の製造
方法。8. The single crystal silicon substrate has an impurity concentration of 10 14 cm −3 or less (resistivity of 30 Ωcm or more),
The impurity concentration of the silicon layer is 10 16 to 10 19 cm −3 (resistivity 0.006 to 0.5 Ωcm), and the impurity concentration of the second silicon layer is 10 18 cm −3 or more (resistivity 0.06 Ωcm).
Below) and the impurity concentration of the third silicon layer is 1.6 × 10
The method for manufacturing a semiconductor substrate according to claim 5, wherein the semiconductor substrate has a resistivity of 16 cm −3 or less (resistivity of 1 Ωcm or more).
０μｍ、前記第３シリコン層の膜厚は３０〜２００μｍ
である請求項５ないし請求項８のいずれか１項に記載の
半導体基板の製造方法。9. The film thickness of the second silicon layer is 10-12.
0 μm, and the thickness of the third silicon layer is 30 to 200 μm
The method for manufacturing a semiconductor substrate according to claim 5, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31406092A JP2911694B2 (en) | 1992-10-29 | 1992-10-29 | Semiconductor substrate and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31406092A JP2911694B2 (en) | 1992-10-29 | 1992-10-29 | Semiconductor substrate and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06151864A JPH06151864A (en) | 1994-05-31 |
| JP2911694B2 true JP2911694B2 (en) | 1999-06-23 |
Family
ID=18048746
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31406092A Expired - Fee Related JP2911694B2 (en) | 1992-10-29 | 1992-10-29 | Semiconductor substrate and method of manufacturing the same |
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| Country | Link |
|---|---|
| JP (1) | JP2911694B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3113156B2 (en) * | 1994-08-31 | 2000-11-27 | 信越半導体株式会社 | Semiconductor substrate manufacturing method |
| DE19829614B4 (en) * | 1998-07-02 | 2004-09-23 | Semikron Elektronik Gmbh | Method for producing a power semiconductor component |
| TWI305927B (en) * | 2001-03-29 | 2009-02-01 | Toshiba Kk | Semiconductor device and method of making the same |
| JP4676708B2 (en) * | 2004-03-09 | 2011-04-27 | 新電元工業株式会社 | Manufacturing method of semiconductor device |
| US7494888B2 (en) * | 2004-06-23 | 2009-02-24 | Agere Systems Inc. | Device and method using isotopically enriched silicon |
| JP4746927B2 (en) * | 2005-07-01 | 2011-08-10 | 新電元工業株式会社 | Manufacturing method of semiconductor device |
| KR100793607B1 (en) * | 2006-06-27 | 2008-01-10 | 매그나칩 반도체 유한회사 | Epitaxial silicon wafer and method for manufacturing the same |
| CN102054690B (en) * | 2010-11-22 | 2012-10-17 | 复旦大学 | Manufacturing method of semiconductor substrate of high-power device |
| JP6844130B2 (en) * | 2015-08-18 | 2021-03-17 | 富士電機株式会社 | Semiconductor devices and their manufacturing methods |
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|---|---|
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