JPH02291123A - Silicon carbide semiconductor device - Google Patents
Silicon carbide semiconductor deviceInfo
- Publication number
- JPH02291123A JPH02291123A JP1111400A JP11140089A JPH02291123A JP H02291123 A JPH02291123 A JP H02291123A JP 1111400 A JP1111400 A JP 1111400A JP 11140089 A JP11140089 A JP 11140089A JP H02291123 A JPH02291123 A JP H02291123A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon carbide
- crystal layer
- single crystal
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 71
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 69
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000013078 crystal Substances 0.000 claims abstract description 61
- 150000002500 ions Chemical class 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000137 annealing Methods 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 20
- 229910052796 boron Inorganic materials 0.000 abstract description 5
- -1 boron ions Chemical class 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 88
- 239000012535 impurity Substances 0.000 description 13
- 230000005669 field effect Effects 0.000 description 8
- 238000001947 vapour-phase growth Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
Abstract
Description
【発明の詳細な説明】
（産業」二の利用分野）
本発明は，高抵抗炭化珪累単結晶層が電気絶縁層とチャ
ネル層とを兼ねる炭化珪素半導体装置，特に絶縁ゲート
型電界効果トランジスタに関する。[Detailed Description of the Invention] (Field of Application in Industry) The present invention relates to a silicon carbide semiconductor device in which a high-resistance silicon carbide cumulative single crystal layer serves as an electrical insulating layer and a channel layer, and in particular to an insulated gate field effect transistor. .
（従来の技術）
珪素（Ｓ１）を初めとして，ヒ化ガリウム（ＧａＡｓ）
やリン化ガリウム（ＧａＰ ）などの化合物半導体を用
いた半導体装置（例えば，ダイオード，トランシスタ，
集積回路，大規模集積回路，発光ダイオド，半導体レー
ザ，および電荷結合素子）がエレクトロニクスの各分野
において広範囲に実用化されている。(Prior art) Starting with silicon (S1), gallium arsenide (GaAs)
Semiconductor devices (e.g. diodes, transistors,
Integrated circuits, large-scale integrated circuits, light emitting diodes, semiconductor lasers, and charge-coupled devices) have been widely used in various fields of electronics.
炭化珪素（ＳｉＣ）は広い禁制帯幅（２． ２〜３．
３ｅＶ）を有する半導体祠料であって，熱的，化学的，
および機械的に極めて安定であり，放射線損傷にも強い
という優れた特徴を持っている。珪素のような従来の半
導体材料を用いた半導体装置は，特に高温．高出力駆動
，放射線照射などの苛酷な条件下では使用が困難である
。従って，炭化珪素を用いた半導体装置は，このような
苛酷な条件下でも使用し得る半導体装置として広範な分
野での応用が期待されている。Silicon carbide (SiC) has a wide forbidden band width (2.2-3.
3eV), which has thermal, chemical,
It also has the excellent characteristics of being extremely mechanically stable and resistant to radiation damage. Semiconductor devices using conventional semiconductor materials such as silicon are particularly susceptible to high temperatures. It is difficult to use under harsh conditions such as high-output drive and radiation exposure. Therefore, semiconductor devices using silicon carbide are expected to be applied in a wide range of fields as semiconductor devices that can be used even under such harsh conditions.
しかしながら１大きな面積を有し，かつ高品質の炭化珪
素単結晶を，生産性を考慮した工業的規模で安定に供給
し得る結晶成長技術は確立されていない。それゆえ，炭
化珪素は，上述のような多くの利点および可能性を有す
る半導体材料であるにもかかわらず，その実用化が阻ま
れている。However, no crystal growth technology has been established that can stably supply large-area, high-quality silicon carbide single crystals on an industrial scale with productivity in mind. Therefore, although silicon carbide is a semiconductor material that has many advantages and possibilities as described above, its practical application has been hindered.
従来，研究室規模では，例えば昇華再結晶法（レーリー
法）で炭化珪素単結晶を成長させたり，該方法で得られ
た炭化珪素単結晶を基板としてその上に気相成長法（Ｃ
ＶＤ法）や液相エピタキシャル成長法（ＬＰＢ法）で炭
化珪素単結晶層をエビタキシャル成長させることにより
，半導体装置の試作が可能なサイズの炭化珪素単結晶を
得ている。Traditionally, on a laboratory scale, silicon carbide single crystals have been grown by sublimation recrystallization method (Rayleigh method), or silicon carbide single crystals obtained by this method have been grown using vapor phase growth method (C
By epitaxially growing a silicon carbide single crystal layer using the VD method (VD method) or the liquid phase epitaxial growth method (LPB method), a silicon carbide single crystal of a size that can be used for prototyping semiconductor devices is obtained.
しかしながら，これらの方法では，拐られた単結晶の面
積が小さく，その寸法や形状を高精度に制御することは
困難である。また，炭化珪素が有する結晶多形および不
純物濃度の制御も容易ではなＧ）。However, in these methods, the area of the single crystal removed is small, and it is difficult to control its size and shape with high precision. Furthermore, it is not easy to control the crystal polymorphism and impurity concentration of silicon carbide.
これらの問題点を解決するために，本発明者らは，安価
で入手の容易な珪素単結晶基板−Ｌに，大きな面積を有
する良質の炭化珪素単結晶を気相成長させる方法を提案
したく特開昭５９−２０３７９９号）。In order to solve these problems, the present inventors would like to propose a method of vapor phase growth of a high-quality silicon carbide single crystal with a large area on an inexpensive and easily available silicon single crystal substrate-L. JP-A-59-203799).
該方法において，炭化珪素を気相成長させる際に不純物
を添加すれば，得られた炭化珪素単結晶における不純物
濃度および伝導型を制御することが可能である。そして
，この方法により珪素基板上に形成した炭化珪素単結晶
層を利用して，各種の半導体装置（例えば，ダイオード
やトランジスタ）を製造する方法が開発されている（特
願昭５８−２４６５１１号，同昭５８−２４９９８１号
，および同昭５８−２５２１５７号）。In this method, if an impurity is added during vapor phase growth of silicon carbide, it is possible to control the impurity concentration and conductivity type in the obtained silicon carbide single crystal. A method for manufacturing various semiconductor devices (for example, diodes and transistors) using a silicon carbide single crystal layer formed on a silicon substrate using this method has been developed (Japanese Patent Application No. 58-246511, No. 58-249981 and No. 252157 of 1982).
従来，これらの炭化珪素半導体装置（例えば電界効果ト
ランジスタ）においては，チャネル層となる口型（また
はｐ型）の炭化珪素弔結晶層をｐ型（またはｎ型）の炭
化珪素単結晶層上に形成し，これら両層のｐｎ接合によ
り該チャ不ル層を半導体基板から電気的に絶縁していた
。しかしながら．このような構造の半導体装置では，
ｐｎ接合に逆ハイアス電圧を印加した場合に，炭化珪素
単結晶層中に存在する結晶欠陥により，半導体基板とチ
ャネル層との間にリーク電流が発生する。従って，チャ
ネル層を半導体基板から電気的に完全に絶縁することが
困難であり，良好なトランジスタ特性が得られなかった
。Conventionally, in these silicon carbide semiconductor devices (for example, field effect transistors), a mouth-shaped (or p-type) silicon carbide crystal layer that serves as a channel layer is formed on a p-type (or n-type) silicon carbide single crystal layer. The chamfer layer was electrically insulated from the semiconductor substrate by a pn junction between these two layers. however. In a semiconductor device with such a structure,
When a reverse high-ass voltage is applied to the pn junction, a leakage current is generated between the semiconductor substrate and the channel layer due to crystal defects present in the silicon carbide single crystal layer. Therefore, it is difficult to completely electrically insulate the channel layer from the semiconductor substrate, and good transistor characteristics cannot be obtained.
これに対し，半導体基板とチャネル層とを電気的に絶縁
するために，上記のような炭化珪素単結晶層間のρｎ接
合に代えて，半導体基板とチャネル層との間に，イオン
注入法で形成した高抵抗炭化珪素単結晶層を電気絶縁層
として用いることを先に特許出願した。このような構造
を有する炭化珪素半導体装置は５００℃付近の高温領域
まで素子特性が劣化しないという利点を有する。On the other hand, in order to electrically insulate the semiconductor substrate and the channel layer, instead of the ρn junction between the silicon carbide single crystal layers as described above, a ρn junction is formed between the semiconductor substrate and the channel layer by ion implantation. The company previously filed a patent application for using a high-resistance silicon carbide single crystal layer as an electrical insulating layer. A silicon carbide semiconductor device having such a structure has the advantage that device characteristics do not deteriorate up to a high temperature range of around 500°C.
（発明が解決しようとする課題）
しかしながら，炭化珪素弔結晶を用いて，特に絶縁ゲー
ト型電界効果トランジスタ （ＭＯＳＦＥＴ）などを形
成する場合には，電気絶縁層上にチャネル層を形成した
後，該チャネル層にドレイン領域とソース領域とを設け
る必要がある。また，該チャネル層」二には，さらにゲ
ート絶縁膜を形成する必要がある。従って，製造工程を
簡略化するために」二記の電気絶縁層とチャネル層とを
単一の高抵抗炭化珪素単結晶層で構成することが考えら
れるがこの場合には，電気絶縁層およびチャネル層とし
て機能するのに充分な抵抗を有する炭化珪素１３，結晶
層の形成方法が問題となる。このような形成方法として
は，例えば上記の気相成長法により，炭化珪素単結晶層
を成長させる際に不純物を添加する方法や，予め成長さ
せた炭化珪素単結晶層に不純物を熱拡散させる方法など
がある。(Problem to be Solved by the Invention) However, when forming an insulated gate field effect transistor (MOSFET) using a silicon carbide crystal, a channel layer is formed on an electrically insulating layer, and then the It is necessary to provide a drain region and a source region in the channel layer. Furthermore, it is necessary to further form a gate insulating film on the channel layer. Therefore, in order to simplify the manufacturing process, it is conceivable to configure the electrical insulating layer and the channel layer described in "2" with a single high-resistance silicon carbide single crystal layer. The problem is how to form a crystalline layer of silicon carbide 13 that has sufficient resistance to function as a layer. Such a formation method includes, for example, adding impurities when growing a silicon carbide single crystal layer using the above-mentioned vapor phase growth method, or thermally diffusing impurities into a silicon carbide single crystal layer that has been grown in advance. and so on.
しかしながら，気相成長の際に添加された炭化珪素単結
晶層中の不純物は，室温では全てがイオン化しているわ
けではなく，温度が上昇するにつれて，該炭化珪素単結
晶層中のキャリア濃度が−ヒ昇ずる。従って，該炭化珪
素単結晶層の抵抗率は，温度が上昇するにつれて低下す
る。また，不純物を添加しながら気相成長させると，炭
化珪素単結晶の成長層表面に多くの凹凸が発生する。従
って炭化珪素単結晶からなるチャネル層の表面の平坦性
が低下し，該チャネル層七に形成されるゲート絶縁膜の
特性に悪影響を及ぼすことになる。However, impurities in the silicon carbide single crystal layer added during vapor phase growth are not all ionized at room temperature, and as the temperature rises, the carrier concentration in the silicon carbide single crystal layer decreases. - He rises. Therefore, the resistivity of the silicon carbide single crystal layer decreases as the temperature increases. Furthermore, when vapor phase growth is performed while adding impurities, many irregularities occur on the surface of the growing layer of silicon carbide single crystal. Therefore, the flatness of the surface of the channel layer made of single crystal silicon carbide deteriorates, which adversely affects the characteristics of the gate insulating film formed on the channel layer 7.
他方，予め成長させた炭化珪素単結晶層に不純物を熱拡
散させて高抵抗層を形成する場合には炭化珪素中におけ
る不純物の拡敗定数が小さく，１，６００℃以−トの高
い拡散温度が必要である。従って，不純物濃度を制御す
ることが困難であり，しかも用いた半導体基板や炭化珪
素単結晶層が劣化するおそれがあるため，不純物熱拡散
法は炭化珪素半導体装置のプロセス技術として適当では
ない。On the other hand, when forming a high-resistance layer by thermally diffusing impurities into a silicon carbide single crystal layer grown in advance, the diffusion constant of impurities in silicon carbide is small, and a high diffusion temperature of 1,600°C or higher is required. is necessary. Therefore, the impurity thermal diffusion method is not suitable as a process technology for silicon carbide semiconductor devices because it is difficult to control the impurity concentration and there is a risk of deterioration of the semiconductor substrate or silicon carbide single crystal layer used.
本発明は１二記従来の問題点を解決するものであり，そ
の目的とするところは，高温領域においても電気絶縁層
およびチャネル層として機能する高抵抗炭化珪素単結晶
層を有する炭化珪素半導体装置を提供することにある。The present invention solves the 12 conventional problems, and its purpose is to provide a silicon carbide semiconductor device having a high-resistance silicon carbide single crystal layer that functions as an electrical insulating layer and a channel layer even in a high temperature region. Our goal is to provide the following.
（課題を解決するための手段）
本発ｌυｊは，電気絶縁層占チャ不ル層とを有ずる炭化
珪素半導体装置であって，該電気絶縁層およびチャネル
層が単一の高抵抗炭化珪素単結晶層から構成され，かつ
該高抵抗炭化珪素単結晶層が半導体基板上に成長させた
炭化珪素単結晶層に所定量のイオンを注入して，その表
面領域にイオン注入層を形成し，該イオン注入層を熱ア
ニール処理することにより形成され，そのことにより上
記１」的か達成される。(Means for Solving the Problems) The present invention lυj is a silicon carbide semiconductor device having an electrically insulating layer and an unoccupied layer, in which the electrically insulating layer and the channel layer are made of a single high-resistance silicon carbide monolayer. A predetermined amount of ions are implanted into a silicon carbide single crystal layer composed of a crystal layer, and the high resistance silicon carbide single crystal layer is grown on a semiconductor substrate to form an ion implantation layer in the surface region. It is formed by thermally annealing the ion-implanted layer, thereby achieving objective 1 above.
上記イオン注入層を形成する際には，イオン注入は１回
で行うこともできろし，複数回に分けて行うこともでき
る。この場合，注入条件を適切に調節することにより，
所定の不純物濃度および層厚を有ずるイオン注入層が得
られる。注入するイオンとしては，例えば，ホウ素（Ｂ
）イオン，アルミニウｌ、（Ａ１）イオン，ガリウム（
６ａ）イオンなどのＩ■族元素イオンが挙げられ，特に
ホウ素イオンが好ましい。When forming the ion-implanted layer, ion implantation can be performed in one step or can be performed in multiple steps. In this case, by appropriately adjusting the injection conditions,
An ion-implanted layer having a predetermined impurity concentration and layer thickness is obtained. Examples of ions to be implanted include boron (B).
) ion, aluminum l, (A1) ion, gallium (
6a) Group I2 element ions such as ions can be mentioned, and boron ions are particularly preferred.
得られたイオン注入層は，次いで熱アニール処理が施さ
れる。熱アニール処理は，不活性ガス（例えば． Ａｒ
ガス）雰囲気下，約ＬＯＯＧ〜１ ３００℃の温度で行
われる。この熱アニール処理により−１一記イオン注入
層は活性化されて高い抵抗率を有するようになり，電気
絶縁層およびチャネル層として機能し得る高抵抗炭化珪
素単結晶層が形成される。The obtained ion-implanted layer is then subjected to thermal annealing treatment. Thermal annealing treatment is performed using an inert gas (e.g. Ar
It is carried out at a temperature of about LOOG to 1300°C under an atmosphere of gas). This thermal annealing treatment activates the ion-implanted layer -1 to have high resistivity, forming a high-resistance silicon carbide single crystal layer that can function as an electrical insulating layer and a channel layer.
（実施例） 以下に本発明の実施例について説明する。(Example) Examples of the present invention will be described below.
第１図（ａ．）は，本発明の炭化珪素半導体装置の例で
ある絶縁ゲート型電界効果トランシスタ（Ｍ口ＳＦＥＴ
）を示す，、該ＭＯＳＦＥＴは以下のようにして作製さ
れた。FIG. 1(a) shows an insulated gate field effect transistor (M-type SFET) which is an example of the silicon carbide semiconductor device of the present invention.
), the MOSFET was manufactured as follows.
まず，第１図（ト））に示すように，気相成長（［Ｖｌ
１）法により，Ｓ１単結晶基板１」二にノンドープ８１
（：単結晶層２を成長させた。次いで，イオン注入装置
を用いて，ノンドープＳｉＣ単結晶層２の表面領域にホ
ウ素イオン（”Ｂ“）を２回に分けて注入することによ
り，第１図（Ｃ）に示ずようなＢイメ゛ン注入層３を形
成した。なお，注入条件は，加速電圧かそれぞれ２ ０
０ ｋ ｅ ｖおよびＨ）Ｏｋｅｌ，Ｉであり，Ｂイ
オンの注入量がそれぞれｌ ＸＩＯ”ｃｍ−２および５
Ｘ ｌ［］”ｃｍ−２であった。First, as shown in Figure 1 (g)), vapor phase growth ([Vl
1) Using the method, the S1 single crystal substrate 1'' is non-doped 81
(: A single crystal layer 2 was grown. Next, boron ions ("B") were implanted into the surface region of the non-doped SiC single crystal layer 2 in two steps using an ion implanter. A B main injection layer 3 as shown in Figure (C) was formed.The injection conditions were as follows:
0 k e v and H) Okel, I, and the implantation amount of B ions is l XIO”cm−2 and 5
X l[]”cm-2.
そして，約１．，０００〜１，３００℃にて熱アニール
処理を行うことにより，Ｂイオン注入層３を活性化させ
２第１図（ｄ）に示すような高抵抗ＳｉＣ単結晶層（す
なわち，電気絶縁層およびチャネル層）４を形成した。And about 1. By performing thermal annealing treatment at ,000 to 1,300°C, the B ion-implanted layer 3 is activated and a high-resistance SiC single crystal layer (i.e., electrically insulating layer and A channel layer) 4 was formed.
該高抵抗ＳｉＣ単結晶層４の抵抗率を測定したところ，
広い温度領域にわたって，抵抗率の低下はほよんど観察
されず，上記の高抵抗ＳｉＣ単結晶層４が電気絶縁層お
よびチャネル層として充分な性能を有することがわかっ
た。When the resistivity of the high resistance SiC single crystal layer 4 was measured,
Almost no decrease in resistivity was observed over a wide temperature range, indicating that the high-resistance SiC single crystal layer 4 had sufficient performance as an electrical insulating layer and a channel layer.
続いて， ［’：Ｖｆｌ法またはプラズマＣＶＤ法によ
り，高抵抗ＳＩＣ単結晶層４上にＳｉｎ，膜を形成した
。次いで，ポトリソグラフィーを用いて． Ｓｌ０２膜
の所定領域をエッチンクにより開口して，フィールド絶
縁膜５とした（第１図（Ｃ））。なお，エツチンクには
フッ化水素（１什）溶液を用いた。そして，イオン注入
装置を用い，フィールド絶縁膜５をマスクとして，高抵
抗Ｓ＋［単結晶層４の開ｉ−１１領域にリンイオン（３
１Ｐ”）を注入した。注入条件は，加速電圧力月００ｋ
ｅＶであり，Ｐイオンの注入量が３×１０１４ｃｍ−２
であった。次いで，約１，０００ 〜１ ２０［］ ℃
にて熱アニール処理を行うことにより，Ｐイオン注入領
域を活性化させ，第１図（ｅ）に示すようなソース領域
６およびドレイン領域７を形成した。Subsequently, a Sin film was formed on the high resistance SIC single crystal layer 4 by the [':Vfl method or plasma CVD method. Next, using potolithography. A predetermined region of the Sl02 film was opened by etching to form a field insulating film 5 (FIG. 1(C)). Note that a solution of hydrogen fluoride (1 liter) was used for etching. Then, using an ion implanter and using the field insulating film 5 as a mask, phosphorus ions (3
1P'') was injected.The injection conditions were: acceleration voltage, power, month, 00k
eV, and the amount of P ion implanted is 3 × 1014 cm-2
Met. Then, about 1,000 to 120[]℃
By performing a thermal annealing process, the P ion implanted region was activated, and a source region 6 and a drain region 7 as shown in FIG. 1(e) were formed.
さらに，ゲート領域に対応する部分のフィールド絶縁膜
５をエッチングにより除去した後，酸素雰囲気下， １
，１００℃にて４時間熱酸化を行うことにより，ゲート
絶縁膜８を形成した。最後に．ンス領域６およひトレイ
ン領域７に対応ずる開１１部分と，ゲート領域に対応ず
る部分のゲート絶縁１Ｊ
膜８上とに，それぞれアルミニウム（八１）を真空蒸着
した後，ホトリソグラフィーを用いて．ソース電極９，
ドレイン電極１０，およびゲート電極ｌ１を形成するこ
とにより，第１図（ａ）に示すようなＭ０ＳＦＩＥＴを
得た。Furthermore, after removing the field insulating film 5 in the portion corresponding to the gate region by etching, 1
The gate insulating film 8 was formed by performing thermal oxidation at 100° C. for 4 hours. lastly. Aluminum (81) was vacuum-deposited on the opening 11 portions corresponding to the train region 6 and the train region 7, and on the gate insulating film 1J on the gate insulating film 8 on the portion corresponding to the gate region, and then deposited using photolithography. ．． source electrode 9,
By forming the drain electrode 10 and the gate electrode l1, an M0SFIET as shown in FIG. 1(a) was obtained.
このようにして得られたＭＯＳＦＥＴにおいては，高抵
抗ＳｉＣ単結晶層４は電気絶縁層としてだけでなくチャ
ネル層としても作用する。つまり，ゲート電極１１に電
圧を印加すると，高抵抗ＳｉＣ単結晶層４の表面にチャ
ネル領域が発生し，該チャネル領域を通じてソース領域
６とドレイン領域７との間に電流が流れ，ＦεＴ動作が
行われる。このＭＯＳＦεＴのトランジスタ特性につい
て調べたところ，第２図に示すような特性図が得られた
。In the MOSFET thus obtained, the high resistance SiC single crystal layer 4 acts not only as an electrical insulating layer but also as a channel layer. In other words, when a voltage is applied to the gate electrode 11, a channel region is generated on the surface of the high resistance SiC single crystal layer 4, a current flows between the source region 6 and the drain region 7 through the channel region, and an FεT operation is performed. be exposed. When the transistor characteristics of this MOSFεT were investigated, a characteristic diagram as shown in FIG. 2 was obtained.
比較のために，Ｂイオン注入層３に代えて．ホウ素不純
物を添加しながら気相成長させた炭化珪素単結晶層を用
いること以外は上記の実施例と同様にして， ＭＯＳＦ
ＢＴを作製した。得られたＭＯＳＦＩＥＴのトランジス
タ特性を第３図に示す。For comparison, B ion-implanted layer 3 was used instead. A MOSFET was fabricated in the same manner as in the above example except that a silicon carbide single crystal layer grown in a vapor phase while adding boron impurities was used.
BT was produced. The transistor characteristics of the obtained MOSFIET are shown in FIG.
第２図および第３図から明らかなように，本実施例のＭ
ＯＳＦＢＴでは，電気絶縁層およびチャネル層として，
Ｂイオンを注入した高抵抗ＳｉＣ単結晶層４が用いられ
ているため，ゲート絶縁膜８の特性が向上すると共に，
チャネル層のソース領域６およびドレイン領域７から８
１単結晶基板１へのリク電流が低減された。また，この
ような良好なトランジスタ特性は高温領域まで安定であ
った。As is clear from FIGS. 2 and 3, M
In OSFBT, as an electrical insulating layer and a channel layer,
Since the high resistance SiC single crystal layer 4 implanted with B ions is used, the characteristics of the gate insulating film 8 are improved, and
Source region 6 and drain region 7 to 8 of the channel layer
1. The leakage current to the single crystal substrate 1 was reduced. Furthermore, these good transistor characteristics were stable even in the high temperature range.
（発明の効果）
本発明によれば，電気絶縁層およびチャネル層として作
用する高抵抗炭化珪素単結晶層をイオン注入法で形成す
るため．高温領域まで素子特性が安定な炭化珪素半導体
装置が得られる。このような炭化珪素半導体装置は，特
に高温動作用の半導体装置として有用である。また，本
発明は，通常のイオン注入技術を利用しているた約，種
々の炭化珪素半導体装置（例えば，ゲート絶縁型電界効
果トランジスタなど）を工業的規模で生産することが可
能になる。(Effects of the Invention) According to the present invention, a high-resistance silicon carbide single crystal layer that acts as an electrical insulating layer and a channel layer is formed by ion implantation. A silicon carbide semiconductor device with stable device characteristics up to a high temperature range can be obtained. Such a silicon carbide semiconductor device is particularly useful as a semiconductor device for high temperature operation. Further, the present invention makes it possible to produce various silicon carbide semiconductor devices (for example, gate insulated field effect transistors, etc.) on an industrial scale using ordinary ion implantation technology.
１ ？
例である絶縁ゲート型電界効果トランジスタの製造工程
を説明するための断面図，第２図は該電界効果トランジ
スタの素子特性を示す図，第３図は従来の方法で製造さ
れた絶縁ゲート型電界効果トランシスタの素子特性を示
す図である。1? A cross-sectional view for explaining the manufacturing process of an example insulated gate field effect transistor, FIG. 2 is a diagram showing the device characteristics of the field effect transistor, and FIG. 3 is an insulated gate field effect transistor manufactured by a conventional method. FIG. 3 is a diagram showing element characteristics of an effect transistor.
１・・・Ｓｉ単結晶基板，２・・ノンドープＳｉＣ単結
晶層，３・・Ｂイオン注入層，４・・・電気絶縁層およ
びチャネル層（高抵抗ＳｉＣ単結晶層），５・・フィル
ド絶縁膜，６・・・ソース領域，７・ ドレイン領域８
・・ゲート絶縁膜，９・・ソース電極，１０・・ドレイ
ン電極，１１・ゲート電極。1... Si single crystal substrate, 2... Non-doped SiC single crystal layer, 3... B ion implantation layer, 4... Electrical insulation layer and channel layer (high resistance SiC single crystal layer), 5... Filled insulation Film, 6... Source region, 7/ Drain region 8
...Gate insulating film, 9.. Source electrode, 10.. Drain electrode, 11. Gate electrode.
Claims (1)
装置であって、 該電気絶縁層およびチャネル層が単一の高抵抗炭化珪素
単結晶層から構成され、該高抵抗炭化珪素単結晶層が、
半導体基板上に成長させた炭化珪素単結晶層に所定量の
イオンを注入して、その表面領域にイオン注入層を形成
し、該イオン注入層を熱アニール処理することにより形
成される、炭化珪素半導体装置。[Claims] 1. A silicon carbide semiconductor device having an electrically insulating layer and a channel layer, wherein the electrically insulating layer and the channel layer are composed of a single high-resistance silicon carbide single crystal layer, and the high-resistance The silicon carbide single crystal layer is
Silicon carbide is formed by implanting a predetermined amount of ions into a silicon carbide single crystal layer grown on a semiconductor substrate, forming an ion implantation layer on the surface region, and thermally annealing the ion implantation layer. Semiconductor equipment.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1111400A JPH02291123A (en) | 1989-04-28 | 1989-04-28 | Silicon carbide semiconductor device |
| DE4009837A DE4009837A1 (en) | 1989-03-27 | 1990-03-27 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE |
| US07/499,889 US5135885A (en) | 1989-03-27 | 1990-03-27 | Method of manufacturing silicon carbide fets |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1111400A JPH02291123A (en) | 1989-04-28 | 1989-04-28 | Silicon carbide semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02291123A true JPH02291123A (en) | 1990-11-30 |
Family
ID=14560193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1111400A Pending JPH02291123A (en) | 1989-03-27 | 1989-04-28 | Silicon carbide semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02291123A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5326991A (en) * | 1991-09-24 | 1994-07-05 | Rohm Co., Ltd. | Semiconductor device having silicon carbide grown layer on insulating layer and MOS device |
| US5384270A (en) * | 1992-11-12 | 1995-01-24 | Fuji Electric Co., Ltd. | Method of producing silicon carbide MOSFET |
| US5610411A (en) * | 1991-09-24 | 1997-03-11 | Rohm Co., Ltd. | Silicon carbide bipolar semiconductor device with birdsbeak isolation structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60142568A (en) * | 1983-12-29 | 1985-07-27 | Sharp Corp | Manufacture of sic field effect transistor |
-
1989
- 1989-04-28 JP JP1111400A patent/JPH02291123A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60142568A (en) * | 1983-12-29 | 1985-07-27 | Sharp Corp | Manufacture of sic field effect transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5326991A (en) * | 1991-09-24 | 1994-07-05 | Rohm Co., Ltd. | Semiconductor device having silicon carbide grown layer on insulating layer and MOS device |
| US5518953A (en) * | 1991-09-24 | 1996-05-21 | Rohm Co., Ltd. | Method for manufacturing semiconductor device having grown layer on insulating layer |
| US5610411A (en) * | 1991-09-24 | 1997-03-11 | Rohm Co., Ltd. | Silicon carbide bipolar semiconductor device with birdsbeak isolation structure |
| US5384270A (en) * | 1992-11-12 | 1995-01-24 | Fuji Electric Co., Ltd. | Method of producing silicon carbide MOSFET |
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