JPH04217343A - Semiconductor device and fabrication thereof - Google Patents
Semiconductor device and fabrication thereofInfo
- Publication number
- JPH04217343A JPH04217343A JP40364190A JP40364190A JPH04217343A JP H04217343 A JPH04217343 A JP H04217343A JP 40364190 A JP40364190 A JP 40364190A JP 40364190 A JP40364190 A JP 40364190A JP H04217343 A JPH04217343 A JP H04217343A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- trench
- collector
- oxide film
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000012212 insulator Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 239000011810 insulating material Substances 0.000 abstract description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 238000001459 lithography Methods 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、半導体装置およびそ
の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same.
【０００２】0002
【従来の技術】近年、半導体装置の微細化・高密度化・
寄生容量の低減化を図るために溝充填分離および選択酸
化分離を併用する方法が用いられている。以下、図２を
参照しながら従来技術について説明する。図２は従来の
半導体装置の断面図である。[Background Art] In recent years, semiconductor devices have become smaller, more densely packed, and
In order to reduce parasitic capacitance, a method is used in which trench filling isolation and selective oxidation isolation are used together. The prior art will be described below with reference to FIG. FIG. 2 is a cross-sectional view of a conventional semiconductor device.
【０００３】この従来の半導体装置の製造方法は、Ｐ型
シリコン基板１に高濃度Ｎ型埋込み層２とＮ型エピタキ
シャル層３を形成した後、酸化膜をマスクとして異方性
ドライエッチング技術によりＰ型シリコン基板１に達す
る深さの溝４を形成する。次に、溝４内のダメージ層除
去を目的とした犠牲酸化およびチャンネルストッパ層５
の形成を行った後、溝４を絶縁物６で埋込み、表面を平
坦化する。次に、配線寄生容量低減を目的として不活性
なフィールド部を選択酸化し、さらにベース・コレクタ
間容量低減を目的としてベース７・コレクタ８間を選択
酸化し、それぞれ選択酸化膜９，１０を形成する。なお
、ベース７，コレクタ８，エミッタ１１の形成は選択酸
化膜９，１０の形成後に行う。This conventional method for manufacturing a semiconductor device involves forming a heavily doped N-type buried layer 2 and an N-type epitaxial layer 3 on a P-type silicon substrate 1, and then using an oxide film as a mask to remove P by anisotropic dry etching technology. A groove 4 having a depth reaching the mold silicon substrate 1 is formed. Next, sacrificial oxidation and channel stopper layer 5 are performed for the purpose of removing the damaged layer in trench 4.
After forming the grooves 4, the grooves 4 are filled with an insulator 6, and the surface is planarized. Next, the inactive field part is selectively oxidized for the purpose of reducing wiring parasitic capacitance, and the area between the base 7 and the collector 8 is selectively oxidized for the purpose of reducing the base-collector capacitance, forming selective oxide films 9 and 10, respectively. do. Note that the base 7, collector 8, and emitter 11 are formed after the selective oxide films 9 and 10 are formed.
【０００４】0004
【発明が解決しようとする課題】しかしながら上記従来
の構成および方法では、選択酸化膜９，１０の形成時に
生じるバーズビーク９ａ，１０ａの存在により、また、
バーズビーク９ａ，１０ａの近傍は応力が大きいことに
より、微細化の点で限界がある。この発明の目的は、よ
り寄生容量の低減を実現できるとともに、より微細化・
高密度化を達成することのできる半導体装置およびその
製造方法を提供することである。However, in the conventional structure and method described above, due to the presence of bird's beaks 9a and 10a that occur when forming the selective oxide films 9 and 10,
There is a limit to miniaturization due to the large stress in the vicinity of the bird's beaks 9a and 10a. The purpose of this invention is to achieve further reduction in parasitic capacitance, as well as further miniaturization and
An object of the present invention is to provide a semiconductor device that can achieve high density and a method for manufacturing the same.
【０００５】[0005]
【課題を解決するための手段】請求項１記載の半導体装
置は、一導電型の半導体基板上に形成されるトランジス
タの活性領域周辺に形成した第１の溝と、この第１の溝
の底面に一導電型の不純物をイオン注入して形成したチ
ャンネルストッパ層と、第１の溝の内面に形成した酸化
膜および内部に充填した絶縁物と、トランジスタの不活
性領域およびトランジスタのベース・コレクタ間に形成
した第２および第３の溝と、この第２および第３の溝の
溝の内面に形成した酸化膜および内部に充填した絶縁物
とを備えている。A semiconductor device according to claim 1 includes a first trench formed around an active region of a transistor formed on a semiconductor substrate of one conductivity type, and a bottom surface of the first trench. A channel stopper layer formed by ion-implanting an impurity of one conductivity type into the first trench, an oxide film formed on the inner surface of the first trench and an insulator filled inside, an inactive region of the transistor, and a region between the base and collector of the transistor. The semiconductor device includes second and third grooves formed in the grooves, an oxide film formed on the inner surfaces of the second and third grooves, and an insulator filled inside the grooves.
【０００６】請求項２記載の半導体装置の製造方法は、
一導電型の半導体基板上に形成されるトランジスタの活
性領域周辺にドライエッチング技術により第１の溝を形
成し、この第１の溝の底面に一導電型の不純物をイオン
注入し、第１の溝内に酸化膜を形成し絶縁物を埋め込む
。さらに、トランジスタの不活性領域およびトランジス
タのベース・コレクタ間にドライエッチング技術により
同時に第２および第３の溝を形成し、この第２および第
３の溝内を酸化し絶縁物を埋め込み、表面を平坦化する
ものである。The method for manufacturing a semiconductor device according to claim 2 comprises:
A first groove is formed by dry etching technology around the active region of a transistor formed on a semiconductor substrate of one conductivity type, and impurities of one conductivity type are ion-implanted into the bottom of the first groove. An oxide film is formed in the trench and an insulator is filled in. Furthermore, second and third trenches are simultaneously formed in the inactive region of the transistor and between the base and collector of the transistor by dry etching technology, and the insides of the second and third trenches are oxidized and filled with an insulator to improve the surface. It flattens the surface.
【０００７】[0007]
【作用】この発明の構成によれば、トランジスタの活性
領域周辺に第１の溝を形成し、この第１の溝内に酸化膜
を形成し絶縁物を埋め込むことにより、コレクタ・基板
間容量が低減される。さらに、トランジスタの不活性領
域およびトランジスタのベース・コレクタ間に第２およ
び第３の溝を形成し、この第２および第３の溝内を酸化
し絶縁物を埋め込むことにより、配線容量およびベース
・コレクタ間容量が低減されるとともに、微細化・高密
度化が可能となる。[Operation] According to the structure of the present invention, a first trench is formed around the active region of the transistor, an oxide film is formed in the first trench, and an insulating material is buried, thereby reducing the collector-substrate capacitance. reduced. Furthermore, by forming second and third trenches in the inactive region of the transistor and between the base and collector of the transistor, and oxidizing the second and third trenches and filling them with an insulator, wiring capacitance and base The inter-collector capacitance is reduced, and miniaturization and higher density are possible.
【０００８】[0008]
【実施例】以下、この発明の一実施例について図面を参
照しながら説明する。図１（ａ） 〜（ｆ） はこの発
明による半導体装置の製造方法を示す工程断面図である
。まず、Ｐ型（１１１）１０〜２０Ω−ｃｍのシリコン
基板１に深さ２μｍの高濃度Ｎ型埋込み層２と厚さ １
．３μｍのＮ型エピタキシャル層３を形成した後、酸化
膜１２を表面に形成し、リソグラフィによりパターニン
グを行い、酸化膜１２をマスクとして異方性ドライエッ
チング技術により、Ｐ型シリコン基板１に達する深さの
第１の溝４を形成する（図１（ａ） ）。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIGS. 1(a) to 1(f) are process cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention. First, a P-type (111) 10 to 20 Ω-cm silicon substrate 1 is coated with a high concentration N-type buried layer 2 having a depth of 2 μm and a thickness of 1 μm.
．． After forming an N-type epitaxial layer 3 of 3 μm, an oxide film 12 is formed on the surface, patterned by lithography, and anisotropic dry etching technique is applied using the oxide film 12 as a mask to a depth that reaches the P-type silicon substrate 1. A first groove 4 is formed (FIG. 1(a)).
【０００９】つぎに、第１の溝４内のダメージ層除去を
目的とした犠牲酸化を行い、Ｂ＋ イオン注入によりチ
ャンネルストッパ層５を形成する。その後、酸化膜１２
および犠牲酸化膜をＨＦ系溶液で全面除去し、再び第１
の溝４内に酸化膜１３を形成する（図１（ｂ） ）。つ
ぎに、第１の溝４を絶縁物であるＢＰＳＧ（Ｂｏｒｏ−
Ｐｈｏｓｐｈｏ−Ｓｉｌｉｃａｔｅ Ｇｌａｓｓ）１４
で埋込み、リフローを行う。その後、ＢＰＳＧ１４をリ
ソグラフィによりパターニングを行う（図１（ｃ） ）
。Next, sacrificial oxidation is performed for the purpose of removing the damaged layer within the first trench 4, and a channel stopper layer 5 is formed by B+ ion implantation. After that, the oxide film 12
Then, the sacrificial oxide film is completely removed using an HF solution, and the first
An oxide film 13 is formed in the groove 4 (FIG. 1(b)). Next, the first groove 4 is made of BPSG (Boro-
Phospho-Silicate Glass)14
Embed and reflow. After that, BPSG14 is patterned by lithography (Figure 1(c))
.
【００１０】つぎに、パターニングしたＢＰＳＧ１４を
マスクとして、異方性ドライエッチング技術により、不
活性フィールド部およびベース・コレクタ間に、第２の
溝１５および第３の溝１６を同時に形成する（図１（ｄ
） ）。つぎに、第２の溝１５および第３の溝１６のダ
メージ層除去を目的とした犠牲酸化を行い酸化膜１７を
形成した後、第２の溝１５および第３の溝１６を絶縁物
であるＢＰＳＧ１８で埋込み、リフローを行う（図１（
ｅ） ）。Next, using the patterned BPSG 14 as a mask, a second groove 15 and a third groove 16 are simultaneously formed in the inactive field portion and between the base and collector by anisotropic dry etching technology (see FIG. (d
) ). Next, after performing sacrificial oxidation for the purpose of removing the damaged layer in the second groove 15 and the third groove 16 and forming an oxide film 17, the second groove 15 and the third groove 16 are made of an insulating material. Embed with BPSG18 and reflow (Figure 1 (
e) ).
【００１１】つぎに、エッチバックにより表面を平坦化
する。その後、ベース７，コレクタ８，エミッタ１１を
形成する（図１（ｆ） ）。この実施例によれば、分離
領域幅はリソグラフィにのみ依存し、より微細化・高密
度化が可能となる。また、第１の溝４によりコレクタ８
・基板１間容量を低減でき、第２の溝１５により配線容
量を低減でき、第３の溝１６によりベース７・コレクタ
８間容量を低減できる。Next, the surface is planarized by etchback. Thereafter, the base 7, collector 8, and emitter 11 are formed (FIG. 1(f)). According to this embodiment, the separation region width depends only on lithography, and further miniaturization and higher density are possible. Also, the first groove 4 allows the collector 8 to
- The capacitance between the substrate 1 can be reduced, the wiring capacitance can be reduced by the second groove 15, and the capacitance between the base 7 and the collector 8 can be reduced by the third groove 16.
【００１２】また、第１の溝４，第２の溝１５および第
３の溝１６内に酸化膜１３，１７を形成することにより
、埋込み絶縁物であるＢＰＳＧ１４，１８がＰ型シリコ
ン基板１と直接接することがないため、ＢＰＳＧ１４，
１８からＰ型シリコン基板１へのボロンや燐の拡散を防
ぐことができ、信頼性も向上する。なお上記実施例では
、溝４，１５，１６の充填絶縁物としてＢＰＳＧ１４，
１８を用いリフローを行ったが、ＳＯＧ（Ｓｐｉｎ ｏ
ｎ Ｇｌａｓｓ ）を用いてもよい。またこの場合でも
溝４，１５，１６内に酸化膜１３，１７を形成すること
により、ＳＯＧからＰ型シリコン基板１への水分の侵入
を防ぐことができ、信頼性も向上する。Furthermore, by forming oxide films 13 and 17 in the first trench 4, second trench 15, and third trench 16, the BPSGs 14 and 18, which are buried insulators, are connected to the P-type silicon substrate 1. Since there is no direct contact, BPSG14,
Diffusion of boron and phosphorus from 18 to P-type silicon substrate 1 can be prevented, and reliability is also improved. Note that in the above embodiment, BPSG14,
18 was used for reflow, but SOG (Spin o
n Glass) may be used. Also in this case, by forming the oxide films 13, 17 in the grooves 4, 15, 16, it is possible to prevent moisture from entering the P-type silicon substrate 1 from the SOG, and reliability is also improved.
【００１３】[0013]
【発明の効果】この発明の半導体装置およびその製造方
法は、トランジスタの活性領域周辺に第１の溝を形成し
、この第１の溝内に酸化膜を形成し絶縁物を埋め込むこ
とにより、コレクタ・基板間容量が低減される。さらに
、トランジスタの不活性領域およびトランジスタのベー
ス・コレクタ間に第２および第３の溝を形成し、この第
２および第３の溝内を酸化し絶縁物を埋め込むことによ
り、配線容量およびベース・コレクタ間容量が低減され
るとともに、微細化・高密度化が可能となる。Effects of the Invention The semiconductor device and the method for manufacturing the same of the present invention form a first trench around the active region of a transistor, form an oxide film in the first trench, and fill it with an insulator.・Capacitance between boards is reduced. Furthermore, by forming second and third trenches in the inactive region of the transistor and between the base and collector of the transistor, and oxidizing the second and third trenches and filling them with an insulator, wiring capacitance and base The inter-collector capacitance is reduced, and miniaturization and higher density are possible.
【００１４】このように各寄生容量の低減化および微細
化・高密度化が図れることにより、高周波特性，低消費
電力特性が向上する。[0014] By reducing each parasitic capacitance and achieving miniaturization and high density in this manner, high frequency characteristics and low power consumption characteristics are improved.
【図１】この発明による半導体装置の製造方法を示す工
程断面図である。FIG. 1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to the present invention.
【図２】従来の半導体装置の断面図である。FIG. 2 is a cross-sectional view of a conventional semiconductor device.
１ Ｐ型シリコン基板
４ 第１の溝
５ チャンネルストッパ層
１３，１７ 酸化膜
１４，１８ ＢＰＳＧ（絶縁物）１５ 第
２の溝
１６ 第３の溝1 P-type silicon substrate 4 First groove 5 Channel stopper layer 13, 17 Oxide film 14, 18 BPSG (insulator) 15 Second groove 16 Third groove
Claims (2)
トランジスタの活性領域周辺に形成した第１の溝と、こ
の第１の溝の底面に一導電型の不純物をイオン注入して
形成したチャンネルストッパ層と、前記第１の溝の内面
に形成した酸化膜および内部に充填した絶縁物と、前記
トランジスタの不活性領域および前記トランジスタのベ
ース・コレクタ間に形成した第２および第３の溝と、こ
の第２および第３の溝の内面に形成した酸化膜および内
部に充填した絶縁物とを備えた半導体装置。Claim 1: A first groove formed around an active region of a transistor formed on a semiconductor substrate of one conductivity type, and an impurity of one conductivity type formed by ion implantation into the bottom surface of the first groove. a channel stopper layer, an oxide film formed on the inner surface of the first trench and an insulator filled therein, an inactive region of the transistor, and second and third trenches formed between the base and collector of the transistor. A semiconductor device comprising: an oxide film formed on the inner surfaces of the second and third grooves and an insulator filled therein.
トランジスタの活性領域周辺にドライエッチング技術に
より第１の溝を形成する工程と、この第１の溝の底面に
一導電型の不純物をイオン注入する工程と、前記第１の
溝内に酸化膜を形成し絶縁物を埋め込む工程と、前記ト
ランジスタの不活性領域および前記トランジスタのベー
ス・コレクタ間にドライエッチング技術により同時に第
２および第３の溝を形成する工程と、この第２および第
３の溝内を酸化し絶縁物を埋め込む工程と、表面を平坦
化する工程とを含む半導体装置の製造方法。2. A step of forming a first groove by dry etching technology around the active region of a transistor formed on a semiconductor substrate of one conductivity type, and adding impurities of one conductivity type to the bottom surface of the first groove. A step of implanting ions, a step of forming an oxide film in the first trench and burying an insulator, and a step of simultaneously forming second and third trenches by dry etching between the inactive region of the transistor and the base-collector of the transistor. A method for manufacturing a semiconductor device, comprising the steps of: forming a trench; oxidizing and filling the second and third trenches with an insulator; and flattening the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40364190A JPH04217343A (en) | 1990-12-19 | 1990-12-19 | Semiconductor device and fabrication thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40364190A JPH04217343A (en) | 1990-12-19 | 1990-12-19 | Semiconductor device and fabrication thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04217343A true JPH04217343A (en) | 1992-08-07 |
Family
ID=18513368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP40364190A Pending JPH04217343A (en) | 1990-12-19 | 1990-12-19 | Semiconductor device and fabrication thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04217343A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100393199B1 (en) * | 2001-01-15 | 2003-07-31 | 페어차일드코리아반도체 주식회사 | High voltage semiconductor device having high breakdown voltage and method for fabricating the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5943546A (en) * | 1982-09-06 | 1984-03-10 | Hitachi Ltd | Semiconductor ic device and its manufacture |
| JPS59147445A (en) * | 1983-02-10 | 1984-08-23 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS59215741A (en) * | 1983-05-24 | 1984-12-05 | Mitsubishi Electric Corp | Manufacture of semiconductor integrated circuit device |
| JPS6489337A (en) * | 1987-09-29 | 1989-04-03 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
1990
- 1990-12-19 JP JP40364190A patent/JPH04217343A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5943546A (en) * | 1982-09-06 | 1984-03-10 | Hitachi Ltd | Semiconductor ic device and its manufacture |
| JPS59147445A (en) * | 1983-02-10 | 1984-08-23 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS59215741A (en) * | 1983-05-24 | 1984-12-05 | Mitsubishi Electric Corp | Manufacture of semiconductor integrated circuit device |
| JPS6489337A (en) * | 1987-09-29 | 1989-04-03 | Toshiba Corp | Semiconductor device and manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100393199B1 (en) * | 2001-01-15 | 2003-07-31 | 페어차일드코리아반도체 주식회사 | High voltage semiconductor device having high breakdown voltage and method for fabricating the same |
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