JPH03203225A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH03203225A JPH03203225A JP34058289A JP34058289A JPH03203225A JP H03203225 A JPH03203225 A JP H03203225A JP 34058289 A JP34058289 A JP 34058289A JP 34058289 A JP34058289 A JP 34058289A JP H03203225 A JPH03203225 A JP H03203225A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- oxygen concentration
- layer
- compound semiconductor
- iii
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 69
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 41
- 239000001301 oxygen Substances 0.000 claims abstract description 41
- 150000001875 compounds Chemical class 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 10
- 239000012298 atmosphere Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 abstract description 4
- 125000005842 heteroatom Chemical group 0.000 abstract 2
- 238000011109 contamination Methods 0.000 description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000010348 incorporation Methods 0.000 description 2
- 101100215641 Aeromonas salmonicida ash3 gene Proteins 0.000 description 1
- 101100441878 Caenorhabditis elegans cyn-3 gene Proteins 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
本発明は、半導体装置およびその製造方法に関し、
Ｓｉ基板から■−Ｖ族化合物半導体へテロエピタキシャ
ル成長層中へのＳｉ混人を防止すると共に大口径化に十
分な基板の機械的強度を確保した半導体装置およびその
製造方法を提供することを目的とし、
本発明の半導体装置は、表面の酸素濃度が１×Ｉ Ｑ
＋’７Ｃ「３以下のＳｉ基板と、前記Ｓｉ基板の表面に
接して成長された■−Ｖ族化合物半導体層とを備えて構
成し、
本発明の半導体装置の製造方法は、Ｓｉ基板に対して不
活性雰囲気中で加熱処理を施し、表面の酸素濃度を１×
１０′″以下にせしめる工程と、前記Ｓｉ基板の表面に
■−■族化合物半導体を成長する工程とを含むように構
成する。[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor device and a method for manufacturing the same, which prevents Si contamination from a Si substrate into a heteroepitaxially grown layer of a ■-V group compound semiconductor, and facilitates an increase in diameter. An object of the present invention is to provide a semiconductor device in which a sufficient mechanical strength of the substrate is ensured, and a method for manufacturing the same.
The semiconductor device manufacturing method of the present invention comprises a Si substrate of 3 or less and a -V group compound semiconductor layer grown in contact with the surface of the Si substrate. heat treatment in an inert atmosphere to reduce the oxygen concentration on the surface to 1×
10'' or less, and a step of growing a ■-■ group compound semiconductor on the surface of the Si substrate.
本発明は、半導体装置およびその製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the same.
近年、ｍ−ｖ族化合物半導体を用いた集積回路の集積度
が向上し、それに伴ってチップサイズが大型化している
。このような集積回路の生産性を向上させるためには、
基板の大口径化が必要である。In recent years, the degree of integration of integrated circuits using m-v group compound semiconductors has improved, and the chip size has accordingly increased. In order to improve the productivity of such integrated circuits,
It is necessary to increase the diameter of the substrate.
■＝Ｖ族化合物半導体は大口径の単結晶インゴットを製
造することが困難であるため、大口径化が可能な８１基
板上に■−Ｖ族化合吻半導体をヘテロエピタキシャル成
長することにより大口径化を図っている。Since it is difficult to manufacture single crystal ingots with large diameters for ■=V group compound semiconductors, large diameters can be achieved by heteroepitaxially growing ■-V group compound semiconductors on 81 substrates that allow for larger diameters. I'm trying.
しかしながら、その際に基板のＳｔがへテロエピタキシ
ャル成長層中に拡散して混入する。■−■族化合物半導
体のへテロエピタキシャル成長層のＳｉ混入領域では、
Ｓｉがドナーとして作用して電気抵抗が低下するため、
ヘテロエピタキシャル成長層中に形成した素子とＳｉ基
板との間の電気的絶縁およびヘテロエピタキシャル成長
層中の素子間の電気的絶縁が不十分にな、って、素子特
性を劣化させる原因となっていた。However, at this time, St from the substrate diffuses into the heteroepitaxially grown layer. In the Si-containing region of the heteroepitaxial growth layer of the ■-■ group compound semiconductor,
Because Si acts as a donor and the electrical resistance decreases,
The electrical insulation between the elements formed in the heteroepitaxially grown layer and the Si substrate and the electrical insulation between the elements in the heteroepitaxially grown layer are insufficient, which causes deterioration of the element characteristics.
本発明は、８１基板から■−Ｖ族化合物半導体へテロエ
ピタキシャル成長層中へのＳｔ混人を防止すると共に大
口径化に十分な基板の機械的強度を確保した半導体装置
およびその製造方法を提供することを目的とする。The present invention provides a semiconductor device and a method for manufacturing the same, which prevents St contamination from an 81 substrate into a heteroepitaxial growth layer of a -V group compound semiconductor, and ensures sufficient mechanical strength of the substrate for increasing the diameter. The purpose is to
上記の目的は、本発明によれば、表面の酸素濃度がＩ
Ｘ １０ ”ｃｍ−″以下のＳｉ基板と、前記Ｓｉ基板
の表面に接して成長された■−Ｖ族化合物半導体層とを
備えることを特徴とする半導体装置、またはＳｉ基板に
対して不活性雰囲気中で加熱処理を施し、表面の酸素濃
度をｌＸｌ０”以下にせしめる工程と、前記Ｓｉ基板の
表面に■−■族化（３）
（４）
合物半導体を成長する工程とを含むことを特徴とする半
導体装置の製造方法によって達成される。According to the present invention, the above object is achieved by reducing the surface oxygen concentration to
A semiconductor device characterized by comprising a Si substrate of X 10 "cm-" or less and a ■-V group compound semiconductor layer grown in contact with the surface of the Si substrate, or an inert atmosphere for the Si substrate. The method is characterized by comprising a step of performing heat treatment in the Si substrate to reduce the oxygen concentration on the surface to 1Xl0'' or less, and a step of growing a ■-■ group compound semiconductor (3) (4) on the surface of the Si substrate. This is achieved by a method of manufacturing a semiconductor device.
本発明者が種々の実験を行った結果、表面の酸素濃度が
Ｉ Ｘ １０ ”ｃｍ−３以下のＳｉの表面に■Ｖ族化
合物半導体を成長した場合は、ヘテロエピタキシャル成
長した■−Ｖ族化合物半導体中へのＳＮの混入が抑制で
きることが判明した。As a result of various experiments conducted by the present inventors, it has been found that when a ■-V group compound semiconductor is grown on the surface of Si with a surface oxygen concentration of I x 10 ''cm-3 or less, a ■-V group compound semiconductor grown heteroepitaxially. It was found that the contamination of SN into the inside could be suppressed.
本発明は、この知見を基に槽底されている。The present invention is based on this knowledge.
また、Ｓｉ基板全体の酸素濃度を低下させるためには、
いわゆるフローティングゾーン法によって作製する必要
があり、コスト高となるばかりか、機械的強度が低下す
る恐れもある。In addition, in order to reduce the oxygen concentration of the entire Si substrate,
It is necessary to manufacture by a so-called floating zone method, which not only increases the cost but also may reduce mechanical strength.
しかし、本発明者は、ヘテロエピタキシャル成長層中へ
のＳｔ混入を防止するには、Ｓｉ基板全体の酸素濃度を
低下させる必要はなく、成長を行う基板表面の酸素濃度
を低下させれば十分であること、また表面の酸素濃度を
低下させても内部の酸素濃度を低下させずに維持してお
けば基板の機械的強度を確保できることを見出した。However, the present inventor believes that in order to prevent St incorporation into the heteroepitaxial growth layer, it is not necessary to reduce the oxygen concentration of the entire Si substrate, but it is sufficient to reduce the oxygen concentration of the surface of the substrate where the growth is performed. In addition, it has been found that even if the surface oxygen concentration is reduced, the mechanical strength of the substrate can be ensured by maintaining the internal oxygen concentration without reducing it.
エピタキシャル成長した■−Ｖ族化合物半導体層中への
Ｓｔ混人を、素子特性を確保するのに十分な程度まで防
止するには、エピタキシャル成長を行うＳｉ基板表面の
酸素濃度が１０”ｃｙｎ−３以下であることが必要であ
る。Ｓｉ基板表面のＳｉ濃度は、できるだけ低いこと望
ましく、１０１６ＣＩ１１−３以下とすることが望まし
い。In order to prevent St incorporation into the epitaxially grown ■-V group compound semiconductor layer to a sufficient extent to ensure device characteristics, the oxygen concentration on the surface of the Si substrate on which epitaxial growth is performed must be 10" cyn-3 or less. The Si concentration on the surface of the Si substrate is desirably as low as possible, preferably 1016 CI11-3 or less.
Ｓｉ基板内部の酸素濃度は、基板口径に応じて十分な機
械的強度が確保される濃度とすることができる。The oxygen concentration inside the Si substrate can be set to a concentration that ensures sufficient mechanical strength depending on the diameter of the substrate.
第１図に、種々の表面酸素濃度のＳｉ基板上に■−Ｖ族
化合物半導体としてＧａＡｓを有機金属化学気相成長法
（ＭＯＣＶＤ法）によりヘテロエピタキシャル成長させ
た場合の、基板／成長層界面付近のＳｔ濃度分布を示す
。いずれの場合も、基板表面の深さ１５μｍ程度までを
図中に表示した酸素濃度とし、基板内部の酸素濃度はＩ
Ｑ １８ ｃｍ −３である。基板表面酸素濃度Ｉ
Ｑ Ｉ ｓ Ｃｍ −３同図中の曲線１）ではＧａＡｓ
層側の１μｍ程度までＳＮ混（５）
（６）
人が認められるが、基板表面酸素濃度が１０１７ｃｙｎ
−３以下（同図中の曲線２および３）になるとＳｉ混入
が著しく低減され、実質的に素子特性に影響するＳｉ混
入は防止されている。また、基板内部酸素濃度が１０１
８ｃｍ−３程度であれば、Ｓｉ基板の機械的強度は十分
に確保される。Figure 1 shows the area near the substrate/growth layer interface when GaAs is heteroepitaxially grown as a ■-V group compound semiconductor by metal organic chemical vapor deposition (MOCVD) on Si substrates with various surface oxygen concentrations. The St concentration distribution is shown. In either case, the oxygen concentration shown in the figure is up to a depth of about 15 μm on the substrate surface, and the oxygen concentration inside the substrate is I
Q 18 cm −3. Substrate surface oxygen concentration I
Q I s Cm -3 In curve 1) in the same figure, GaAs
SN mixture (5) (6) is observed up to about 1 μm on the layer side, but the oxygen concentration on the substrate surface is 1017 cyn.
-3 or less (curves 2 and 3 in the figure), Si contamination is significantly reduced, and Si contamination that would affect device characteristics is substantially prevented. In addition, the oxygen concentration inside the substrate is 101
If it is about 8 cm-3, the mechanical strength of the Si substrate is sufficiently ensured.
本発明においては、Ｓｉ基板の表面をＢ１７０ｍ−３以
下の低酸素濃度とすることによりヘテロエピタキシャル
成長層中へのＳｉ混入を防止し、且つ基板内部の酸素濃
度を適宜選択できることにより十分な機械的強度を確保
する。In the present invention, the surface of the Si substrate has a low oxygen concentration of B170m-3 or less to prevent Si from entering the heteroepitaxial growth layer, and the oxygen concentration inside the substrate can be appropriately selected to provide sufficient mechanical strength. ensure that
以下に、実施例により本発明をより詳細に説明する。EXAMPLES Below, the present invention will be explained in more detail with reference to Examples.
〔実施例１］ 第２図（ａ）は、本実施例の構成を示している。[Example 1] FIG. 2(a) shows the configuration of this embodiment.
まず、Ｓｉ基板１表面の酸素濃度を低下させる処理とし
て、Ｓｉ基板１を通常の酸化炉内に装入し、温度１１０
０°ｃ、Ｎ２雰囲気中で３０〜６０分間加熱した。この
加熱処理によって形成されたＳｉ基板表面（深さ１０〜
３０μｍまで）の低酸素濃度領域２の酸素濃度は１０１
１０ｌ６”であった。First, as a treatment to reduce the oxygen concentration on the surface of the Si substrate 1, the Si substrate 1 is placed in a normal oxidation furnace, and the temperature is 110.
Heated at 0°C for 30-60 minutes in a N2 atmosphere. The Si substrate surface formed by this heat treatment (depth 10~
The oxygen concentration in the low oxygen concentration region 2 (up to 30 μm) is 101
It was 10l6”.
この低酸素濃度領域２上に、Ｍ、Ａｋｉｙａｍａ、 Ｙ
、Ｋａｗａｒａｄａ、 ａｎｄ Ｋ、Ｋａｗａｎｉｓｉ
：Ｊｐｎ、 Ｊ、＾ｐｐ１． Ｐｈｙｓ。On this low oxygen concentration area 2, M, Akiyama, Y
, Kawarada, and K. Kawanisi
: Jpn, J, ^pp1. Phys.
ｖｏｌ、２３ Ｌ８４３ （１９８４）に記載されてい
る減圧ＭＯＣＶＤ法による二段階成長法を用いて、Ｇａ
Ａｓ層３をヘテロエピタキシャル成長させた。ＧａＡｓ
層３の原料としては、ＡＳＨ３およびＴＭＧ （）リメ
チルガリウム）を用いた。全成長過程を通して、反応管
内の圧力を７０Ｔｏｒｒとした。手順は以下の通りであ
った。vol. 23 L843 (1984), Ga
The As layer 3 was grown heteroepitaxially. GaAs
As raw materials for layer 3, ASH3 and TMG ()limethylgallium) were used. The pressure inside the reaction tube was maintained at 70 Torr throughout the entire growth process. The procedure was as follows.
前記加熱処理済みのＳｉ基板をＨＦ水溶液中で洗浄処理
し、水洗した後、反応管内のサセプターに装入した。反
応管内にＮ２およびＡ ｓ Ｉ−１３をそれぞれ１２Ｓ
ＬＭおよび３０ＳＣＣＭの流量で導入し、基板を１００
０″Ｃに１０分間加熱した。次に、Ｎ２およびＡ ｓ
Ｈ３の流量をそれぞれ１２ＳＬＭおよび０．２ＳＬＭと
し、ＴＭＧを１３．３３ＣＣＭの流量で導入し、基板温
度を４５０°Ｃにして、先ず、下地となるアモルファス
状のＧａＡｓ層（７）
（８）
（図示せず）を５０〜２００人の厚さに成長させた。そ
の後、基板温度を６００〜７００°Ｃに上げて、Ｎ２、
ＡｓＨ＋、およびＴＭＧの流量をそれぞれ１２ＳＬＭ、
Ｏ，ＩＳＬＭ、および３３．３３ＣＣＭとして、ＧａＡ
ｓ層３を２〜３μｍ成長させた。The heat-treated Si substrate was washed in an HF aqueous solution, washed with water, and then placed in a susceptor in a reaction tube. Inject 12S of N2 and As I-13 into the reaction tube.
LM and a flow rate of 30 SCCM, the substrate was
Heated to 0″C for 10 minutes. Then N2 and A s
The H3 flow rate was set to 12SLM and 0.2SLM, respectively, TMG was introduced at a flow rate of 13.33CCM, and the substrate temperature was set to 450°C. First, an amorphous GaAs layer (7) (8) (Fig. (not shown) were grown to a thickness of 50 to 200 people. After that, the substrate temperature was raised to 600-700°C, and N2,
The flow rates of AsH+ and TMG were each 12SLM,
GaA as O, ISLM, and 33.33CCM
The s-layer 3 was grown to a thickness of 2 to 3 μm.
基板／ Ｇ ａ Ａ ｓ層へテロ界面付近のＳｉ濃度分
布は第１図の曲線３と同様であり、実質的に素子特性に
影響するＳｉ混入は防止されていた。The Si concentration distribution near the substrate/GaAs layer heterointerface was similar to curve 3 in FIG. 1, and Si contamination that would substantially affect device characteristics was prevented.
〔実施例２〕 第２図（ｂ）は、本実施例を説明する図である。[Example 2] FIG. 2(b) is a diagram illustrating this embodiment.
まず、表面酸素濃度の低いＳｉ基板を得る別の手段とし
て、酸素濃度１０ ” 〜１０ ”ｃｍ−”のＳｉ基板
１上に、下記の２段階の手順で低酸素濃度Ｓｉ層４をエ
ピタキシャル成長させた。第１段階として、上記Ｓｉ基
板を流量１０１！、／ｌｌ１ｉｎのＮ２気流中で１００
０“Ｃに加熱して２０分間保持することにより、基板表
面のＳｉ２０層を除去した。第２段階として、Ｎ２およ
びＳｉＨ，をそれぞれ１０ｆｆｉ／ＩｎＩｎおよび１０
０ ｃ ｃ／ｍｉｎの流量で流し、基板を１０００ ’
Ｃに加熱して１〜３．３時間保持することにより、Ｓｉ
基板上に低酸素濃度３４層４を厚さ３〜１０μｍにエピ
タキシャル成長させた。First, as another means of obtaining a Si substrate with a low surface oxygen concentration, a low oxygen concentration Si layer 4 was epitaxially grown on a Si substrate 1 with an oxygen concentration of 10'' to 10'' cm by the following two-step procedure. As a first step, the above Si substrate was heated in a N2 air flow of 101!,/ll1in.
The Si20 layer on the substrate surface was removed by heating to 0"C and holding for 20 minutes. In the second step, N2 and SiH were heated to 10ffi/InIn and 10
The flow rate was 0 c c/min, and the substrate was
By heating to C and holding for 1 to 3.3 hours, Si
A low oxygen concentration 34 layer 4 was epitaxially grown to a thickness of 3 to 10 μm on the substrate.
表面酸素濃度は１０１６ｃｍ−３であった。The surface oxygen concentration was 1016 cm-3.
次に、このＳｉ基板を用いて、上記低酸素濃度Ｓｉ層４
上に、実施例１と同様の手順でＧ ａ Ａ、 ｓ層３を
ヘテロエピタキシャル成長させた。Next, using this Si substrate, the low oxygen concentration Si layer 4
A Ga A, s layer 3 was heteroepitaxially grown thereon in the same manner as in Example 1.
低酸素濃度３４層４ ／ Ｇ ａ Ａ ｓ層３ヘテロ界
面付近のＳｉ濃度分布は第１図の曲線３と同様であり、
実質的に素子特性に影響するＳｉ混入は防止されていた
。The Si concentration distribution near the low oxygen concentration 34 layer 4/GaAs layer 3 heterointerface is similar to curve 3 in FIG.
The contamination of Si, which would substantially affect the device characteristics, was prevented.
以上説明したように、本発明によれば、Ｓｉ基板から■
−Ｖ族化合物半導体へテロエピタキシャル成長層中への
Ｓｉ混入を防止すると共に大口径化に十分な基板の機械
的強度を確保して■−■族化合物半導体をエピタキシャ
ル成長させることができる。As explained above, according to the present invention, from the Si substrate
It is possible to epitaxially grow a -V group compound semiconductor while preventing Si from being mixed into the heteroepitaxially grown layer of the -V group compound semiconductor and ensuring sufficient mechanical strength of the substrate for increasing the diameter.
（９） （１０）(9) (10)
第１図は、種々の表面酸素濃度のＳｉ基板につイテ、Ｇ
ａＡｓヘテロエピタキシャル成長層とＳｉ基板との界面
付近のＳｔ濃度分布を示すグラフ、および
第２図（ａ）および（ｂ）は、本発明の詳細な説明する
ための断面図である。
１ ：Ｓｉ基板、２：低酸素濃度領域、３：ＧａＡ、ｓ
層、４：低酸素濃度Ｓｉ層。Figure 1 shows Si substrates with various surface oxygen concentrations, G
A graph showing the St concentration distribution near the interface between the aAs heteroepitaxial growth layer and the Si substrate, and FIGS. 2(a) and 2(b) are cross-sectional views for explaining the present invention in detail. 1: Si substrate, 2: low oxygen concentration region, 3: GaA, s
Layer 4: Low oxygen concentration Si layer.
Claims (1)
下のＳｉ基板と、前記Ｓｉ基板の表面に接して成長され
たIII−Ｖ族化合物半導体層とを備えることを特徴とす
る半導体装置。 ２、前記Ｓｉ基板の表面は、エピタキシャル成長された
酸素濃度が１×１０＾１＾７ｃｍ＾−＾３以下のＳｉ層
で構成されることを特徴とする請求項１記載の半導体装
置。 ３、前記Ｓｉ基板の内部の酸素濃度は、１×１０＾１＾
７ｃｍ＾−＾３以上であることを特徴とする請求項１ま
たは２に記載の半導体装置。 ４、Ｓｉ基板に対して不活性雰囲気中で加熱処理を施し
、表面の酸素濃度を１×１０＾１＾７以下にせしめる工
程と、前記Ｓｉ基板の表面にIII−Ｖ族化合物半導体を
成長する工程とを含むことを特徴とする半導体装置の製
造方法。[Claims] 1. A Si substrate with a surface oxygen concentration of 1×10^1^7 cm^-^3 or less, and a III-V compound semiconductor layer grown in contact with the surface of the Si substrate. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the surface of the Si substrate is composed of an epitaxially grown Si layer having an oxygen concentration of 1×10^1^7 cm^-^3 or less. 3. The oxygen concentration inside the Si substrate is 1×10^1^
3. The semiconductor device according to claim 1, wherein the semiconductor device is 7 cm^-^3 or more. 4. Heat-treating the Si substrate in an inert atmosphere to reduce the oxygen concentration on the surface to 1×10^1^7 or less, and growing a III-V compound semiconductor on the surface of the Si substrate. A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34058289A JP2853226B2 (en) | 1989-12-29 | 1989-12-29 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34058289A JP2853226B2 (en) | 1989-12-29 | 1989-12-29 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03203225A true JPH03203225A (en) | 1991-09-04 |
| JP2853226B2 JP2853226B2 (en) | 1999-02-03 |
Family
ID=18338378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34058289A Expired - Lifetime JP2853226B2 (en) | 1989-12-29 | 1989-12-29 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2853226B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001127326A (en) * | 1999-08-13 | 2001-05-11 | Oki Electric Ind Co Ltd | Semiconductor substrate, method of manufacturing the same, solar cell using the same and manufacturing method thereof |
-
1989
- 1989-12-29 JP JP34058289A patent/JP2853226B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001127326A (en) * | 1999-08-13 | 2001-05-11 | Oki Electric Ind Co Ltd | Semiconductor substrate, method of manufacturing the same, solar cell using the same and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2853226B2 (en) | 1999-02-03 |
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