JPH04280898A - Process for growing compound semiconductor crystal on si substrate - Google Patents
Process for growing compound semiconductor crystal on si substrateInfo
- Publication number
- JPH04280898A JPH04280898A JP6902391A JP6902391A JPH04280898A JP H04280898 A JPH04280898 A JP H04280898A JP 6902391 A JP6902391 A JP 6902391A JP 6902391 A JP6902391 A JP 6902391A JP H04280898 A JPH04280898 A JP H04280898A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- compound semiconductor
- gaas
- layer
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 150000001875 compounds Chemical class 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 title claims abstract description 27
- 239000013078 crystal Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims description 25
- 230000007547 defect Effects 0.000 abstract description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 31
- 235000012431 wafers Nutrition 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、Ｓｉ基板上にＧａＡｓ
，ＩｎＰなどの化合物半導体をエピタキシャル成長させ
る方法に関するものである。[Industrial Application Field] The present invention provides a method for forming GaAs on a Si substrate.
, and relates to a method for epitaxially growing compound semiconductors such as InP.
【０００２】0002
【従来の技術】発光素子や高感度受光素子，高速電子素
子などの半導体素子は、ＧａＡｓ等の化合物半導体を材
料として作製されているが、かかる化合物半導体の基板
は一般に高価で脆く、比重が大きいとともに、大面積化
が困難であるなどの問題がある。そこで、大面積化が可
能で軽量、高強度で且つ安価なＳｉ基板上に、上記化合
物半導体をエピタキシャル成長させることが考えられて
いる。[Prior Art] Semiconductor devices such as light-emitting devices, high-sensitivity light-receiving devices, and high-speed electronic devices are manufactured using compound semiconductors such as GaAs, but the substrates of such compound semiconductors are generally expensive, brittle, and have a high specific gravity. In addition, there are other problems such as difficulty in increasing the area. Therefore, it has been considered to epitaxially grow the above-mentioned compound semiconductor on a lightweight, high-strength, and inexpensive Si substrate that can be made into a large area.
【０００３】0003
【発明が解決しようとする課題】しかしながら、Ｓｉと
化合物半導体とではその格子定数や熱膨張係数が異なる
ため、Ｓｉ基板上にそのまま化合物半導体をエピタキシ
ャル成長させると、化合物半導体の結晶中に高密度の結
晶欠陥が発生し、これが前記発光素子などとして用いる
場合のデバイス特性を悪化させていた。[Problems to be Solved by the Invention] However, since Si and compound semiconductors have different lattice constants and coefficients of thermal expansion, if a compound semiconductor is grown epitaxially on a Si substrate, a high density of crystals will be formed in the crystal of the compound semiconductor. Defects occur, which deteriorate the device characteristics when used as the light emitting element or the like.
【０００４】本発明は以上の事情を背景として為された
もので、その目的とするところは、Ｓｉ基板上に結晶欠
陥が少ない化合物半導体をエピタキシャル成長させるこ
とにある。The present invention was made against the background of the above circumstances, and its object is to epitaxially grow a compound semiconductor with few crystal defects on a Si substrate.
【０００５】[0005]
【課題を解決するための手段】かかる目的を達成するた
めに、本発明は、Ｓｉ基板上に化合物半導体をエピタキ
シャル成長させる方法であって、（ａ）前記Ｓｉ基板上
にＳｉをエピタキシャル成長させてＳｉエピタキシャル
層を形成する工程と、（ｂ）そのＳｉエピタキシャル層
の上に前記化合物半導体をエピタキシャル成長させる工
程とを含むことを特徴とする。Means for Solving the Problems In order to achieve the above object, the present invention provides a method for epitaxially growing a compound semiconductor on a Si substrate, comprising: (a) epitaxially growing Si on the Si substrate; and (b) epitaxially growing the compound semiconductor on the Si epitaxial layer.
【０００６】[0006]
【実施例】以下、本発明の一実施例を図面に基づいて詳
細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.
【０００７】図１は、本発明方法に従って製造されたエ
ピタキシャルウェハの一例を説明する図で、かかるエピ
タキシャルウェハ１０は、Ｓｉ基板１２上にＳｉエピタ
キシャル層１４、バッファ層１６、ＧａＡｓ層１８、歪
超格子層２０、およびＧａＡｓ層２２が順次積層された
もので、バッファ層１４から上の部分が目的とする化合
物半導体である。FIG. 1 is a diagram illustrating an example of an epitaxial wafer manufactured according to the method of the present invention. Such an epitaxial wafer 10 includes a Si epitaxial layer 14, a buffer layer 16, a GaAs layer 18, and a super-strained layer on a Si substrate 12. A lattice layer 20 and a GaAs layer 22 are sequentially laminated, and the portion above the buffer layer 14 is the target compound semiconductor.
【０００８】上記Ｓｉ基板１２は、通常の引上げ法によ
って作製されたｐ−Ｓｉで、その表面の結晶面方位は（
１００）から〔０１１〕方向に３．６°傾けてあり、不
純物濃度は１０１８（ａｔｏｍ／ｃｍ３ ）程度である
。Ｓｉエピタキシャル層１４は、ＣＶＤ（化学気相成長
）法により約１０００℃〜１１００℃でＳｉＨ４ を熱
分解してＳｉをエピタキシャル成長させたもので、この
Ｓｉエピタキシャル層１４もｐ−Ｓｉから成り、その厚
さは約１１μｍで、不純物濃度は１０１８（ａｔｏｍ／
ｃｍ３ ）程度である。The Si substrate 12 is made of p-Si produced by a normal pulling method, and the crystal plane orientation of its surface is (
The impurity concentration is approximately 1018 (atoms/cm3). The Si epitaxial layer 14 is made by epitaxially growing Si by thermally decomposing SiH4 at approximately 1000°C to 1100°C using the CVD (chemical vapor deposition) method. This Si epitaxial layer 14 is also made of p-Si, and its thickness is The diameter is approximately 11 μm, and the impurity concentration is 1018 (atoms/
cm3).
【０００９】Ｓｉエピタキシャル層１４が設けられたＳ
ｉ基板１２は、室温まで冷却した後ＣＶＤの反応炉から
取り出されて数日間大気中に放置され、その後、化合物
半導体としてのＧａＡｓをＳｉエピタキシャル層１４上
にエピタキシャル成長させた。かかるＧａＡｓのエピタ
キシャル成長に際しては、予め有機溶剤による超音波清
浄を行うとともにフッ酸によるエッチング処理を施し、
Ｓｉエピタキシャル層１４の表面を清浄化した後、ＭＯ
ＣＶＤ（有機金属化学気相成長）装置の反応炉内にセッ
トして、図３に示されている加熱温度で成長処理を行っ
た。なお、この加熱温度はＳｉ基板１２がセットされる
サセプタにおける温度である。[0009] The S layer provided with the Si epitaxial layer 14
After the i-substrate 12 was cooled to room temperature, it was taken out from the CVD reactor and left in the atmosphere for several days, and then GaAs as a compound semiconductor was epitaxially grown on the Si epitaxial layer 14. When epitaxially growing GaAs, ultrasonic cleaning with an organic solvent is performed in advance, and etching treatment with hydrofluoric acid is performed.
After cleaning the surface of the Si epitaxial layer 14, the MO
The film was set in a reactor of a CVD (organic metal chemical vapor deposition) apparatus, and a growth process was performed at the heating temperature shown in FIG. Note that this heating temperature is the temperature in the susceptor in which the Si substrate 12 is set.
【００１０】上記図３を参照しつつ、ＧａＡｓのエピタ
キシャル成長について具体的に説明すると、先ず、１０
００℃程度まで加熱してＳｉエピタキシャル層１４の表
面に付着している酸化物等を除去し、その後４００℃程
度まで降温してＧａＡｓを結晶成長させた。この４００
℃程度でＧａＡｓを結晶成長させたものが前記バッファ
層１６であり、その厚さは約１２．５ｎｍである。この
バッファ層１６は結晶成長温度が低いため、この段階で
は単結晶となっていないが、続いて７５０℃程度まで昇
温することにより単結晶となり、その７５０℃程度に維
持した状態でバッファ層１６の上に更にＧａＡｓをエピ
タキシャル成長させた。この７５０℃程度でＧａＡｓを
エピタキシャル成長させたものが前記ＧａＡｓ層１８で
あり、その厚さは約１μｍである。上記バッファ層１６
は、ＳｉとＧａＡｓとの格子不整合を緩和するために形
成されるものである。Referring to FIG. 3 above, the epitaxial growth of GaAs will be explained in detail.
The silicon epitaxial layer 14 was heated to about 00° C. to remove oxides and the like adhering to the surface of the Si epitaxial layer 14, and then the temperature was lowered to about 400° C. to grow GaAs crystals. This 400
The buffer layer 16 is formed by crystal-growing GaAs at a temperature of approximately 12.5 nm in thickness. This buffer layer 16 is not a single crystal at this stage because the crystal growth temperature is low, but it becomes a single crystal by subsequently increasing the temperature to about 750°C, and while maintaining the temperature at about 750°C, the buffer layer 16 Further, GaAs was epitaxially grown on top of this. The GaAs layer 18 is formed by epitaxially growing GaAs at about 750° C., and has a thickness of about 1 μm. The buffer layer 16
is formed to alleviate the lattice mismatch between Si and GaAs.
【００１１】その後、一旦２００℃程度まで降温した後
９００℃程度まで昇温し、その９００℃程度に約１０分
間保持した後再び２００℃程度まで降温するという熱サ
イクルを行う。この熱サイクルは、上記ＧａＡｓ層１８
をアニールして転位等の結晶欠陥を逃がすためのもので
ある。２００℃程度まで降温したら直ちに７５０℃程度
まで昇温し、ＧａＡｓＰとＧａＡｓとを交互にエピタキ
シャル成長させる。これが前記歪超格子層２０であり、
その厚さは約０．２μｍである。Thereafter, a thermal cycle is performed in which the temperature is lowered to about 200°C, then raised to about 900°C, held at about 900°C for about 10 minutes, and then lowered to about 200°C again. This thermal cycle
This is to anneal and release crystal defects such as dislocations. Immediately after the temperature is lowered to about 200° C., the temperature is raised to about 750° C., and GaAsP and GaAs are epitaxially grown alternately. This is the strained superlattice layer 20,
Its thickness is approximately 0.2 μm.
【００１２】上記歪超格子層２０を形成した後、再び２
００℃への降温、９００℃への昇温、９００℃に１０分
間保持、２００℃への降温から成る熱サイクルを行って
アニールし、最後に、７５０℃程度で再びＧａＡｓをエ
ピタキシャル成長させた。この７５０℃程度でＧａＡｓ
をエピタキシャル成長させたものが前記ＧａＡｓ層２２
であり、その厚さは約１．８μｍである。したがって、
Ｓｉエピタキシャル層１４上には、歪超格子層２０も含
めて約３μｍのＧａＡｓ単結晶がエピタキシャル成長さ
せられたことになる。After forming the strained superlattice layer 20, 2
Annealing was performed by performing a thermal cycle consisting of lowering the temperature to 00°C, raising the temperature to 900°C, holding the temperature at 900°C for 10 minutes, and lowering the temperature to 200°C.Finally, GaAs was epitaxially grown again at about 750°C. At this temperature of about 750°C, GaAs
The GaAs layer 22 is epitaxially grown.
and its thickness is approximately 1.8 μm. therefore,
This means that on the Si epitaxial layer 14, including the strained superlattice layer 20, a GaAs single crystal of about 3 μm is epitaxially grown.
【００１３】このようにして作製されたエピタキシャル
ウェハ１０のＧａＡｓ層２２の表面を溶融ＫＯＨでエッ
チングし、結晶欠陥によって発生するエッチピットの密
度を測定したところ、１×１０５ 個／ｃｍ２ であっ
た。
これに対し、図２に示されているように、上記Ｓｉエピ
タキシャル層１４を形成することなく、Ｓｉ基板２４上
に直接バッファ層１６、ＧａＡｓ層１８、歪超格子層２
０、およびＧａＡｓ層２２をエピタキシャルウェハ１０
の場合と全く同じ方法、具体的には図３に示されている
加熱温度でエピタキシャル成長させてエピタキシャルウ
ェハ２６を作製し、そのＧａＡｓ層２２の表面を溶融Ｋ
ＯＨでエッチングしてエッチピット密度を測定したとこ
ろ、３×１０６ 個／ｃｍ２ であった。すなわち、Ｓ
ｉ基板１２上にＳｉエピタキシャル層１４を形成して、
その上にＧａＡｓをエピタキシャル成長させると、Ｓｉ
基板２４上に直接ＧａＡｓをエピタシャル成長させた場
合に比較して、結晶欠陥が約１／３０になったのである
。なお、上記Ｓｉ基板２４は引上げ法によって作製され
たｎ−Ｓｉであり、その不純物濃度は１０１８（ａｔｏ
ｍ／ｃｍ３ ）程度である。The surface of the GaAs layer 22 of the epitaxial wafer 10 thus fabricated was etched with molten KOH, and the density of etch pits generated by crystal defects was measured to be 1×10 5 pits/cm 2 . On the other hand, as shown in FIG. 2, the buffer layer 16, the GaAs layer 18, and the strained superlattice layer 2 are directly formed on the Si substrate 24 without forming the Si epitaxial layer 14.
0, and the GaAs layer 22 on the epitaxial wafer 10
The epitaxial wafer 26 is fabricated by epitaxial growth using exactly the same method as in the case of FIG. 3, specifically, at the heating temperature shown in FIG.
When the etch pit density was measured by etching with OH, it was found to be 3×10 6 pits/cm 2 . That is, S
Forming a Si epitaxial layer 14 on the i-substrate 12,
When GaAs is epitaxially grown on top of it, Si
Compared to the case where GaAs was epitaxially grown directly on the substrate 24, the number of crystal defects was reduced to about 1/30. The Si substrate 24 is made of n-Si manufactured by a pulling method, and its impurity concentration is 1018 (ato
m/cm3).
【００１４】以上、本発明方法に従って作製されたエピ
タキシャルウェハの一例、並びに結晶欠陥低減に関する
試験結果について説明したが、本発明は他の態様で実施
することもできる。Although an example of an epitaxial wafer manufactured according to the method of the present invention and test results regarding reduction of crystal defects have been described above, the present invention can also be practiced in other embodiments.
【００１５】例えば、前記実施例では化合物半導体とし
てＧａＡｓをエピタキシャル成長させる場合について説
明したが、ＩｎＰなどの他の化合物半導体をＳｉ基板上
に形成する場合にも本発明は同様に適用され得る。For example, in the above embodiment, the case where GaAs is epitaxially grown as a compound semiconductor has been described, but the present invention can be similarly applied to the case where other compound semiconductors such as InP are formed on a Si substrate.
【００１６】また、前記実施例ではＭＯＣＶＤ法を用い
て化合物半導体をエピタキシャル成長させる場合につい
て説明したが、分子線エピタキシー法などの他のエピタ
キシャル成長法を採用することもできる。Further, in the above embodiment, the case where a compound semiconductor is epitaxially grown using MOCVD method has been described, but other epitaxial growth methods such as molecular beam epitaxy method can also be adopted.
【００１７】また、前記ＧａＡｓのエピタキシャル成長
工程はあくまでも一例で、例えばバッファ層１６の代わ
りにＧａＰ層、ＧａＰ／ＧａＡｓＰ歪超格子層、ＧａＡ
ｓＰ／ＧａＡｓ歪超格子層を順次エピタキシャル成長さ
せて、ＳｉとＧａＡｓとの格子不整合を緩和することも
できるなど、必要に応じて適宜変更され得る。要するに
、Ｓｉ基板上にＳｉをエピタキシャル成長させて、その
上に化合物半導体をエピタキシャル成長させるようにな
っておれば良く、その化合物半導体のエピタキシャル成
長に際しては種々の手法が採用され得るのである。Further, the GaAs epitaxial growth process is just one example; for example, instead of the buffer layer 16, a GaP layer, a GaP/GaAsP strained superlattice layer, a GaAs
The method may be modified as necessary, such as by sequentially growing sP/GaAs strained superlattice layers epitaxially to alleviate the lattice mismatch between Si and GaAs. In short, it is sufficient to epitaxially grow Si on a Si substrate and then epitaxially grow a compound semiconductor thereon, and various methods can be adopted for epitaxially growing the compound semiconductor.
【００１８】また、前記実施例ではＳｉ基板１２上にＳ
ｉエピタキシャル層１４を形成した後、一旦反応炉から
取り出して室温に放置する場合について説明したが、Ｇ
ａＡｓをエピタキシャル成長させるＭＯＣＶＤ装置にＳ
ｉＨ４ のガスタンクを設けて、Ｓｉのエピタキシャル
成長とＧａＡｓのエピタキシャル成長とを連続的に行う
ようにすることも可能である。Further, in the above embodiment, S is formed on the Si substrate 12.
Although the case where the i-epitaxial layer 14 is formed, it is taken out of the reactor and left at room temperature has been explained,
S is installed in MOCVD equipment for epitaxial growth of aAs.
It is also possible to provide an iH4 gas tank so that Si epitaxial growth and GaAs epitaxial growth can be performed continuously.
【００１９】また、前記実施例ではＳｉＨ４ を熱分解
してＳｉをエピタキシャル成長させる場合について説明
したが、ＳｉＨ２ Ｃｌ２を熱分解してＳｉを気相成長
させたり、ＳｉＣｌ４ を水素還元してＳｉを気相成長
させたりするなど、他のエピタキシャル成長手段を採用
することもできる。Further, in the above embodiment, the case where Si is epitaxially grown by thermally decomposing SiH4 is explained, but it is also possible to thermally decompose SiH2Cl2 to grow Si in a vapor phase, or reduce SiCl4 with hydrogen to grow Si in a vapor phase. Other epitaxial growth methods can also be employed, such as by growing.
【００２０】その他一々例示はしないが、本発明は当業
者の知識に基づいて種々の変更，改良を加えた態様で実
施することができる。Although no other examples are given, the present invention can be implemented with various modifications and improvements based on the knowledge of those skilled in the art.
【００２１】[0021]
【発明の効果】以上詳述したように、Ｓｉ基板上にＳｉ
をエピタキシャル成長させてＳｉエピタキシャル層を形
成し、そのＳｉエピタキシャル層の上に化合物半導体を
エピタキシャル成長させる本発明方法によれば、前述の
試験結果から明らかなように、Ｓｉ基板上に直接化合物
半導体をエピタキシャル成長させる場合に比較して化合
物半導体内の結晶欠陥が低減されるのである。Effects of the Invention As detailed above, Si
According to the method of the present invention, in which a Si epitaxial layer is formed by epitaxial growth, and a compound semiconductor is epitaxially grown on the Si epitaxial layer, the compound semiconductor is epitaxially grown directly on the Si substrate, as is clear from the above test results. The number of crystal defects in the compound semiconductor is reduced compared to the case where the crystal defects are present in the compound semiconductor.
【図１】本発明方法に従って作製されたエピタキシャル
ウェハの一例を説明する図である。FIG. 1 is a diagram illustrating an example of an epitaxial wafer manufactured according to the method of the present invention.
【図２】Ｓｉ基板上に直接ＧａＡｓをエピタキシャル成
長させたエピタキシャルウェハの一例を説明する図であ
る。FIG. 2 is a diagram illustrating an example of an epitaxial wafer in which GaAs is epitaxially grown directly on a Si substrate.
【図３】図１および図２のエピタキシャルウェハにおけ
るＧａＡｓのエピタキシャル成長工程を説明する加熱温
度のタイムチャートである。3 is a time chart of heating temperatures illustrating the GaAs epitaxial growth process on the epitaxial wafers of FIGS. 1 and 2; FIG.
１２：Ｓｉ基板 １４：Ｓｉエピタキシャル層 12:Si substrate 14: Si epitaxial layer
Claims (1)
シャル成長させる方法であって、前記Ｓｉ基板上にＳｉ
をエピタキシャル成長させてＳｉエピタキシャル層を形
成する工程と、該Ｓｉエピタキシャル層の上に前記化合
物半導体をエピタキシャル成長させる工程とを含むこと
を特徴とするＳｉ基板上への化合物半導体の結晶成長法
。1. A method for epitaxially growing a compound semiconductor on a Si substrate, the method comprising: growing a compound semiconductor on a Si substrate;
A method for growing crystals of a compound semiconductor on a Si substrate, the method comprising the steps of epitaxially growing a Si epitaxial layer to form an Si epitaxial layer, and epitaxially growing the compound semiconductor on the Si epitaxial layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6902391A JPH04280898A (en) | 1991-03-08 | 1991-03-08 | Process for growing compound semiconductor crystal on si substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6902391A JPH04280898A (en) | 1991-03-08 | 1991-03-08 | Process for growing compound semiconductor crystal on si substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04280898A true JPH04280898A (en) | 1992-10-06 |
Family
ID=13390576
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6902391A Pending JPH04280898A (en) | 1991-03-08 | 1991-03-08 | Process for growing compound semiconductor crystal on si substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04280898A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014511815A (en) * | 2011-04-07 | 2014-05-19 | エヌアーエスペー スリー／ヴィー ゲーエムベーハー | III / VSi Template Manufacturing Method |
| US9595438B2 (en) | 2011-09-12 | 2017-03-14 | Nasp Iii/V Gmbh | Method for producing a III/V Si template |
-
1991
- 1991-03-08 JP JP6902391A patent/JPH04280898A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014511815A (en) * | 2011-04-07 | 2014-05-19 | エヌアーエスペー スリー／ヴィー ゲーエムベーハー | III / VSi Template Manufacturing Method |
| US9595438B2 (en) | 2011-09-12 | 2017-03-14 | Nasp Iii/V Gmbh | Method for producing a III/V Si template |
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