JPH03173999A - 電気的にプログラム可能でかつ消去可能な複数のメモリセルを有するメモリアレイ - Google Patents
電気的にプログラム可能でかつ消去可能な複数のメモリセルを有するメモリアレイInfo
- Publication number
- JPH03173999A JPH03173999A JP2215102A JP21510290A JPH03173999A JP H03173999 A JPH03173999 A JP H03173999A JP 2215102 A JP2215102 A JP 2215102A JP 21510290 A JP21510290 A JP 21510290A JP H03173999 A JPH03173999 A JP H03173999A
- Authority
- JP
- Japan
- Prior art keywords
- cells
- potential
- region
- coupled
- block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 15
- 230000008878 coupling Effects 0.000 claims 4
- 238000010168 coupling process Methods 0.000 claims 4
- 238000005859 coupling reaction Methods 0.000 claims 4
- 239000000758 substrate Substances 0.000 abstract 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
Landscapes
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
め要約のデータは記録されません。
Description
関するものであり、とくに、浮動ゲートメモリ装置を採
用する電気的にプログラム可能なメモリに関するもので
ある。
能な読出し専用メモIJ (EPROM)は、電気的に
分離されているゲート(浮動ゲート)を有するメモリセ
ルをしばしば用いる。それらの浮動ゲートは典型的には
絶縁体により完全に囲筐れ、多結晶シリコン(ポリシリ
コン)層から形成される。
モリ装置に記憶される。電子なだれ注入、チャネル注入
、トンネル効果等、セルの構造に応じてきまる各種のメ
カニズムによって、電荷は浮動ゲートへ送られる。アレ
イに紫外線を照射することにようセルは全体的に消去さ
れる。それらのセルの例全米国粋許第3,500,14
2号、第3.660゜819号、第4,099,196
号に見ることができる。
PROMセル)。そのようなセルの例が米国特許第4,
203,158号に示されている。
Claims (2)
- (1)ソース領域と、ドレイン領域と、浮動ゲートと、
制御ゲートとをおのおの有する電気的に消去可能かつ電
気的に消去可能な複数のメモリセルを有するメモリアレ
イにおいて、 複数の前記セルの前記ドレイン領域へ結合される全体と
して並列の複数のビット線をおのおの有する複数のブロ
ックと、 各ブロックに1つずつ設けられるソーススイツチであつ
て、各ソーススイッチへ前記各ブロック中の前記複数の
前記セルの前記ソース領域が結合される複数のソースス
イッチと、 各前記ビット線上の1つの前記セルの前記制御ゲートへ
おのおのが結合され、前記複数のブロックを通つて延長
し、かつ連続である、前記ビット線に対して全体として
垂直である複数の語線と、1本の前記語線が選択された
時に、全ての前記ブロック内の前記語線に沿う前記セル
の前記制御ゲートにおける電位が変えられるように、行
アドレスを復号し、語線を選択する行復号器手段と、プ
ログラミングのために選択された1つのブロック中の複
数のビット線のプログラミング中に、前記選択されたブ
ロック中の前記セルの前記ソース領域を選択し、かつそ
れらのソース領域を第1の電位へ結合し、かつ選択され
ていない前記ブロック中の前記セルの前記ソース領域を
選択し、かつそれらのソース領域を第2の電位へ結合し
、更に、選択された前記ブロック中の前記セルの前記ソ
ース領域を消去中に第3の電位へ結合し、選択されてい
ない前記ブロック中の前記セルの前記ソース領域を前記
第1の電位へ結合する第2の復号器手段と、 を備える、電気的にプログラム可能でかつ消去可能な複
数のメモリセルを有するメモリアレイ。 - (2)全体として平行な複数の語線と、 それらの語線に垂直な、全体として平行な複数のビット
線と、 前記ビット線と前記語線の各交点におのおの組合わされ
、それぞれのビット線へ結合される第1の領域と、第2
の領域と、前記語線により形成された制御ゲートとをお
のおのが有する複数のメモリセルと、 隣接する前記ビット線のブロック内の前記セルの前記第
2の領域を第1の電位、第2の電位または第3の電位へ
選択的におのおの結合する複数のスイッチング手段と、 前記語線へ結合され、第1のアドレス信号を受け、前記
語線の少くとも1本を選択して、選択された前記語線に
沿う全ての前記セルが選択された同じ電位を受けるよう
にする第1の復号手段と、前記ビット線へ結合され、第
2のアドレス信号を受け、選択された1つの前記ブロッ
ク中の少くとも1本の前記ビット線を選択する第2の復
号手段と、 前記セルの前記第2の領域を前記第1の電位、前記第2
の電位または前記第3の電位の1つへ結合するために前
記スイッチへ結合され、前記第2のアドレス信号の少く
ともいくつかを受ける第3の復号手段と、 を備える電気的にプログラム可能でかつ消去可能なメモ
リ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US407.645 | 1989-09-15 | ||
US07/407,645 US5065364A (en) | 1989-09-15 | 1989-09-15 | Apparatus for providing block erasing in a flash EPROM |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03173999A true JPH03173999A (ja) | 1991-07-29 |
JP2847322B2 JP2847322B2 (ja) | 1999-01-20 |
Family
ID=23612935
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21510290A Expired - Lifetime JP2847322B2 (ja) | 1989-09-15 | 1990-08-16 | 電気的にプログラム可能でかつ消去可能な複数のメモリセルを有するメモリアレイ |
Country Status (8)
Country | Link |
---|---|
US (1) | US5065364A (ja) |
JP (1) | JP2847322B2 (ja) |
DE (1) | DE4028575C2 (ja) |
FR (1) | FR2652189B1 (ja) |
GB (1) | GB2235999B (ja) |
HK (1) | HK63794A (ja) |
IE (1) | IE64921B1 (ja) |
IT (1) | IT1242990B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7505329B2 (en) | 1992-03-17 | 2009-03-17 | Renesas Technology Corp. | Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein |
Families Citing this family (116)
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- 1990-04-19 IE IE139990A patent/IE64921B1/en not_active IP Right Cessation
- 1990-04-25 FR FR909005278A patent/FR2652189B1/fr not_active Expired - Fee Related
- 1990-08-16 JP JP21510290A patent/JP2847322B2/ja not_active Expired - Lifetime
- 1990-08-29 IT IT02132190A patent/IT1242990B/it active IP Right Grant
- 1990-09-08 DE DE4028575A patent/DE4028575C2/de not_active Expired - Fee Related
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1994
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US7505329B2 (en) | 1992-03-17 | 2009-03-17 | Renesas Technology Corp. | Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein |
US7965563B2 (en) | 1992-03-17 | 2011-06-21 | Renesas Technology Corp. | Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein |
Also Published As
Publication number | Publication date |
---|---|
IT9021321A1 (it) | 1992-02-29 |
FR2652189A1 (fr) | 1991-03-22 |
JP2847322B2 (ja) | 1999-01-20 |
FR2652189B1 (fr) | 1994-03-04 |
IT1242990B (it) | 1994-05-23 |
US5065364A (en) | 1991-11-12 |
IE64921B1 (en) | 1995-09-20 |
HK63794A (en) | 1994-07-15 |
GB2235999B (en) | 1993-12-15 |
DE4028575C2 (de) | 1998-06-04 |
IE901399A1 (en) | 1991-03-27 |
GB9005482D0 (en) | 1990-05-09 |
IT9021321A0 (it) | 1990-08-29 |
GB2235999A (en) | 1991-03-20 |
DE4028575A1 (de) | 1991-03-28 |
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