JPH03173999A - 電気的にプログラム可能でかつ消去可能な複数のメモリセルを有するメモリアレイ - Google Patents

電気的にプログラム可能でかつ消去可能な複数のメモリセルを有するメモリアレイ

Info

Publication number
JPH03173999A
JPH03173999A JP2215102A JP21510290A JPH03173999A JP H03173999 A JPH03173999 A JP H03173999A JP 2215102 A JP2215102 A JP 2215102A JP 21510290 A JP21510290 A JP 21510290A JP H03173999 A JPH03173999 A JP H03173999A
Authority
JP
Japan
Prior art keywords
cells
potential
region
coupled
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2215102A
Other languages
English (en)
Other versions
JP2847322B2 (ja
Inventor
Gregory E Atwood
グレゴリー・イー・アトウツド
Albert N M I Fazio
アルバート・エヌエムアイ・ファツイオ
Richard A Lodenquai
リチヤード・エイ・ローデンケ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JPH03173999A publication Critical patent/JPH03173999A/ja
Application granted granted Critical
Publication of JP2847322B2 publication Critical patent/JP2847322B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

Landscapes

  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電気的にプログラム可能な読出し専用メモリに
関するものであり、とくに、浮動ゲートメモリ装置を採
用する電気的にプログラム可能なメモリに関するもので
ある。
〔従来の技術〕
金属−酸化物一半導体ＣＭＯ８）！気的にプログラム可
能な読出し専用メモＩＪ　（ＥＰＲＯＭ）は、電気的に
分離されているゲート（浮動ゲート）を有するメモリセ
ルをしばしば用いる。それらの浮動ゲートは典型的には
絶縁体により完全に囲筐れ、多結晶シリコン（ポリシリ
コン）層から形成される。
情報は浮動ゲート上の電荷の形でメモリセルすなわちメ
モリ装置に記憶される。電子なだれ注入、チャネル注入
、トンネル効果等、セルの構造に応じてきまる各種のメ
カニズムによって、電荷は浮動ゲートへ送られる。アレ
イに紫外線を照射することにようセルは全体的に消去さ
れる。それらのセルの例全米国粋許第３，５００，１４
２号、第３．６６０゜８１９号、第４，０９９，１９６
号に見ることができる。
ある場合にはそれらのセルは電気的に消去できる（Ｅｇ
ＰＲＯＭセル）。そのようなセルの例が米国特許第４，
２０３，１５８号に示されている。

Claims (2)

    【特許請求の範囲】
  1. （１）ソース領域と、ドレイン領域と、浮動ゲートと、
    制御ゲートとをおのおの有する電気的に消去可能かつ電
    気的に消去可能な複数のメモリセルを有するメモリアレ
    イにおいて、 複数の前記セルの前記ドレイン領域へ結合される全体と
    して並列の複数のビット線をおのおの有する複数のブロ
    ックと、 各ブロックに１つずつ設けられるソーススイツチであつ
    て、各ソーススイッチへ前記各ブロック中の前記複数の
    前記セルの前記ソース領域が結合される複数のソースス
    イッチと、 各前記ビット線上の１つの前記セルの前記制御ゲートへ
    おのおのが結合され、前記複数のブロックを通つて延長
    し、かつ連続である、前記ビット線に対して全体として
    垂直である複数の語線と、１本の前記語線が選択された
    時に、全ての前記ブロック内の前記語線に沿う前記セル
    の前記制御ゲートにおける電位が変えられるように、行
    アドレスを復号し、語線を選択する行復号器手段と、プ
    ログラミングのために選択された１つのブロック中の複
    数のビット線のプログラミング中に、前記選択されたブ
    ロック中の前記セルの前記ソース領域を選択し、かつそ
    れらのソース領域を第１の電位へ結合し、かつ選択され
    ていない前記ブロック中の前記セルの前記ソース領域を
    選択し、かつそれらのソース領域を第２の電位へ結合し
    、更に、選択された前記ブロック中の前記セルの前記ソ
    ース領域を消去中に第３の電位へ結合し、選択されてい
    ない前記ブロック中の前記セルの前記ソース領域を前記
    第１の電位へ結合する第２の復号器手段と、 を備える、電気的にプログラム可能でかつ消去可能な複
    数のメモリセルを有するメモリアレイ。
  2. （２）全体として平行な複数の語線と、 それらの語線に垂直な、全体として平行な複数のビット
    線と、 前記ビット線と前記語線の各交点におのおの組合わされ
    、それぞれのビット線へ結合される第１の領域と、第２
    の領域と、前記語線により形成された制御ゲートとをお
    のおのが有する複数のメモリセルと、 隣接する前記ビット線のブロック内の前記セルの前記第
    ２の領域を第１の電位、第２の電位または第３の電位へ
    選択的におのおの結合する複数のスイッチング手段と、 前記語線へ結合され、第１のアドレス信号を受け、前記
    語線の少くとも１本を選択して、選択された前記語線に
    沿う全ての前記セルが選択された同じ電位を受けるよう
    にする第１の復号手段と、前記ビット線へ結合され、第
    ２のアドレス信号を受け、選択された１つの前記ブロッ
    ク中の少くとも１本の前記ビット線を選択する第２の復
    号手段と、 前記セルの前記第２の領域を前記第１の電位、前記第２
    の電位または前記第３の電位の１つへ結合するために前
    記スイッチへ結合され、前記第２のアドレス信号の少く
    ともいくつかを受ける第３の復号手段と、 を備える電気的にプログラム可能でかつ消去可能なメモ
    リ。
JP21510290A 1989-09-15 1990-08-16 電気的にプログラム可能でかつ消去可能な複数のメモリセルを有するメモリアレイ Expired - Lifetime JP2847322B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US407.645 1989-09-15
US07/407,645 US5065364A (en) 1989-09-15 1989-09-15 Apparatus for providing block erasing in a flash EPROM

Publications (2)

Publication Number Publication Date
JPH03173999A true JPH03173999A (ja) 1991-07-29
JP2847322B2 JP2847322B2 (ja) 1999-01-20

Family

ID=23612935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21510290A Expired - Lifetime JP2847322B2 (ja) 1989-09-15 1990-08-16 電気的にプログラム可能でかつ消去可能な複数のメモリセルを有するメモリアレイ

Country Status (8)

Country Link
US (1) US5065364A (ja)
JP (1) JP2847322B2 (ja)
DE (1) DE4028575C2 (ja)
FR (1) FR2652189B1 (ja)
GB (1) GB2235999B (ja)
HK (1) HK63794A (ja)
IE (1) IE64921B1 (ja)
IT (1) IT1242990B (ja)

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US7505329B2 (en) 1992-03-17 2009-03-17 Renesas Technology Corp. Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein

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FR2652189B1 (fr) 1994-03-04
IT1242990B (it) 1994-05-23
US5065364A (en) 1991-11-12
IE64921B1 (en) 1995-09-20
HK63794A (en) 1994-07-15
GB2235999B (en) 1993-12-15
DE4028575C2 (de) 1998-06-04
IE901399A1 (en) 1991-03-27
GB9005482D0 (en) 1990-05-09
IT9021321A0 (it) 1990-08-29
GB2235999A (en) 1991-03-20
DE4028575A1 (de) 1991-03-28

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