JPH03173160A - Package for housing semiconductor element - Google Patents

Package for housing semiconductor element

Info

Publication number
JPH03173160A
JPH03173160A JP1312728A JP31272889A JPH03173160A JP H03173160 A JPH03173160 A JP H03173160A JP 1312728 A JP1312728 A JP 1312728A JP 31272889 A JP31272889 A JP 31272889A JP H03173160 A JPH03173160 A JP H03173160A
Authority
JP
Japan
Prior art keywords
external lead
lead terminal
glass
semiconductor element
lid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1312728A
Other languages
Japanese (ja)
Other versions
JP2742618B2 (en
Inventor
Hiroshi Matsumoto
弘 松本
Masaaki Iguchi
井口 公明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP1312728A priority Critical patent/JP2742618B2/en
Priority to US07/573,406 priority patent/US5057905A/en
Publication of JPH03173160A publication Critical patent/JPH03173160A/en
Application granted granted Critical
Publication of JP2742618B2 publication Critical patent/JP2742618B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce a noise generated at an external lead terminal to a minimum and to reduce an attenuation of a signal to a minimum at the external lead terminal by a method wherein an insulating container is formed of a forsterite sintered substance or a zirconia sintered substance, the external lead terminal is formed of a metal of a specific physical property and a glass member is formed of a glass of a specific composition. CONSTITUTION:An insulating substrate 1 and a lid body 2 are formed of a forsterite sintered substance or a zirconia sintered substance; glass members 6, for sealing use, applied to opposite main faces of the insulating substrate 1 and the lid body 2 are formed of a glass composed of the following: 60.0 to 70.0wt.% of silica; 10.0 to 20.0wt.% of at least one kind of oxides of sodium and potassium; and 5.0 to 15.0wt.% of barium oxide. Regarding external lead terminals 5, their permeability is 200 (CGS) or lower, their electric conductivity is 10% (IACS) or higher and their coefficient of thermal expansion is 100 to 110X10<-7>/ deg.C.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体素子を収容する半導体素子収納用パッケ
ージの改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a semiconductor element housing package that houses a semiconductor element.

(従来の技術) 従来、半導体素子を収容するためのパッケージ、特にガ
ラスの溶着によって封止するガラス封止型半導体素子収
納用パッケージは、絶縁基体と蓋体とから成り、内部に
半導体素子を収容する空所を有する絶縁容器と、該容器
内に収容される半導体素子を外部電気回路に電気的に接
続するための外部リード端子とから構成されており、絶
縁基体及び蓋体の相対向する主面に予め封止用のガラス
部材を被着形成すると共に、絶縁基体主面に外部リード
端子を固定し、半導体素子の各電極と外部リード端子と
をワイヤポンド接続した後、絶縁基体及び蓋体のそれぞ
に被着させた封止用のガラス部材を溶融一体止させるこ
とによって内部に半導体素子を気密に封止している。
(Prior Art) Conventionally, a package for accommodating a semiconductor element, particularly a glass-sealed semiconductor element accommodating package sealed by glass welding, consists of an insulating base and a lid body, and the semiconductor element is housed inside. The device is composed of an insulating container having a cavity to open the container, and an external lead terminal for electrically connecting the semiconductor element housed in the container to an external electric circuit. A glass member for sealing is formed on the surface in advance, external lead terminals are fixed to the main surface of the insulating substrate, and each electrode of the semiconductor element and the external lead terminal are connected with a wire bond, and then the insulating substrate and the lid are attached. The semiconductor element is hermetically sealed inside by melting and integrally sealing glass members attached to each of the parts.

(発明が解決しようとする課題) しかし乍ら、この従来のガラス封止型半導体素子収納用
パッケージは通常、外部リード端子がコバール(29W
tX Ni−16WtX Co−55WtχFe合金)
や42Alloy(42WtXNi−58WtZ Fe
合金)の導電性材料から成っており、該コバールや42
AIloy等は透磁率が高く、且つ導電率が低いことか
ら以下に述べる欠点を有する。
(Problem to be Solved by the Invention) However, in this conventional glass-sealed package for storing semiconductor elements, the external lead terminals are usually Kovar (29W).
tX Ni-16WtX Co-55WtχFe alloy)
Ya 42Alloy (42WtXNi-58WtZ Fe
It is made of conductive materials such as Kovar and 42
Since AIloy and the like have high magnetic permeability and low electrical conductivity, they have the following drawbacks.

即ら、 ■コバールや42八I joyは鉄(Fe)、ニッケル
(Ni)、コバルト(co)といった強磁性体金属のみ
から成っており、その透磁率は250〜700 (CG
S)と高い。そのためこのコバールや42A11oy等
から成る外部リード端子に電流が流れると外部リード端
子中に透磁率に比例した大きな自己インダクタンスが発
生し、これが逆起電力を誘発してノイズとなると共に、
該ノイズが半導体素子に入力されて半導体素子に誤動作
を生じさせる、 ■コバールや42Alloyはその導電率が3.0〜3
.5χ(lAC3)と低い。そのためこのコバールや4
2Alloy等から成る外部リード端子に信号を伝搬さ
せた場合、信号の伝搬速度が極めて遅いものとなり、高
速駆動を行う半導体素子はその収容が不可となってしま
う、 ■半導体素子収納用パッケージの内部に収容する半導体
素子の高密度化、高集積化の進展に伴い、半導体素子の
電極数が大幅に増大しており、半導体素子の各電極を外
部電気回路に接続する外部リード端子の線幅も極めて細
くなってきている。そのため外部リード端子は上記■に
記載のコバールや42^11oyの導電率が低いことと
相俊って電気抵抗が極めて大きなものになってきており
、外部リード端子に信号を伝搬させると、該外部リード
端子の電気抵抗に起因して信号が大きく減衰し、内部に
収容する半導体素子に信号を正確に入力することができ
ず、半導体素子に誤動作を生じさせてしまう、 等の欠点を有していた。
In other words, Kovar and 428I joy are made only of ferromagnetic metals such as iron (Fe), nickel (Ni), and cobalt (Co), and their magnetic permeability is 250 to 700 (CG
S) and high. Therefore, when a current flows through the external lead terminal made of Kovar, 42A11oy, etc., a large self-inductance proportional to the magnetic permeability is generated in the external lead terminal, which induces a back electromotive force and causes noise.
The noise is input to the semiconductor device and causes the semiconductor device to malfunction. ■ Kovar and 42Alloy have an electrical conductivity of 3.0 to 3.
.. It is as low as 5χ(lAC3). Therefore, this Kobar and 4
When a signal is propagated to an external lead terminal made of 2Alloy, etc., the signal propagation speed becomes extremely slow, making it impossible to accommodate semiconductor devices that drive at high speed. With the progress of higher density and higher integration of semiconductor devices, the number of electrodes on semiconductor devices has increased significantly, and the line width of external lead terminals that connect each electrode of semiconductor devices to external electric circuits has also become extremely large. It's getting thinner. Therefore, the electrical resistance of the external lead terminal has become extremely large due to the low conductivity of Kovar and 42^11oy described in (■) above, and when a signal is propagated to the external lead terminal, It has the disadvantage that the signal is greatly attenuated due to the electrical resistance of the lead terminal, making it impossible to accurately input the signal to the semiconductor element housed inside, causing the semiconductor element to malfunction. Ta.

(発明の目的) 本発明は上記欠点に鑑み案出されたもので、その目的は
外部リード端子で発生するノイズ及び外部リード端子に
おける信号の減衰を極小となし、内部に収容する半導体
素子への信号の入出力を確実に行うことを可能として半
導体素子を長期間にわたり正常、且つ安定に作動させる
ことができる半導体素子収納用パッケージを提供するこ
とにある。
(Object of the Invention) The present invention was devised in view of the above drawbacks, and its purpose is to minimize the noise generated at the external lead terminal and the attenuation of the signal at the external lead terminal, and to minimize the noise generated at the external lead terminal and the attenuation of the signal at the external lead terminal. It is an object of the present invention to provide a package for storing a semiconductor element, which enables reliable input and output of signals and allows the semiconductor element to operate normally and stably for a long period of time.

また本発明の他の目的は高速駆動を行う半導体素子を収
容することができる半導体素子収納用パ・2ケージを提
供することにある。
Another object of the present invention is to provide a package 2 for storing semiconductor devices that can accommodate semiconductor devices that operate at high speed.

(課題を解決するための手段) 本発明は内部に半導体素子を収容するための空所を有す
る絶縁容器に外部リード端子をガラス部材を介して取着
して成る半導体素子収納用パンケージにおいて、前記&
fi S&容器をフォルステライト質焼結体もしくはジ
ルコニア質焼結体で、外部リード端子を透磁率200(
CGS )以下、熱膨張係数100乃至110 X 1
0−’/ ℃、導電率102(lAC3)以上の金属で
、ガラス部材をシリカ60.0乃至70.OWt%、ナ
トリウム、カリウムの酸化物の少なくとも1種10.0
乃至20.0WtX、酸化バリウム5.0乃至15.O
Wtχから成るガラスで形成したことを特徴とするもの
である。
(Means for Solving the Problems) The present invention provides a semiconductor device storage pancase comprising an insulating container having a cavity for accommodating a semiconductor device and an external lead terminal attached via a glass member. &
The fi S& container is made of forsterite sintered body or zirconia sintered body, and the external lead terminal is made of magnetic permeability 200 (
CGS) Below, thermal expansion coefficient 100 to 110 x 1
0-'/°C, a metal with an electrical conductivity of 102 (lAC3) or more, and a glass member made of silica 60.0 to 70. OWt%, at least one of sodium and potassium oxides 10.0
to 20.0 WtX, barium oxide 5.0 to 15. O
It is characterized in that it is made of glass made of Wtχ.

(実施例) 次に本発明を添°付図面に基づき詳細に説明する。(Example) Next, the present invention will be explained in detail based on the accompanying drawings.

第1図及び第2図は本発明の半導体素子収納用パッケー
ジの一実施例を示し、1は絶縁基体、2は蓋体である。
FIGS. 1 and 2 show an embodiment of the semiconductor element storage package of the present invention, where 1 is an insulating base and 2 is a lid.

この絶縁基体lと蓋体2とにより絶縁容器3が構成され
る。
The insulating base 1 and the lid 2 constitute an insulating container 3.

前記絶縁基体1及び蓋体2はそれぞれの中央部に半導体
素子を収容する空所を形成するための凹部が設けてあり
、絶縁基体1の凹部底面には半導体素子4が樹脂、ガラ
ス、ロウ剤等の接着剤を介し取着固定される。
The insulating base 1 and the lid 2 are each provided with a recess in the center thereof to form a cavity for accommodating a semiconductor element, and the semiconductor element 4 is placed in a resin, glass, or brazing agent on the bottom of the recess of the insulating base 1. It is attached and fixed via adhesive such as.

前記絶縁基体1及び蓋体2はフォルステライト質焼結体
もしくはジルコニア質焼結体から成り、第1図に示すよ
うな絶縁基体1及び蓋体2に対応した形状を有するプレ
ス型内に、フォルステライト質焼結体の場合はマグネシ
ア(MgO) 、シリカ(SiOz)等の原料粉末を、
ジルコニア質焼結体の場合は酸化ジルコニウム(ZrO
z)、イツトリア(Y2O2)等の原料粉末を充填させ
るとともに一定圧力を印加して成形し、しかる後、成形
品を約1200〜l500°Cの温度で焼成することに
よって製作される。
The insulating base 1 and the lid 2 are made of a forsterite sintered body or a zirconia sintered body, and are placed in a press mold having a shape corresponding to the insulating base 1 and the lid 2 as shown in FIG. In the case of stellite sintered bodies, raw material powders such as magnesia (MgO) and silica (SiOz) are used.
In the case of zirconia sintered bodies, zirconium oxide (ZrO
It is manufactured by filling raw material powder such as z), ittria (Y2O2), molding by applying constant pressure, and then firing the molded product at a temperature of about 1200 to 1500°C.

尚、前記絶縁基体1及び蓋体2を形成するフォルステラ
イト質焼結体もしくはジルコニア質焼結体はその熱膨張
係数が100乃至110 xlO−’/ ”cであり、
後述する封止用ガラス部材の熱膨張係数との関係におい
て絶縁基体1及び蓋体2と封止用ガラス部材間に大きな
熱膨張の差が生じることはない。
The forsterite sintered body or the zirconia sintered body forming the insulating base 1 and the lid 2 have a coefficient of thermal expansion of 100 to 110 xlO-'/''c,
In relation to the coefficient of thermal expansion of the sealing glass member, which will be described later, there is no large difference in thermal expansion between the insulating base 1 and the lid 2 and the sealing glass member.

また前記絶縁基体1及び蓋体2にはその相対向する主面
に封止用のガラス部材6が予め被着形成されており、該
絶縁基体l及び蓋体2の各々に被着されている封止用ガ
ラス部材6を加熱溶融させ一体化させることにより絶縁
容器3内の半導体素子4を気密に封止する。
Further, a sealing glass member 6 is formed in advance on the opposing main surfaces of the insulating base 1 and the lid 2, and is adhered to each of the insulating base 1 and the lid 2. The semiconductor element 4 inside the insulating container 3 is hermetically sealed by heating and melting the sealing glass member 6 to integrate it.

前記絶縁基体l及び蓋体2の相対向する主面に被着され
る封止用ガラス部材6は、シリカ60.0乃至70.0
14t%、ナトリウム、カリウムの酸化物の少なくとも
1種10.0乃至20.OWt%、酸化バリウム5.0
乃至15.OWtχより形成されるガラスから成り、上
記各成分を所定の値となるように秤量混合すると共に、
該混合粉末を1300〜1400℃の温度で加熱熔融さ
せることによって製作される。このガラス部材6の熱膨
張係数は90乃至100 xlO−’/ ’cである。
The sealing glass member 6 adhered to the opposing main surfaces of the insulating base 1 and the lid 2 is made of silica 60.0 to 70.0.
14t%, at least one of sodium and potassium oxides 10.0 to 20. OWt%, barium oxide 5.0
to 15. It is made of glass formed from OWtχ, and the above components are weighed and mixed to a predetermined value, and
It is manufactured by heating and melting the mixed powder at a temperature of 1300 to 1400°C. The coefficient of thermal expansion of this glass member 6 is 90 to 100 xlO-'/'c.

前記封止用ガラス部材6は、その熱膨張係数が90乃至
100 xlO−’/ ”cであり、絶縁基体l及び蓋
体2の各々の熱膨張係数と近似することから絶縁基体1
及び蓋体2の各々に被着されている封止用ガラス部材6
を加熱溶融させ一体化させることにより絶縁容器3内の
半導体素子4を気密に封止する際、絶縁基体1及び蓋体
2と封止用ガラス部材6との間には両者の熱膨張係数の
相違に起因する熱応力が発生することは殆どなく、絶縁
基体1と蓋体2とを封止用ガラス部材6を介し強固に接
合することが可能となる。
The sealing glass member 6 has a thermal expansion coefficient of 90 to 100 xlO-'/''c, which is similar to the thermal expansion coefficient of each of the insulating base 1 and the lid 2.
and a sealing glass member 6 attached to each of the lid body 2
When the semiconductor element 4 in the insulating container 3 is hermetically sealed by heating and melting and integrating them, there is a gap between the insulating base 1 and the lid 2 and the sealing glass member 6, which has a coefficient of thermal expansion between them. There is almost no thermal stress caused by the difference, and it becomes possible to firmly join the insulating base 1 and the lid 2 via the sealing glass member 6.

尚、前記封止用ガラス部材6はシリカ(SiOz)が6
0.0Wtχ未満であるとガラスの結晶化が進んで絶縁
容器3の気密封止が困難となり、また70.0Wtχを
越えるとガラスの熱膨張が小さくなって絶縁基体lと蓋
体2の熱膨張と合わなくなることからシリカ(SiO□
)は60.0乃至70.0Wtχの範囲に限定される。
Note that the sealing glass member 6 is made of silica (SiOz).
If it is less than 0.0 Wtχ, crystallization of the glass will progress and it will be difficult to hermetically seal the insulating container 3, and if it exceeds 70.0 Wtχ, the thermal expansion of the glass will be small and the thermal expansion of the insulating base l and the lid 2 will be reduced. Silica (SiO□
) is limited to a range of 60.0 to 70.0 Wtχ.

またナトリウム、カリウムの酸化物が10.OWtχ未
満であるとガラスを製作する際のガラスの熔融温度が大
幅に上がって作業性が著しく悪くなり、また2o、ow
tχを越えるとガラスの耐薬品性が劣化して絶縁容器3
の気密封止の信頼性が大きく低下するためナトリウム、
カリウムの酸化物は10.0乃至20.OWtχの範囲
に限定される。
Also, sodium and potassium oxides are 10. If it is less than OWtχ, the melting temperature of the glass will increase significantly during glass production, resulting in significantly poor workability, and 2o, ow
If tχ is exceeded, the chemical resistance of the glass deteriorates and the insulation container 3
Sodium, as the reliability of hermetic sealing is greatly reduced.
Potassium oxide is 10.0 to 20. limited to the range of OWtχ.

また酸化バリウム(Bad)が5.0 WtX未満であ
るとガラスの耐薬品性が劣化して絶縁容器3の気密封止
の信頼性が大きく低下し、また15.OWtχを越える
とガラスの結晶化が進んで絶縁容器3の気密1、i止が
困難となることから酸化バリウム(Bad)は5.0乃
至15.OWtχの範囲に限定される。
Moreover, if barium oxide (Bad) is less than 5.0 WtX, the chemical resistance of the glass will deteriorate, and the reliability of hermetic sealing of the insulating container 3 will be greatly reduced. If OWtχ is exceeded, crystallization of the glass progresses, making it difficult to keep the insulating container 3 airtight. limited to the range of OWtχ.

前記封止用ガラス部材6は前述した成分から成るガラス
に適当な有機溶剤、溶媒を添加して得たガラスペースト
を従来周知の厚膜手法を採用することによって絶縁基体
1及び蓋体2の相対向する主面に被着形成される。
The sealing glass member 6 is made by applying a well-known thick film method to a glass paste obtained by adding an appropriate organic solvent or solvent to the glass made of the above-mentioned components, and thereby attaching the insulating substrate 1 and the lid 2 to each other. It is deposited and formed on the main surface facing the opposite direction.

前記絶縁基体lと蓋体2との間には導電性材料から成る
外部リード端子5が配されており、該外部リード端子5
は半導体素子4の各電極がワイヤ7を介し電気的に接続
され、外部リード端子5を外部電気回路に接続すること
によって半導体素子4が外部電気回路に接続されること
となる。
An external lead terminal 5 made of a conductive material is disposed between the insulating base l and the lid 2.
Each electrode of the semiconductor element 4 is electrically connected via the wire 7, and the semiconductor element 4 is connected to the external electric circuit by connecting the external lead terminal 5 to the external electric circuit.

前記外部リード端子5は絶縁基体1と蓋体2の相対向す
る主面に被着させた封止用ガラス部材6を溶融一体止さ
せ、絶縁容器3を気密封止する際に同時に絶縁基体1と
蓋体2との間に取着される。
The external lead terminal 5 is formed by melting and integrally bonding the sealing glass member 6 attached to the opposing main surfaces of the insulating base 1 and the lid 2, and simultaneously sealing the insulating base 1 when the insulating container 3 is hermetically sealed. and the lid body 2.

前記外部リード端子5は非磁性体金属である銅(Cu)
から成る芯体の外表面にクロム−鉄合金(CrFe合金
)を接合させたもの、或いは板状のインバー合金(36
,5WtχNi−63,5WtXFe合金)の上下面に
非磁性体金属である銅(Cu)を接合させたもの等から
成り、その透磁率は200 (CGS)以下、導電率ハ
102(IAC3)以上、熱膨張係数は100乃至11
0×10−’/ ’Cの導電性材料から成る。
The external lead terminal 5 is made of copper (Cu), which is a non-magnetic metal.
Chromium-iron alloy (CrFe alloy) is bonded to the outer surface of the core, or plate-shaped Invar alloy (36
, 5WtχNi-63, 5WtXFe alloy) with copper (Cu), which is a non-magnetic metal, bonded to the upper and lower surfaces, and has a magnetic permeability of 200 (CGS) or less, an electrical conductivity of 102 (IAC3) or more, Thermal expansion coefficient is 100 to 11
It is made of a conductive material of 0x10-'/'C.

前記外部リード端子5はその透磁率が200 (CGS
)以下であり、透磁率が低いことから外部リード端子5
に電流が流れたとしても外部リード端子5中には大きな
自己インダクタンスが発生することばなく、その結果、
前記自己インダクタンスにより誘発される逆起電力に起
因したノイズを極小となし、内部に収容する半導体素子
4を常に正常に作動させることができる。
The external lead terminal 5 has a magnetic permeability of 200 (CGS
) or less, and the magnetic permeability is low, so the external lead terminal 5
Even if a current flows through the external lead terminal 5, no large self-inductance is generated in the external lead terminal 5, and as a result,
Noise caused by the back electromotive force induced by the self-inductance can be minimized, and the semiconductor element 4 housed inside can always operate normally.

また前記外部リート端子5はその導電率が工0χ(IA
cs)以上であり、電気を流し易いことから外部リード
端子5の信号伝搬速度を極めて速いものとなすことがで
き、絶縁容器3内に収容した半導体素子4を高速駆動さ
せたとしても半導体素子4と外部電気回路との間におけ
る信号の出し入れは常に安定、且つ確実となすことがで
きる。
Further, the external lead terminal 5 has a conductivity of 0χ (IA
cs), and since it is easy to conduct electricity, the signal propagation speed of the external lead terminal 5 can be made extremely high, and even if the semiconductor element 4 housed in the insulating container 3 is driven at high speed, the semiconductor element 4 The input/output of signals between the external electric circuit and the external electric circuit can always be performed stably and reliably.

また同時に外部リード端子5の導電率が晶いことから外
部リード端子5の線幅が細くなったとしても外部リード
端子5の電気抵抗を低く抑えることができ、その結果、
外部リード端子5における信号の減衰を瓶小として内部
に収容する半導体素子4に外部電気回路から供給される
電気信号を正確に入力することができる。
At the same time, since the conductivity of the external lead terminal 5 is crystalline, even if the line width of the external lead terminal 5 becomes thin, the electrical resistance of the external lead terminal 5 can be kept low, and as a result,
The electric signal supplied from the external electric circuit can be accurately inputted to the semiconductor element 4 housed inside by reducing the attenuation of the signal at the external lead terminal 5.

また更に前記外部リート端子5はその熱膨張係数が10
0乃至110 xlO−’/ ’cであり、封止用ガラ
ス部材6の熱膨張係数と近似することから外部リード端
子5を絶縁基体1と蓋体2の間に封止用ガラス部材6を
用いて固定する際、外部リード端子5と封止用ガラス部
材6との間には両者の熱膨張係数の相違に起因する熱応
力が発生することはなく、外部リード端子5を封止用ガ
ラス部材6で強固に固定することも可能となる。
Furthermore, the external lead terminal 5 has a coefficient of thermal expansion of 10.
0 to 110 xlO-'/'c, which approximates the coefficient of thermal expansion of the sealing glass member 6. When fixing the external lead terminals 5 to the sealing glass member 6, no thermal stress is generated between the external lead terminals 5 and the sealing glass member 6 due to the difference in coefficient of thermal expansion between the two. 6 can also be firmly fixed.

かくして、この半導体素子収納用パッケージによれば絶
縁基体lの凹部底面に半導体素子4を取着固定するとと
もに該半導体素子4の各電極をボンディングワイヤ7に
より外部リード端子5に接続させ、しかる後、絶縁基体
1と蓋体2とを該絶縁基体1及び蓋体2の相対向する主
面に予め被着させておいた封止用ガラス部材6を溶融一
体止させることによって接合させ、これによって最終製
品としての半導体装置が完成する。
Thus, according to this semiconductor element storage package, the semiconductor element 4 is attached and fixed to the bottom surface of the recess of the insulating substrate l, and each electrode of the semiconductor element 4 is connected to the external lead terminal 5 by the bonding wire 7, and then, The insulating base 1 and the lid 2 are joined together by melting the sealing glass member 6 that has been previously applied to the opposing main surfaces of the insulating base 1 and the lid 2. The semiconductor device as a product is completed.

(発明の効果) 本発明の半導体素子収納用パッケージによれば、半導体
素子を収容するための絶縁容器をフォルステライト質焼
結体もしくはジルコニア質焼結体で、外部リード端子を
透磁率が200 (CGS)以下、導電率が10χ(I
AC5)以上、熱膨張係数が100乃至110×10−
’/ ”Cの金属で、ガラス部材をシリカ60.0乃至
70.0Wt%、ナトリウム、カリウムの酸化物の少な
くとも1種10.0乃至2Q、OWt%、酸化バリウム
5.0乃至15.OWtχから成るガラスで形成したこ
とから外部リード端子に電流を流したとしても該外部リ
ード端子中に大きな自己インダクタンスが発生すること
はなく、その結果、前記自己インダクタンスにより誘発
される逆起電力に起因したノイズを極小となし、内部に
収容する半導体素子を常に正常に作動させることが可能
となる。
(Effects of the Invention) According to the semiconductor device storage package of the present invention, the insulating container for accommodating the semiconductor device is made of a forsterite sintered body or a zirconia sintered body, and the external lead terminal has a magnetic permeability of 200 ( CGS) or less, the conductivity is 10χ(I
AC5) or higher, thermal expansion coefficient 100 to 110×10-
'/''C metal, the glass member is made of silica 60.0 to 70.0 Wt%, at least one of sodium and potassium oxides 10.0 to 2Q, OWt%, barium oxide 5.0 to 15.OWtχ Since it is made of glass, even if a current is passed through the external lead terminal, a large self-inductance will not be generated in the external lead terminal, and as a result, noise caused by the back electromotive force induced by the self-inductance will be reduced. This makes it possible to keep the semiconductor element housed inside the device normally operating at all times.

また外部リード端子の信号伝搬速度を極めて速いものと
なすことができ、絶縁容器内に収容した半導体素子を高
速駆動させたとしても半導体素子と外部電気回路との間
における信号の出し入れを安定、且つ確実となすことが
可能となる。
In addition, the signal propagation speed of the external lead terminal can be made extremely high, so that even if the semiconductor element housed in the insulating container is driven at high speed, the signal can be stably input and output between the semiconductor element and the external electric circuit. It becomes possible to do so with certainty.

更に外部リード端子の線幅が細くなったとしても外部リ
ード端子の電気抵抗を低く抑えることができ、その結果
、外部リード端子における信号の減衰を極小として内部
に収容する半導体素子に外部電気回路から供給される電
気信号を正確に入力することができる。
Furthermore, even if the line width of the external lead terminal becomes thinner, the electrical resistance of the external lead terminal can be kept low, and as a result, the attenuation of the signal at the external lead terminal is minimized, and the external electrical circuit is connected to the semiconductor element housed inside. The supplied electrical signal can be input accurately.

また更に前記外部リード端子はその熱膨張係数が絶縁基
体、蓋体及び封止用ガラス部材の各々の熱膨張係数と近
似し、絶縁基体と蓋体との間に外部リード端子を挟み、
各々を封止用ガラス部材で取着接合したとしても絶縁基
体及び蓋体と封止用ガラス部材との間、外部リード端子
と封止用ガラス部材との間のいずれにも熱膨張係数の相
違に起因する熱応力は発生せず、すべてを強固に取着接
合することも可能となる。
Furthermore, the external lead terminal has a coefficient of thermal expansion that approximates each of the coefficients of thermal expansion of the insulating base, the lid, and the sealing glass member, and the external lead terminal is sandwiched between the insulating base and the lid,
Even if each is attached and bonded with a glass sealing member, there are differences in the coefficient of thermal expansion between the insulating base and lid and the glass sealing member, and between the external lead terminal and the glass sealing member. There is no thermal stress caused by this, and it is possible to firmly attach and join everything.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体素子収納用パッケージの一実施
例を示す断面図、第2図は第1図に示すパッケージの絶
縁基体上面より見た平面図である。 1・・絶縁基体  2 ・・蓋体 3・・絶縁容器  5 ・・外部リード端子6・・封止
用ガラス部材
FIG. 1 is a sectional view showing an embodiment of the semiconductor element storage package of the present invention, and FIG. 2 is a plan view of the package shown in FIG. 1, viewed from the top surface of the insulating base. 1...Insulating base 2...Lid 3...Insulating container 5...External lead terminal 6...Glass member for sealing

Claims (1)

【特許請求の範囲】[Claims] 内部に半導体素子を収容するための空所を有する絶縁容
器に外部リード端子をガラス部材を介して取着して成る
半導体素子収納用パッケージにおいて、前記絶縁容器を
フォルステライト質焼結体もしくはジルコニア質焼結体
で、外部リード端子を透磁率200(CGS)以下、熱
膨張係数100乃至110×10^−^7/℃、導電率
10%(IACS)以上の金属で、ガラス部材をシリカ
60.0乃至70.0Wt%、ナトリウム、カリウムの
酸化物の少なくとも1種10.0乃至20.0Wt%、
酸化バリウム5.0乃至15.0Wt%から成るガラス
で形成したことを特徴とする半導体素子収納用パッケー
ジ。
In a semiconductor device storage package in which external lead terminals are attached via a glass member to an insulating container having a cavity for accommodating a semiconductor device inside, the insulating container is made of a forsterite sintered body or a zirconia sintered body. The external lead terminal is a sintered body, the external lead terminal is made of metal with a magnetic permeability of 200 (CGS) or less, a thermal expansion coefficient of 100 to 110 x 10^-^7/°C, and an electrical conductivity of 10% (IACS) or more, and the glass member is made of silica 60. 0 to 70.0 Wt%, at least one of sodium and potassium oxides 10.0 to 20.0 Wt%,
A package for housing a semiconductor element, characterized in that it is formed of glass comprising 5.0 to 15.0 Wt% of barium oxide.
JP1312728A 1989-08-25 1989-11-30 Package for storing semiconductor elements Expired - Lifetime JP2742618B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1312728A JP2742618B2 (en) 1989-11-30 1989-11-30 Package for storing semiconductor elements
US07/573,406 US5057905A (en) 1989-08-25 1990-08-24 Container package for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1312728A JP2742618B2 (en) 1989-11-30 1989-11-30 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH03173160A true JPH03173160A (en) 1991-07-26
JP2742618B2 JP2742618B2 (en) 1998-04-22

Family

ID=18032709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1312728A Expired - Lifetime JP2742618B2 (en) 1989-08-25 1989-11-30 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP2742618B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50146899A (en) * 1974-05-16 1975-11-25
JPS53123080A (en) * 1977-04-02 1978-10-27 Ngk Insulators Ltd Circuit substrate and ceramic package assembly and method of producing same
JPS6265954A (en) * 1985-09-18 1987-03-25 Nippon Electric Glass Co Ltd Borosilicate glass for sealing alumina
JPS63185318U (en) * 1987-05-22 1988-11-29
JPS645041A (en) * 1987-06-29 1989-01-10 Shinko Electric Ind Co Manufacture of ceramic body having superconducting circuit pattern

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50146899A (en) * 1974-05-16 1975-11-25
JPS53123080A (en) * 1977-04-02 1978-10-27 Ngk Insulators Ltd Circuit substrate and ceramic package assembly and method of producing same
JPS6265954A (en) * 1985-09-18 1987-03-25 Nippon Electric Glass Co Ltd Borosilicate glass for sealing alumina
JPS63185318U (en) * 1987-05-22 1988-11-29
JPS645041A (en) * 1987-06-29 1989-01-10 Shinko Electric Ind Co Manufacture of ceramic body having superconducting circuit pattern

Also Published As

Publication number Publication date
JP2742618B2 (en) 1998-04-22

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