JP2742613B2 - Package for storing semiconductor elements - Google Patents
Package for storing semiconductor elementsInfo
- Publication number
- JP2742613B2 JP2742613B2 JP1308610A JP30861089A JP2742613B2 JP 2742613 B2 JP2742613 B2 JP 2742613B2 JP 1308610 A JP1308610 A JP 1308610A JP 30861089 A JP30861089 A JP 30861089A JP 2742613 B2 JP2742613 B2 JP 2742613B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- external lead
- lead terminal
- package
- lid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体素子を収容する半導体素子収納用パッ
ケージの改良に関するものである。Description: TECHNICAL FIELD The present invention relates to an improvement in a semiconductor device housing package for housing a semiconductor device.
（従来の技術） 従来、半導体素子を収容するためのパッケージ、特に
ガラスの溶着によって封止するガラス封止型半導体素子
収納用パッケージは、絶縁基体と蓋体とから成り、内部
に半導体素子を収容する空所を有する絶縁容器と、該容
器内に収容される半導体素子を外部電気回路に電気的に
接続するための外部リード端子とから構成されており、
絶縁基体及び蓋体の相対向する主面に予め封止用のガラ
ス部材を被着形成すると共に、絶縁基体主面に外部リー
ド端子を固定し、半導体素子の各電極と外部リード端子
とをワイヤボンド接続した後、絶縁基体及び蓋体のそれ
ぞれに被着させた封止用のガラス部材を溶融一体化させ
ることによって内部に半導体素子を気密に封止してい
る。(Prior Art) Conventionally, a package for accommodating a semiconductor element, particularly a package for accommodating a glass-encapsulated semiconductor element sealed by welding glass, includes an insulating base and a lid, and accommodates the semiconductor element inside. And an external lead terminal for electrically connecting a semiconductor element housed in the container to an external electric circuit,
A glass member for sealing is applied in advance on the opposing main surfaces of the insulating base and the lid, and external lead terminals are fixed on the main surface of the insulating base, and each electrode of the semiconductor element and the external lead terminal are wired. After the bond connection, the semiconductor element is hermetically sealed inside by fusing and integrating a sealing glass member attached to each of the insulating base and the lid.
（発明が解決しようとする課題） しかし乍ら、この従来のガラス封止型半導体素子収納
用パッケージは通常、外部リード端子がコバール（29Wt
％ Ni−16Wt％ Co−55Wt％ Fe合金）や42Alloy（42Wt％
Ni−58Wt％ Fe合金）の導電性材料から成っており、該
コバールや42Alloy等は導電率が低いことから以下に述
べる欠点を有する。(Problems to be Solved by the Invention) However, this conventional package for housing a glass-sealed semiconductor element usually has an external lead terminal of Kovar (29 Wt).
% Ni-16Wt% Co-55Wt% Fe alloy) and 42Alloy (42Wt%
Ni-58Wt% Fe alloy), and Kovar and 42Alloy have the following disadvantages due to their low conductivity.
即ち、 コバールや42Alloyはその導電率が3.0〜3.5％（IAC
S）と低い。そのためこのコバールや42Alloy等から成る
外部リード端子に信号を伝搬させた場合、信号の伝搬速
度が極めて遅いものとなり、高速駆動を行う半導体素子
はその収容が不可となってしまう、 半導体素子収納用パッケージの内部に収容する半導体
素子の高密度化、高集積化の進展に伴い、半導体素子の
電極数が大幅に増大しており、半導体素子の各電極を外
部電気回路に接続する外部リード端子の線幅も極めて細
くなってきている。そのため外部リード端子は上記に
記載のコバールや42Alloyの導電率が低いことと相俊っ
て電気抵抗が極めて大きなものになってきており、外部
リード端子に信号を伝搬させると、該外部リード端子の
電気抵抗に起因して信号が大きく減衰し、内部に収容す
る半導体素子に信号を正確に入力することができず、半
導体素子に誤動作を生じさせてしまう、 等の欠点を有していた。That is, Kovar and 42Alloy have a conductivity of 3.0 to 3.5% (IAC
S) and low. Therefore, when a signal is propagated to an external lead terminal made of Kovar or 42Alloy, the signal propagation speed becomes extremely slow, and semiconductor devices that perform high-speed driving cannot be accommodated. The number of electrodes of a semiconductor element has increased significantly with the progress of higher density and higher integration of semiconductor elements housed inside the semiconductor device, and wires of external lead terminals for connecting each electrode of the semiconductor element to an external electric circuit. The width has also become extremely narrow. For this reason, the external lead terminal has become extremely large in electrical resistance in tandem with the low conductivity of Kovar and 42 Alloy described above, and when a signal is propagated to the external lead terminal, the external lead terminal becomes The signal is greatly attenuated due to the electric resistance, and the signal cannot be accurately input to the semiconductor element housed therein, thereby causing a malfunction in the semiconductor element.
（発明の目的） 本発明は上記欠点に鑑み案出されたもので、その目的
は外部リード端子における信号の減衰を極小となし、内
部に収容する半導体素子への信号の入出力を確実に行う
ことを可能として半導体素子を長期間にわたり正常、且
つ安定に作動させることができる半導体素子収納用パッ
ケージを提供することにある。(Object of the Invention) The present invention has been devised in view of the above-mentioned drawbacks, and an object of the present invention is to minimize signal attenuation at an external lead terminal and to reliably input and output a signal to a semiconductor element housed therein. It is therefore an object of the present invention to provide a semiconductor element storage package that enables the semiconductor element to operate normally and stably for a long period of time.
また本発明の他の目的は高速駆動を行う半導体素子を
収容することができる半導体素子収納用パッケージを提
供することにある。Another object of the present invention is to provide a semiconductor element housing package capable of housing a semiconductor element which operates at high speed.
（課題を解決するための手段） 本発明は内部に半導体素子を収容するための空所を有
する絶縁容器に外部リード端子をガラス部材を介して取
着して成る半導体素子収納用パッケージにおいて、前記
絶縁容器をフォルステライト質焼結体もしくはジルコニ
ア質焼結体で、外部リード端子を熱膨張係数95乃至110
×10-7/℃、導電率12％（IACS）以上の金属で、ガラス
部材をシリカ60.0乃至70.0Wt％、ナトリウム、カリウム
の酸化物の少なくとも１種10.0乃至20.0Wt％、酸化バリ
ウム（BaO）5.0乃至15.0Wt％から成るガラスで形成した
ことを特徴とするものである。(Means for Solving the Problems) The present invention relates to a package for housing semiconductor elements, wherein external lead terminals are attached via a glass member to an insulating container having a space for housing semiconductor elements therein. The insulating container is a forsterite-based sintered body or a zirconia-based sintered body, and the external lead terminals have a coefficient of thermal expansion of 95 to 110.
X10 -7 / ° C, metal with conductivity of 12% (IACS) or higher, glass member made of silica 60.0 to 70.0 Wt%, at least one of sodium and potassium oxides 10.0 to 20.0 Wt%, barium oxide (BaO) It is characterized by being formed of glass of 5.0 to 15.0 Wt%.
（実施例） 次に本発明を添付図面に基づき詳細に説明する。(Example) Next, the present invention will be described in detail with reference to the accompanying drawings.
第１図及び第２図は本発明の半導体素子収納用パッケ
ージの一実施例を示し、１は絶縁基体、２は蓋体であ
る。この絶縁基体１と蓋体２とにより絶縁容器３が構成
される。1 and 2 show an embodiment of a package for accommodating a semiconductor element according to the present invention, wherein 1 is an insulating base and 2 is a lid. The insulating container 3 is constituted by the insulating base 1 and the lid 2.
前記絶縁基体１及び蓋体２はそれぞれの中央部に半導
体素子を収容する空所を形成するための凹部が設けてあ
り、絶縁基体１の凹部底面には半導体素子４が樹脂、ガ
ラス、ロウ剤等の接着剤を介し取着固定される。The insulating base 1 and the lid 2 are each provided with a concave portion for forming a space for accommodating a semiconductor element at the center thereof, and the semiconductor element 4 is formed of resin, glass, brazing agent on the bottom surface of the concave portion of the insulating base 1. It is attached and fixed via an adhesive such as.
前記絶縁基体１及び蓋体２はフォルステライト質焼結
体もしくはジルコニア質焼結体から成り、第１図に示す
ような絶縁基体１及び蓋体２に対応した形状を有するプ
レス型内に、フォルステライト質焼結体の場合はマグネ
シア（MgO）、シリカ（SiO2）等の原料粉末を、ジルコ
ニア質焼結体の場合は酸化ジルコニウム（ZrO2）、イッ
トリア（Y2O3）等の原料粉末を充填させるとともに一定
圧力を印加して成形し、しかる後、成形品を約1200〜15
00℃の温度で焼成することによって製作される。The insulating base 1 and the lid 2 are made of a forsterite-based sintered body or a zirconia-based sintered body, and are placed in a press die having a shape corresponding to the insulating base 1 and the lid 2 as shown in FIG. Raw material powders such as magnesia (MgO) and silica (SiO 2 ) for stellite sintered bodies, and raw material powders such as zirconium oxide (ZrO 2 ) and yttria (Y 2 O 3 ) for zirconia sintered bodies And molding by applying a constant pressure.
It is manufactured by firing at a temperature of 00 ° C.
尚、前記絶縁基体１及び蓋体２を形成するフォルステ
ライト質焼結体もしくはジルコニア質焼結体はその熱膨
張係数が100乃至110×10-7/℃であり、後述する封止用
ガラス部材の熱膨張係数との関係において絶縁基体１及
び蓋体２と封止用ガラス部材間に大きな熱膨張の差が生
じることはない。The forsterite-based sintered body or zirconia-based sintered body forming the insulating base 1 and the lid 2 has a thermal expansion coefficient of 100 to 110 × 10 −7 / ° C., and a sealing glass member described later. There is no large difference in thermal expansion between the insulating base 1 and the lid 2 and the sealing glass member in relation to the thermal expansion coefficient of
また前記絶縁基体１及び蓋体２にはその相対向する主
面に封止用のガラス部材６が予め被着形成されており、
該絶縁基体１及び蓋体２の各々に被着されている封止用
ガラス部材６を加熱溶融させ一体化させることにより絶
縁容器３内の半導体素子４を気密に封止する。Further, a glass member 6 for sealing is previously formed on the opposing main surfaces of the insulating base 1 and the lid 2.
The semiconductor element 4 in the insulating container 3 is hermetically sealed by heating and melting the sealing glass member 6 attached to each of the insulating base 1 and the lid 2 to be integrated.
前記絶縁基体１及び蓋体２の相対向する主面に被着さ
れる封止用ガラス部材６は、シリカ60.0乃至70.0Wt％、
ナトリウム、カリウムの酸化物の少なくとも１種10.0乃
至20.0Wt％、酸化バリウム5.0乃至15.0Wt％より形成さ
れるガラスから成り、上記各成分を所定の値となるよう
に秤量混合すると共に、該混合粉末を1300〜1400℃の温
度で加熱溶融させることによって製作される。このガラ
ス部材６の熱膨張係数は90乃至100×10-7/℃である。The sealing glass member 6 attached to the opposing main surfaces of the insulating base 1 and the lid 2 is made of silica of 60.0 to 70.0 Wt%,
It is made of glass formed of at least one of sodium and potassium oxides of 10.0 to 20.0 Wt% and barium oxide of 5.0 to 15.0 Wt%. The above components are weighed and mixed so as to have predetermined values, and the mixed powder is mixed. Is manufactured by heating and melting at a temperature of 1300 to 1400 ° C. The glass member 6 has a coefficient of thermal expansion of 90 to 100 × 10 −7 / ° C.
前記封止用ガラス部材６は、その熱膨張係数が90乃至
100×10-7/℃であり、絶縁基体１及び蓋体２の各々の熱
膨張係数と近似することから絶縁基体１及び蓋体２の各
々に被着されている封止用ガラス部材６を加熱溶融させ
一体化させることにより絶縁容器３内の半導体素子４を
気密に封止する際、絶縁基体１及び蓋体２と封止用ガラ
ス部材６との間には両者の熱膨張係数の相違に起因する
熱応力が発生することは殆どなく、絶縁基体１と蓋体２
とを封止用ガラス部材６を介し強固に接合することが可
能となる。The sealing glass member 6 has a thermal expansion coefficient of 90 to 90.
Since it is 100 × 10 −7 / ° C. and approximates the thermal expansion coefficients of the insulating base 1 and the lid 2, the sealing glass member 6 attached to each of the insulating base 1 and the lid 2 is When the semiconductor element 4 in the insulating container 3 is air-tightly sealed by heat melting and integrating, the difference in the thermal expansion coefficient between the insulating base 1 and the lid 2 and the sealing glass member 6 is caused. Is hardly generated due to the heat, the insulating base 1 and the lid 2
Can be firmly joined via the sealing glass member 6.
尚、前記封止用ガラス部材６はシリカ（SiO2）が60.0
Wt％未満であるとガラスの結晶化が進んで絶縁容器３の
気密封止が困難となり、また70.0Wt％を越えるとガラス
の熱膨張が小さくなって絶縁基体１と蓋体２の熱膨張と
合わなくなることからシリカ（SiO2）は60.0乃至70.0Wt
％の範囲に限定される。The sealing glass member 6 is made of silica (SiO 2 ) of 60.0%.
If it is less than Wt%, the crystallization of the glass proceeds and it becomes difficult to hermetically seal the insulating container 3, and if it exceeds 70.0Wt%, the thermal expansion of the glass becomes small, and the thermal expansion of the insulating base 1 and the lid 2 is reduced. 60.0 to 70.0 Wt for silica (SiO 2 )
%.
またナトリウム、カリウムの酸化物が10.0Wt％未満で
あるとガラスを製作する際のガラスの溶融温度が大幅に
上がって作業性が著しく悪くなり、また20.0Wt％を越え
るとガラスの耐薬品性が劣化して絶縁容器３の気密封止
の信頼性が大きく低下するためナトリウム、カリウムの
酸化物は10.0乃至20.0Wt％の範囲に限定される。If the content of sodium and potassium oxides is less than 10.0 Wt%, the melting temperature of the glass at the time of manufacturing the glass is greatly increased, and the workability is significantly deteriorated. If it exceeds 20.0 Wt%, the chemical resistance of the glass is reduced. Since the reliability of the hermetic sealing of the insulating container 3 is greatly reduced due to deterioration, the oxides of sodium and potassium are limited to the range of 10.0 to 20.0 Wt%.
また酸化バリウム（BaO）が5.0Wt％未満であるとガラ
スの耐薬品性が劣化して絶縁容器３の気密封止の信頼性
が大きく低下し、また15.0Wt％を越えるとガラスの結晶
化が進んで絶縁容器３の気密封止が困難となることから
酸化バリウム（BaO）は5.0乃至15.0Wt％の範囲に限定さ
れる。When barium oxide (BaO) is less than 5.0 Wt%, the chemical resistance of the glass is deteriorated, and the reliability of hermetic sealing of the insulating container 3 is greatly reduced. Barium oxide (BaO) is limited to the range of 5.0 to 15.0 Wt% because it becomes difficult to hermetically seal the insulating container 3.
前記封止用ガラス部材６は前述した成分から成るガラ
スに適当な有機溶剤、溶媒を添加して得たガラスペース
トを従来周知の厚膜手法を採用することによって絶縁基
体１及び蓋体２の相対向する主面に被着形成される。The sealing glass member 6 is made of a glass paste obtained by adding a suitable organic solvent and a solvent to the glass composed of the above-described components, by employing a conventionally known thick-film technique, by using a conventionally known thick-film technique. It is formed on the opposite main surface.
前記絶縁基体１と蓋体２との間には導電性材料から成
る外部リード端子５が配されており、該外部リード端子
５は半導体素子４の各電極がワイヤ７を介し電気的に接
続され、外部リード端子５を外部電気回路に接続するこ
とによって半導体素子４が外部電気回路に接続されるこ
ととなる。An external lead terminal 5 made of a conductive material is disposed between the insulating base 1 and the lid 2. The external lead terminal 5 is electrically connected to each electrode of the semiconductor element 4 via a wire 7. By connecting the external lead terminal 5 to an external electric circuit, the semiconductor element 4 is connected to the external electric circuit.
前記外部リード端子５は絶縁基体１と蓋体２の相対向
する主面に被着させた封止用ガラス部材６を溶融一体化
させ、絶縁容器３を気密封止する際に同時に絶縁基体１
と蓋体２との間に取着される。The external lead terminals 5 are formed by melting and integrating a sealing glass member 6 attached to the opposing main surfaces of the insulating base 1 and the lid 2, and simultaneously sealing the insulating container 3 with the insulating base 1.
And the cover 2.
前記外部リード端子５は非磁性体金属である銅（Cu）
から成る芯体の外表面にニッケル−鉄合金（Ni−Fe合
金）を接合させたもの等から成り、その導電率は12％
（IACS）以上、熱膨張係数は95乃至110×10-7/℃の導電
性材料から成る。The external lead terminal 5 is made of a non-magnetic metal such as copper (Cu).
Made of nickel-iron alloy (Ni-Fe alloy) joined to the outer surface of a core made of
(IACS) As described above, the conductive material has a coefficient of thermal expansion of 95 to 110 × 10 −7 / ° C.
前記外部リード端子５はその導電率が12％（IACS）以
上であり、電気を流し易いことから外部リード端子５の
信号伝搬速度を極めて速いものとなすことができ、絶縁
容器３内に収容した半導体素子４を高速駆動させたとし
ても半導体素子４と外部電気回路との間における信号の
出し入れは常に安定、且つ確実となすことができる。The external lead terminal 5 has an electrical conductivity of 12% (IACS) or more, and since it is easy to conduct electricity, the signal propagation speed of the external lead terminal 5 can be made extremely high. Even when the semiconductor element 4 is driven at a high speed, it is possible to always stably and reliably send and receive signals between the semiconductor element 4 and an external electric circuit.
また外部リード端子５の導電率が高いことから外部リ
ード端子５の線幅が細くなったとしても外部リード端子
５の電気抵抗を低く抑えることができ、その結果、外部
リード端子５における信号の減衰を極小として内部に収
容する半導体素子４に外部電気回路から供給される電気
信号を正確に入力することができる。Further, since the electrical conductivity of the external lead terminal 5 is high, the electrical resistance of the external lead terminal 5 can be kept low even if the line width of the external lead terminal 5 is reduced, and as a result, signal attenuation at the external lead terminal 5 is achieved. The electric signal supplied from the external electric circuit can be accurately input to the semiconductor element 4 housed therein with the minimum value.
更に前記外部リード端子５はその熱膨張係数が95乃至
110×10-7/℃であり、封止用ガラス部材６の熱膨張係数
と近似することから外部リード端子５を絶縁基体１と蓋
体２の間に封止用ガラス部材６を用いて固定する際、外
部リード端子５と封止用ガラス部材６との間には両者の
熱膨張係数の相違に起因する熱応力が発生することはな
く、外部リード端子５を封止用ガラス部材６で強固に固
定することも可能となる。Further, the external lead terminal 5 has a thermal expansion coefficient of 95 to
The external lead terminal 5 is fixed between the insulating base 1 and the lid 2 using the sealing glass member 6 because it is 110 × 10 −7 / ° C. and is close to the thermal expansion coefficient of the sealing glass member 6. At this time, no thermal stress is generated between the external lead terminal 5 and the sealing glass member 6 due to the difference in the coefficient of thermal expansion between the external lead terminal 5 and the sealing glass member 6. It becomes possible to fix firmly.
かくして、この半導体素子収納用パッケージによれば
絶縁基体１の凹部底面に半導体素子４を取着固定すると
ともに該半導体素子４の各電極をボンディングワイヤ７
により外部リード端子５に接続させ、しかる後、絶縁基
体１と蓋体２とを該絶縁基体１及び蓋体２の相対向する
主面に予め被着させておいた封止用ガラス部材６を溶融
一体化させることによって接合させ、これによって最終
製品としての半導体装置が完成する。Thus, according to the package for accommodating the semiconductor element, the semiconductor element 4 is attached and fixed to the bottom surface of the concave portion of the insulating base 1 and each electrode of the semiconductor element 4 is connected to the bonding wire 7.
After that, the sealing glass member 6 in which the insulating substrate 1 and the lid 2 are previously adhered to the opposing main surfaces of the insulating substrate 1 and the lid 2 is removed. The semiconductor device as a final product is completed by joining by melting and integrating.
（発明の効果） 本発明の半導体素子収納用パッケージによれば、半導
体素子を収容するための絶縁容器をフォルステライト質
焼結体もしくはジルコニア質焼結体で、外部リード端子
を導電率が12（IACS）以上、熱膨張係数95乃至110×10
-7/℃の金属で、ガラス部材をシリカ60.0乃至70.0Wt
％、ナトリウム、カリウムの酸化物の少なくとも１種1
0.0乃至20.0Wt％、酸化バリウム（BaO）5.0乃至15.0Wt
％から成るガラスで形成したことから外部リード端子の
信号伝搬速度を極めて速いものとなすことができ、絶縁
容器内に収容した半導体素子を高速駆動させたとしても
半導体素子と外部電気回路との間における信号の出し入
れを安定、且つ確実となすことが可能となる。(Effect of the Invention) According to the package for housing a semiconductor element of the present invention, the insulating container for housing the semiconductor element is a forsterite-based sintered body or a zirconia-based sintered body, and the external lead terminals have a conductivity of 12 ( IACS) or higher, coefficient of thermal expansion 95 to 110 × 10
-7 / ℃ metal, glass member silica 60.0 ~ 70.0Wt
%, At least one of sodium and potassium oxides 1
0.0 to 20.0 Wt%, barium oxide (BaO) 5.0 to 15.0 Wt
%, The signal propagation speed of the external lead terminals can be made extremely high. Even if the semiconductor element housed in the insulating container is driven at a high speed, the distance between the semiconductor element and the external electric circuit can be increased. Can be made stable and reliable.
また外部リード端子の線幅が細くなったとしても外部
リード端子の電気抵抗を低く抑えることができ、その結
果、外部リード端子における信号の減衰を極小として内
部に収容する半導体素子に外部電気回路から供給される
電気信号を正確に入力することができる。Also, even if the line width of the external lead terminal is reduced, the electric resistance of the external lead terminal can be kept low. The supplied electric signal can be input accurately.
更に前記外部リード端子はその熱膨張係数が絶縁基
体、蓋体及び封止用ガラス部材の各々の熱膨張係数と近
似し、絶縁基体と蓋体との間に外部リード端子を挟み、
各々を封止用ガラス部材で取着接合したとしても絶縁基
体及び蓋体と封止用ガラス部材との間、外部リード端子
と封止用ガラス部材との間のいずれにも熱膨張係数の相
違に起因する熱応力は発生せず、すべてを強固に取着接
合することも可能となる。Further, the thermal expansion coefficient of the external lead terminal approximates the thermal expansion coefficient of each of the insulating base, the lid and the sealing glass member, and sandwiches the external lead terminal between the insulating base and the lid,
Even if each of them is attached and bonded with a sealing glass member, the thermal expansion coefficient is different between the insulating base and the lid and the sealing glass member, and between the external lead terminal and the sealing glass member. No thermal stress is caused by this, and it is possible to firmly attach and join all of them.
第１図は本発明の半導体素子収納用パッケージの一実施
例を示す断面図、第２図は第１図に示すパッケージの絶
縁基体上面より見た平面図である。 １……絶縁基体、２……蓋体 ３……絶縁容器 ５……外部リード端子 ６……封止用ガラス部材FIG. 1 is a cross-sectional view showing one embodiment of a package for housing a semiconductor element according to the present invention, and FIG. 2 is a plan view of the package shown in FIG. DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Lid 3 ... Insulating container 5 ... External lead terminal 6 ... Glass member for sealing
Claims (1)
有する絶縁容器に外部リード端子をガラス部材を介して
取着して成る半導体素子収納用パッケージにおいて、前
記絶縁容器をフォルステライト質焼結体もしくはジルコ
ニア質焼結体で、外部リード端子を熱膨張係数95乃至11
0×10-7/℃、導電率12％（IACS）以上の金属で、ガラス
部材をシリカ60.0乃至70.0Wt％、ナトリウム、カリウム
の酸化物の少なくとも１種10.0乃至20.0Wt％、酸化バリ
ウム5.0乃至15.0Wt％から成るガラスで形成したことを
特徴とする半導体素子収納用パッケージ。1. A package for storing semiconductor elements, wherein an external lead terminal is attached via a glass member to an insulating container having a space for accommodating a semiconductor element therein. The external lead terminal is a thermal expansion coefficient of 95 to 11
0 × 10 −7 / ° C., conductivity 12% (IACS) or more metal, glass member 60.0 to 70.0 Wt% of silica, at least one of sodium and potassium oxides 10.0 to 20.0 Wt%, barium oxide 5.0 to A package for housing a semiconductor element, wherein the package is made of 15.0 Wt% glass.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1308610A JP2742613B2 (en) | 1989-11-27 | 1989-11-27 | Package for storing semiconductor elements |
| US07/574,472 US5168126A (en) | 1989-08-25 | 1990-08-27 | Container package for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1308610A JP2742613B2 (en) | 1989-11-27 | 1989-11-27 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03167861A JPH03167861A (en) | 1991-07-19 |
| JP2742613B2 true JP2742613B2 (en) | 1998-04-22 |
Family
ID=17983116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1308610A Expired - Lifetime JP2742613B2 (en) | 1989-08-25 | 1989-11-27 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2742613B2 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5521968B2 (en) * | 1974-05-16 | 1980-06-13 | ||
| JPS53123080A (en) * | 1977-04-02 | 1978-10-27 | Ngk Insulators Ltd | Circuit substrate and ceramic package assembly and method of producing same |
| JPS6265954A (en) * | 1985-09-18 | 1987-03-25 | Nippon Electric Glass Co Ltd | Borosilicate glass for sealing alumina |
| JPH0516730Y2 (en) * | 1987-05-22 | 1993-05-06 | ||
| JPS645041A (en) * | 1987-06-29 | 1989-01-10 | Shinko Electric Ind Co | Manufacture of ceramic body having superconducting circuit pattern |
-
1989
- 1989-11-27 JP JP1308610A patent/JP2742613B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03167861A (en) | 1991-07-19 |
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