JPH02283046A - Circuit substrate - Google Patents
Circuit substrateInfo
- Publication number
- JPH02283046A JPH02283046A JP1105029A JP10502989A JPH02283046A JP H02283046 A JPH02283046 A JP H02283046A JP 1105029 A JP1105029 A JP 1105029A JP 10502989 A JP10502989 A JP 10502989A JP H02283046 A JPH02283046 A JP H02283046A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor element
- insulating layer
- circuit substrate
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title abstract 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野コ
本発明は、ギヤングボンディング用の回路基板のインナ
ーリード構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inner lead structure of a circuit board for gigantic bonding.
[従来の技術]
従来は、第1図(α)、(1!l)に示すように、絶縁
層5上に導体層1を有し、半導体素子40図示してない
電極との接続用インナーリード2より[発明が解決しよ
うとする課題]
近年の世界の電子機器の市場動向を見ると、小型化・微
細化の要求が年々高まってきているが、従来の回路基板
のインナーリード構造では、インナーリード巾を例えば
50μmとするとインナーリードとインナーリードの隙
間も最低50μm程度を必要とする為、インナーリード
ピッチは100μm程度となる。従来の回路基板製造で
は、前記100μmピッチ程度が限界とされていた。そ
の為、半導体素子のサイズによりピン数は限定され、更
に多ピン化をするには、半導体兼子のサイズを大きくし
なければならなかった。[Prior Art] Conventionally, as shown in FIGS. 1(α) and (1!l), a conductor layer 1 is provided on an insulating layer 5, and a semiconductor element 40 has an inner layer for connecting to an electrode (not shown). From Lead 2 [Problems to be Solved by the Invention] Looking at the recent market trends of electronic devices around the world, the demand for miniaturization and miniaturization is increasing year by year, but the inner lead structure of the conventional circuit board is If the inner lead width is, for example, 50 μm, the gap between the inner leads also needs to be at least about 50 μm, so the inner lead pitch is about 100 μm. In conventional circuit board manufacturing, the pitch of about 100 μm was considered to be the limit. Therefore, the number of pins is limited depending on the size of the semiconductor element, and in order to further increase the number of pins, it is necessary to increase the size of the semiconductor element.
そこで、本発明は、従来のこのような課題を解決する為
に、半導体素子のサイズは従来と同様或いは小型化して
、半導体素子の電極を千鳥状に配列し、回路基板のイン
ナーリードな表裏2層とする事により小型化、微細化を
はかる事を目的としている。Therefore, in order to solve these conventional problems, the present invention has made the size of the semiconductor element the same or smaller than the conventional one, arranged the electrodes of the semiconductor element in a staggered manner, and arranged the electrodes of the semiconductor element on the front and back sides of the inner lead of the circuit board. The aim is to achieve miniaturization and miniaturization by forming layers.
[課題を解決するための手段]
上記課題を解決するために、本発明の回路基板は、絶縁
層の表裏両面に導体層を有し、半導体素子の電極と接続
されるインナーリードが、前記導体層の表面リード及び
裏面リードにより構成され、半導体素子の千鳥状に配列
された電極とギヤングボンディングにより接続する事を
特徴とする。[Means for Solving the Problems] In order to solve the above problems, the circuit board of the present invention has conductor layers on both the front and back surfaces of the insulating layer, and the inner leads connected to the electrodes of the semiconductor element are connected to the conductor layers. It is composed of front and back leads of the layer, and is characterized by being connected to the staggered electrodes of the semiconductor element by guy-young bonding.
[実施例]
第2図(α)l(b)は、本発明の一実施例で(α)は
側面図、(b)は平面図である。[Example] Figures 2(α) and 1(b) show an embodiment of the present invention, in which (α) is a side view and (b) is a plan view.
第2図に於て、インナーリードの表面リード21は、絶
縁層6の表面に把持され、半導体素子40図示してない
内側電極と接続される。又、インナーリードの裏面リー
ド22は、前記絶縁層5の裏面に把持され、前記半導体
素子40図示してない外側電極と接続される。In FIG. 2, the surface leads 21 of the inner leads are held on the surface of the insulating layer 6 and connected to the inner electrodes of the semiconductor element 40 (not shown). Further, the back lead 22 of the inner lead is held on the back surface of the insulating layer 5, and is connected to the outside electrode (not shown) of the semiconductor element 40.
第2図の実施例は、表面リードと表面リードの間に裏面
リードを配列できる為、従来の1/2のピッチとするこ
とが可能となり、同一サイズの半導体素子でも2倍位の
ビン数とする事が可能である[発明の効果]
本発明の回路基板は、以上説明したように、絶縁層の表
裏両面に導体層を有し、半導体素子の電極と接続される
インナーリードが、前記導体層の表面リードと裏面リー
ドからなる事により、半導体素子の小型化及び回路基板
の小型化がはかれ、微細化につながる。In the embodiment shown in Fig. 2, the back side leads can be arranged between the front side leads, so the pitch can be halved compared to the conventional one, and the number of bins can be doubled even for the same size semiconductor element. [Effects of the Invention] As explained above, the circuit board of the present invention has a conductor layer on both the front and back surfaces of the insulating layer, and the inner lead connected to the electrode of the semiconductor element is connected to the conductor layer. By forming the layer with front and back leads, it is possible to miniaturize semiconductor elements and circuit boards, leading to miniaturization.
第1図(α)は、従来の回路基板の側面図。第1図(b
)はその平面図。
第2図(α)は、本発明の一実施例を示した回路基板の
側面図。第2図(b)はその平面図である。
1・・・・・・・・・導体層
2・・・・・・・・・インナーリード
3・・・・・・・・・絶縁層
4・・・・・・・・・半導体素子
1・・・・・・・・・表導体層
2・・・・・・・・・裏導体層
1・・・・・・・・・表面リード
2・・・・・・・・・裏面リード
以上FIG. 1 (α) is a side view of a conventional circuit board. Figure 1 (b
) is the plan view. FIG. 2(α) is a side view of a circuit board showing an embodiment of the present invention. FIG. 2(b) is a plan view thereof. 1... Conductor layer 2... Inner lead 3... Insulating layer 4... Semiconductor element 1. ......Front conductor layer 2...Bear conductor layer 1...Front lead 2...Bear lead or higher
Claims (1)
導体素子の電極と接続されるインナーリードが、前記導
体層の表面リード及び裏面リードからなる事を特徴とす
る回路基板。1. A circuit board having a conductor layer on both the front and back surfaces of an insulating layer, and an inner lead connected to an electrode of a semiconductor element consisting of a front lead and a back lead of the conductor layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1105029A JPH02283046A (en) | 1989-04-25 | 1989-04-25 | Circuit substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1105029A JPH02283046A (en) | 1989-04-25 | 1989-04-25 | Circuit substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02283046A true JPH02283046A (en) | 1990-11-20 |
Family
ID=14396603
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1105029A Pending JPH02283046A (en) | 1989-04-25 | 1989-04-25 | Circuit substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02283046A (en) |
-
1989
- 1989-04-25 JP JP1105029A patent/JPH02283046A/en active Pending
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