JP2580727B2 - Wiring method of multilayer printed circuit board - Google Patents
Wiring method of multilayer printed circuit boardInfo
- Publication number
- JP2580727B2 JP2580727B2 JP17602488A JP17602488A JP2580727B2 JP 2580727 B2 JP2580727 B2 JP 2580727B2 JP 17602488 A JP17602488 A JP 17602488A JP 17602488 A JP17602488 A JP 17602488A JP 2580727 B2 JP2580727 B2 JP 2580727B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- printed circuit
- circuit board
- wiring method
- multilayer printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Description
【発明の詳細な説明】 〔概 要〕 各種電子機器に広く使用される多層プリント基板の配
線方法に関し、 それぞれの配線回路に複数本のパターンを設けて信号
パターンの断面積および表面積を大きくすることを目的
とし、 一定の板厚に積層する信号層内部の指定経路に、少な
くとも２本の微細幅パターンがそれぞれ対向するように
一定の間隔で配線し、VIAにより該パターンを接続して
基板主面と導通する。DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding a wiring method of a multilayer printed circuit board widely used in various electronic devices, providing a plurality of patterns in each wiring circuit to increase a sectional area and a surface area of a signal pattern. For the purpose, wiring is performed at a fixed interval so that at least two fine width patterns are respectively opposed to a designated path inside the signal layer laminated with a certain thickness, and the patterns are connected by VIA to connect the main surface of the substrate. To conduct.
本発明は、各種電子機器に広く使用される多層プリン
ト基板の配線方法に関する。The present invention relates to a wiring method for a multilayer printed circuit board widely used in various electronic devices.
最近特に、各種電算機等のプリント板に実装される半
導体チップは、ますます高集積化されて入出力端子が微
小ピッチで高密度に配列されるとともに高密度実装が要
求されており、それに伴ってプリント配線基板（以下基
板と略記する）は微細化された配線パターンを高密度に
形成されている。In recent years, in particular, semiconductor chips mounted on printed boards of various computers and the like have been increasingly integrated, and input / output terminals are arranged at a high density at a fine pitch, and high density mounting is required. Thus, a printed wiring board (hereinafter abbreviated as a substrate) has a fine wiring pattern formed at a high density.
そのため、配線パターンの電気抵抗が大きくなって伝
送する信号波形に悪影響を与えているので、配線パター
ンの断面積および表面積を大きくして直流抵抗および高
周波抵抗が少なくなる新しい多層プリント基板の配線方
法が必要とされている。As a result, the electrical resistance of the wiring pattern is increased, which adversely affects the transmitted signal waveform. Therefore, a new multilayer printed circuit board wiring method in which the cross-sectional area and the surface area of the wiring pattern are increased to reduce the DC resistance and the high-frequency resistance. is necessary.
従来広く使用されている多層プリント基板、第２図の
断面図に示すように信号用のパターン４−１を印刷した
セラミックを積層して板厚“T"例えば1.8mmに形成した
信号層４の両面に、電源供給用のグランド層３（以下GN
D層と略記する）を介して表面層２を積層している。Conventionally widely used multilayer printed circuit boards, as shown in the cross-sectional view of FIG. 2, a signal layer 4 formed by laminating ceramics on which a signal pattern 4-1 is printed and having a thickness "T" of, for example, 1.8 mm. Power supply ground layers 3 (hereinafter GN)
The surface layer 2 is laminated via a D layer.
その基板の配線方法は、例えば第３図の平面図に示す
ように表面層２の主面中央部に半導体チップ等の電子部
品１に配設された入出力端子、或いはその電子部品１を
装着するiCソケットのリード端子と接合する接合パッド
２−１を配設して、基板の外周縁に外部と接続する接続
端子２−２を配列し、点線で示すパターン４−１と図示
していないVIAにより接合パッド２−１と接続端子２−
２を接続している。The wiring method of the substrate is, for example, as shown in the plan view of FIG. 3, mounting the input / output terminals provided on the electronic component 1 such as a semiconductor chip at the center of the main surface of the surface layer 2, or mounting the electronic component 1. A connection pad 2-1 for connecting to a lead terminal of an iC socket to be connected is provided, and connection terminals 2-2 for connection to the outside are arranged on the outer peripheral edge of the substrate, and a pattern 4-1 shown by a dotted line and not shown. VIA bonding pad 2-1 and connection terminal 2-
2 are connected.
そのパターン４−１は、第２図の断面図に示すように
幅,W＝200μｍ×厚み,t＝20μｍの導体で形成され、そ
の導体中心が信号層４の板厚中心面，即ち両面のGND層
３より0.9mmとなる面に配線されて、導体のインピーダ
ンスが整合するように構成している。The pattern 4-1 is formed of a conductor having a width, W = 200 μm × thickness, and t = 20 μm as shown in the cross-sectional view of FIG. It is wired on the surface that is 0.9 mm from the GND layer 3 so that the impedance of the conductor matches.
以上説明した従来の配線方法で問題となるのは、配線
密度が高密度化されるに従って接合パッドと導通するパ
ターンの幅“W"がますます微細となり、それに伴ってパ
ターンの断面積および表面積が小さくなるので直流抵抗
が大きくなるので、パターンにより伝送する信号パルス
の立ち上がり時間（rise time）と立ち下がり時間（fal
l time）が長くなって、伝送信号の特性が低下するとい
う問題が生じる。The problem with the conventional wiring method described above is that as the wiring density increases, the width “W” of the pattern that conducts to the bonding pad becomes increasingly finer, and the cross-sectional area and surface area of the pattern accordingly increase. As the DC resistance increases, the DC resistance increases, so the rise time (rise time) and fall time (fal
l time) is prolonged, which causes a problem that the characteristics of the transmission signal deteriorate.
そのため、パターンの厚みを大きくして断面積を増加
することにより直流抵抗の増大を抑える方法が考えられ
るが、製造プロセス上あまり厚くすることが不可能であ
るという問題が生じている。Therefore, a method of suppressing an increase in the DC resistance by increasing the thickness of the pattern and increasing the cross-sectional area can be considered, but there is a problem that it is impossible to make the pattern too thick in the manufacturing process.
本発明は上記のような問題点に鑑み、それぞれの配線
回路に複数本のパターンを設けて信号パターンの断面積
および表面積を大きくすることができる多層プリント基
板の配線方法の提供を目的とする。SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a wiring method for a multilayer printed circuit board in which a plurality of patterns are provided in each wiring circuit to increase the cross-sectional area and the surface area of a signal pattern.
本発明は、第１図に示すように一定の板厚に積層する
信号層14内部の指定経路に微細幅で断面図寸法が同一の
第一パターン14−１と第二パターン14−２を、板厚の中
心面に対して一定の間隔でそれぞれ対向するように配線
し、図示していないVIAにより第一パターン14−１と第
二パターン14−２を接続して、基板主面に配設して接合
パッドおよび接続端子と導通するように形成される。The present invention, as shown in FIG. 1, a first pattern 14-1 and a second pattern 14-2 having the same cross-sectional dimensions and a fine width in a designated path inside the signal layer 14 laminated to a certain thickness, Wired so as to face the center plane of the board at a fixed interval, and connect the first pattern 14-1 and the second pattern 14-2 by VIA (not shown) and arrange them on the main surface of the board. Then, it is formed so as to be electrically connected to the bonding pad and the connection terminal.
本発明では、信号層14内部の指定経路に断面図寸法が
同一の第一パターン14−１と第二パターン14−２を、板
厚の中心面に対して一定の間隔でそれぞれ対向するよう
に配線しているので、１本の信号回路に２本のパターン
が形成されてその断面積および表面積が大きくなり、そ
れに伴ってそれぞれの信号回路の直流抵抗および高周波
抵抗が小さくなって、信号回路の信号伝送特性を向上さ
せることが可能となる。According to the present invention, the first pattern 14-1 and the second pattern 14-2 having the same cross-sectional view size are respectively opposed to the designated path inside the signal layer 14 at a certain interval with respect to the center plane of the plate thickness. Because of the wiring, two patterns are formed on one signal circuit, the cross-sectional area and the surface area thereof become large, and accordingly, the DC resistance and high-frequency resistance of each signal circuit become small. Signal transmission characteristics can be improved.
以下図面に示した実施例に基づいて本発明を詳細に説
明する。Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.
第１図は本実施例による多層プリント基板の配線方法
の断面図を示し、図中において、第２図と同一部材には
同一記号が付してあるが、その他の14は信号伝送用のパ
ターンを形成する信号層である。FIG. 1 is a cross-sectional view of a wiring method for a multilayer printed circuit board according to the present embodiment. In FIG. 1, the same members as those in FIG. Is a signal layer that forms
本発明の配線方法は、第１図に示すように従来と同一
断面図寸法，即ち幅:W＝200μm,厚さ:t＝20μｍの第一
パターン14−１を、第３図で示す指定経路で印刷したセ
ラミックよりなる薄板と、同じく第二パターン14−２を
印刷したセラミック薄板を、第一パターン14−１と第二
パターン14−２が積層する板厚の中心面に対して一定間
隔:D＝150μｍとなるようにそれぞれ対向させて、一定
の板厚，例えばＴ＝1.8mmの積層して信号層14を形成す
ることにより各指定経路に第一パターン14−１と第二パ
ターン14−２を配線している。According to the wiring method of the present invention, as shown in FIG. 1, a first pattern 14-1 having the same cross-sectional dimensions as the conventional one, that is, a width: W = 200 μm and a thickness: t = 20 μm, is designated by a designated path shown in FIG. The ceramic thin plate printed with the ceramic pattern printed on the second pattern 14-2, and the first pattern 14-1 and the second pattern 14-2 are stacked at a constant interval with respect to the center plane of the thickness of the laminated plate: By forming the signal layer 14 by laminating them so that D = 150 μm and having a constant thickness, for example, T = 1.8 mm, the first pattern 14-1 and the second pattern 14- 2 is wired.
そして、従来と同様に上記信号層14の両面にGND層３
を介して表面層２を積層し、第３図に示す基板主面に配
設して接合パッドおよび接続端子と、第一パターン14−
１と第二パターン14−２を図示していないVIAにより導
通するように形成される。Then, as in the conventional case, the GND layers 3 are formed on both sides of the signal layer 14.
A surface layer 2 is laminated on the substrate, and is disposed on the main surface of the substrate shown in FIG.
The first and second patterns 14-2 are formed so as to be electrically connected by VIA (not shown).
その結果、１本の信号回路に第一パターン14−１と第
二パターン14−２を配線しているので、信号用のパター
ン断面積および表面積が大きくなって、直流抵抗および
高周波抵抗が小さくなり、その結果信号回路の信号伝送
特性を向上させることが可能となる。As a result, since the first pattern 14-1 and the second pattern 14-2 are wired in one signal circuit, the cross-sectional area and surface area of the signal pattern are increased, and the DC resistance and high-frequency resistance are reduced. As a result, the signal transmission characteristics of the signal circuit can be improved.
以上の説明から明らかなように本発明によれば極めて
簡単な配線方法で、配線のパターンの断面積および表面
積が大きくなって、直流抵抗および高周波抵抗が小さく
なり、それに伴って伝送する信号の波形を崩さない等の
利点があり、著しい特性向上の効果が期待できる多層プ
リント基板の配線方法を提供することができる。As is apparent from the above description, according to the present invention, with a very simple wiring method, the cross-sectional area and the surface area of the wiring pattern are increased, the DC resistance and the high-frequency resistance are reduced, and the waveform of the signal transmitted accordingly. Thus, there can be provided a wiring method for a multilayer printed circuit board that has advantages such as not breaking down, and is expected to have a remarkable effect of improving characteristics.
第１図は本発明の一実施例による多層プリント基板の配
線方法を示す断面図、 第２図は従来の配線方法を示す断面図、 第３図は多層プリント基板を示す平面図である。 図において、 ２は表面層、 ３はGND層、 14は信号層、 14−１は第一パターン、 14−２は第二パターン、 を示す。FIG. 1 is a sectional view showing a wiring method of a multilayer printed circuit board according to an embodiment of the present invention, FIG. 2 is a sectional view showing a conventional wiring method, and FIG. 3 is a plan view showing the multilayer printed circuit board. In the figure, 2 indicates a surface layer, 3 indicates a GND layer, 14 indicates a signal layer, 14-1 indicates a first pattern, and 14-2 indicates a second pattern.
Claims (1)
指定経路に、少なくとも２本の微細幅パターン（14−1,
14−2,・・14−ｎ）がそれぞれ対向するように一定の間
隔で配線し、VIAにより該パターン（14−1,14−2,・・1
4−ｎ）を接続して基板主面と導通することを特徴とす
る多層プリント基板の配線方法。1. A method according to claim 1, wherein at least two fine width patterns (14-1,
14-2,... 14-n) are wired at regular intervals so as to face each other, and the pattern (14-1, 14-2,.
4-n) to conduct to the main surface of the substrate for wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17602488A JP2580727B2 (en) | 1988-07-13 | 1988-07-13 | Wiring method of multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17602488A JP2580727B2 (en) | 1988-07-13 | 1988-07-13 | Wiring method of multilayer printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0225100A JPH0225100A (en) | 1990-01-26 |
| JP2580727B2 true JP2580727B2 (en) | 1997-02-12 |
Family
ID=16006391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17602488A Expired - Lifetime JP2580727B2 (en) | 1988-07-13 | 1988-07-13 | Wiring method of multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2580727B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5768109A (en) * | 1991-06-26 | 1998-06-16 | Hughes Electronics | Multi-layer circuit board and semiconductor flip chip connection |
| JP2009212116A (en) * | 2008-02-29 | 2009-09-17 | Oki Printed Circuits Co Ltd | Multilayer printed wiring board |
| CN111328185A (en) * | 2020-03-04 | 2020-06-23 | 惠州Tcl移动通信有限公司 | Printed circuit board structure and terminal equipment |
-
1988
- 1988-07-13 JP JP17602488A patent/JP2580727B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| 綱島瑛一著「新版プリント配線の設計と製作」株式会社誠文堂新光社発行，昭和４８年８月２５日第１版発行，第２８４〜２８５頁 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0225100A (en) | 1990-01-26 |
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