JPH05175071A - Laminated ceramic capacitor - Google Patents
Laminated ceramic capacitorInfo
- Publication number
- JPH05175071A JPH05175071A JP34443491A JP34443491A JPH05175071A JP H05175071 A JPH05175071 A JP H05175071A JP 34443491 A JP34443491 A JP 34443491A JP 34443491 A JP34443491 A JP 34443491A JP H05175071 A JPH05175071 A JP H05175071A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic chip
- internal electrode
- ceramic
- ceramic capacitor
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、受動電子部品として使
用される積層セラミックコンデンサに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic ceramic capacitor used as a passive electronic component.
【０００２】[0002]
【従来の技術】近年、実装技術の高密度化とともに、積
層セラミックコンデンサの小型化が進み、シートの薄膜
化、内部電極厚の薄膜化が実施されている。以下に図面
を参照しながら、上記した従来の積層セラミックコンデ
ンサの一例について説明する。2. Description of the Related Art In recent years, as the packaging technology has become higher in density, the size of multilayer ceramic capacitors has been reduced, and the thickness of sheets and the thickness of internal electrodes have been reduced. An example of the above-described conventional multilayer ceramic capacitor will be described below with reference to the drawings.
【０００３】図３は従来の積層セラミックコンデンサの
断面図を示すものである。図３において、１１は焼成を
完了した誘電体からなるセラミックチップ、１２はセラ
ミックチップ１１に積層されて内蔵された内部電極、１
３はセラミックチップ１１の端面まで引き出された内部
電極１２と電気的に接続された一対の外部電極である。FIG. 3 is a sectional view of a conventional monolithic ceramic capacitor. In FIG. 3, 11 is a ceramic chip made of a dielectric material that has been fired, 12 is an internal electrode that is laminated and built in the ceramic chip 11, 1
Reference numeral 3 denotes a pair of external electrodes that are electrically connected to the internal electrodes 12 drawn to the end surface of the ceramic chip 11.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら上記のよ
うな構成では、側面に外部電極が形成されているために
実装する上から回路基板の小型化、実装密度の高密度化
が果たせず、実装密度に限界が生じてきているという問
題点を有していた。However, in the above structure, since the external electrodes are formed on the side surfaces, the circuit board cannot be downsized and the mounting density cannot be increased from the viewpoint of mounting. There was a problem that there was a limit to it.
【０００５】本発明は上記問題点に鑑み、小型化が進ん
でも省スペースで高密度の実装が可能な積層セラミック
コンデンサを提供することを目的とする。In view of the above problems, it is an object of the present invention to provide a monolithic ceramic capacitor which can be mounted in a high density in a space-saving manner even if the size is reduced.
【０００６】[0006]
【課題を解決するための手段】この目的を達成するため
に本発明の積層セラミックコンデンサは、誘電体からな
るセラミックチップと、このセラミックチップの内部に
間隔をおいて積層されている複数層の平面状内部電極
と、この平面状内部電極と１層おきに電気的に接続され
前記平面状内部電極の平面に対して直交する方向に円筒
軸方向があってその円筒の一端または両端が前記セラミ
ックチップの外面に露出して内設された一対の円筒状内
部電極と、この円筒状内部電極の露出した端部と電気的
に接続されかつ前記セラミックチップの外面の少なくと
も一面に形成された一対の外部電極とからなる構成とし
たものである。In order to achieve this object, a monolithic ceramic capacitor according to the present invention comprises a ceramic chip made of a dielectric material, and a plurality of flat layers laminated inside the ceramic chip with a space therebetween. -Shaped internal electrodes, and the planar internal electrodes are electrically connected to every other layer and have a cylinder axial direction in a direction orthogonal to the plane of the planar internal electrodes, and one or both ends of the cylinder are the ceramic chips. A pair of cylindrical internal electrodes exposed and provided on the outer surface of the ceramic chip, and a pair of external electrodes electrically connected to the exposed ends of the cylindrical internal electrodes and formed on at least one of the outer surfaces of the ceramic chip. It is configured to include electrodes.
【０００７】[0007]
【作用】本発明は上記した構成によって外部電極がセラ
ミックチップの上下面にくるため、回路基板に実装した
ときこの回路基板の板面に平行な方向の実装スペースが
小さくなり、実装密度が高くなる。According to the present invention, since the external electrodes are provided on the upper and lower surfaces of the ceramic chip by the above structure, the mounting space in the direction parallel to the plate surface of the circuit board becomes small when mounted on the circuit board, and the mounting density becomes high. .
【０００８】[0008]
（実施例１）以下本発明の実施例について、図面を参照
しながら説明する。(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.
【０００９】図１（ａ）は本発明の第１の実施例におけ
る積層セラミックコンデンサの側面と平行な面の断面
図、図１（ｂ）はその平面図を示すものである。図１に
おいて、１は焼成を完了した誘電体からなるセラミック
チップ、２は平面状内部電極、３は一対の円筒状内部電
極、４は外部電極である。円筒状内部電極３は、その円
筒軸方向が平面状内部電極２の平面に対して直交するよ
うにセラミックチップ１の両端部付近に内設され、かつ
平面状内部電極２と電気的に接続されている。外部電極
４は、セラミックチップ１の上下面の両端部付近に、こ
の上下面まで突き抜けた円筒状内部電極３と電気的に接
続されるように導電ペーストが塗布されて形成されてい
る。FIG. 1 (a) is a sectional view of a plane parallel to the side surface of the monolithic ceramic capacitor according to the first embodiment of the present invention, and FIG. 1 (b) is a plan view thereof. In FIG. 1, 1 is a ceramic chip made of a dielectric material that has been fired, 2 is a planar internal electrode, 3 is a pair of cylindrical internal electrodes, and 4 is an external electrode. The cylindrical internal electrode 3 is internally provided in the vicinity of both ends of the ceramic chip 1 so that the cylinder axis direction is orthogonal to the plane of the planar internal electrode 2, and is electrically connected to the planar internal electrode 2. ing. The external electrodes 4 are formed by coating a conductive paste near both ends of the upper and lower surfaces of the ceramic chip 1 so as to be electrically connected to the cylindrical internal electrodes 3 penetrating to the upper and lower surfaces.
【００１０】この構成により、外部電極４がセラミック
チップ１の上下面にくるため、実装スペースが狭くなり
実装密度を高くすることができる。With this structure, since the external electrodes 4 are provided on the upper and lower surfaces of the ceramic chip 1, the mounting space is narrowed and the mounting density can be increased.
【００１１】なお、本実施例では外部電極４をセラミッ
クチップ１の上下面に形成したが、用途により上面また
は下面のどちらか一方のみに形成してもよい。また、本
実施例では一対の円筒状内部電極３を両端部付近に設け
た例を示したが、互いに接触しなければ必ずしもその配
置が両端部付近に限定されるものではない。Although the external electrodes 4 are formed on the upper and lower surfaces of the ceramic chip 1 in this embodiment, they may be formed on either the upper surface or the lower surface depending on the application. Further, in the present embodiment, an example in which the pair of cylindrical internal electrodes 3 is provided near both ends is shown, but the arrangement is not necessarily limited to near both ends unless they contact each other.
【００１２】（実施例２）図２は、本発明の第２の実施
例における積層セラミックコンデンサの側面と平行な面
の断面図である。図２において図１（ａ）と異なるの
は、図１（ａ）における外部電極４を塗布しない点であ
る。このように構成された積層セラミックコンデンサ
は、多層の回路基板の内部にそのまま埋め込み、コンデ
ンサ内蔵の回路基板、特にセラミック回路基板を得るの
に適している。すなわち、セラミックチップ１の側面に
従来のような外部電極を形成しなくても円筒状内部電極
３の両端部でセラミック回路基板の導体部と電気的接続
ができるため、コンデンサを高密度に内蔵したセラミッ
ク回路基板が得られる。(Embodiment 2) FIG. 2 is a sectional view of a plane parallel to a side surface of a monolithic ceramic capacitor according to a second embodiment of the present invention. 2 is different from FIG. 1A in that the external electrode 4 in FIG. 1A is not applied. The monolithic ceramic capacitor configured in this manner is suitable for obtaining a circuit board with a built-in capacitor, particularly a ceramic circuit board, by embedding it as it is in a multilayer circuit board. That is, both ends of the cylindrical internal electrode 3 can be electrically connected to the conductor portion of the ceramic circuit board without forming an external electrode on the side surface of the ceramic chip 1, so that the capacitors are built in at high density. A ceramic circuit board is obtained.
【００１３】なお、本実施例では、セラミックチップ１
は焼成を完了させたものとしたが、セラミックチップ１
は焼成末了の生セラミックチップでも多層のセラミック
回路基板の内部にそのまま埋め込み、生セラミックチッ
プと同時に焼成してコンデンサ内蔵のセラミック回路基
板としても同様の効果が得られる。In this embodiment, the ceramic chip 1 is used.
Has been fired, but ceramic chip 1
The same effect can be obtained even when a raw ceramic chip after completion of firing is directly embedded in a multilayer ceramic circuit board and fired at the same time as the raw ceramic chip to form a ceramic circuit board with a built-in capacitor.
【００１４】[0014]
【発明の効果】以上のように本発明の積層セラミックコ
ンデンサは、セラミックチップの内部に円筒状内部電極
を設けたことにより、その円筒状内部電極の端部と電気
的に接続された外部電極がセラミックチップの上面また
は下面にくるため、実装スペースが小さくなり、実装密
度を高くすることができる。As described above, in the monolithic ceramic capacitor of the present invention, by providing the cylindrical internal electrode inside the ceramic chip, the external electrode electrically connected to the end of the cylindrical internal electrode is provided. Since it is located on the upper surface or the lower surface of the ceramic chip, the mounting space can be reduced and the mounting density can be increased.
【図１】（ａ）本発明の第１の実施例における積層セラ
ミックコンデンサの断面図 （ｂ）同平面図FIG. 1A is a sectional view of a monolithic ceramic capacitor according to a first embodiment of the present invention. FIG. 1B is a plan view of the same.
【図２】本発明の第２の実施例における積層セラミック
コンデンサの断面図FIG. 2 is a sectional view of a monolithic ceramic capacitor according to a second embodiment of the present invention.
【図３】従来の積層セラミックコンデンサの断面図FIG. 3 is a sectional view of a conventional monolithic ceramic capacitor.
１ セラミックチップ ２ 平面状内部電極 ３ 円筒状内部電極 ４ 外部電極 1 Ceramic Chip 2 Planar Internal Electrode 3 Cylindrical Internal Electrode 4 External Electrode
Claims (2)
のセラミックチップの内部に間隔をおいて積層されてい
る複数層の平面状内部電極と、この平面状内部電極と１
層おきに電気的に接続され前記平面状内部電極の平面に
対して直交する方向に円筒軸方向があってその円筒の一
端または両端が前記セラミックチップの外面に露出して
内設された一対の円筒状内部電極と、この円筒状内部電
極の露出した端部と電気的に接続されかつ前記セラミッ
クチップの外面の少なくとも一面に形成された一対の外
部電極とからなる積層セラミックコンデンサ。1. A ceramic chip made of a dielectric material, a plurality of layers of planar internal electrodes laminated inside the ceramic chip at intervals, and the planar internal electrode.
A pair of layers electrically connected to each other and having a cylinder axial direction in a direction orthogonal to the plane of the planar internal electrode and one end or both ends of the cylinder being exposed and exposed on the outer surface of the ceramic chip. A monolithic ceramic capacitor comprising a cylindrical internal electrode and a pair of external electrodes electrically connected to the exposed end of the cylindrical internal electrode and formed on at least one of the outer surfaces of the ceramic chip.
のセラミックチップの内部に間隔をおいて積層されてい
る複数層の平面状内部電極と、この平面状内部電極と１
層おきに電気的に接続され前記平面状内部電極の平面に
対して直交する方向に円筒軸方向があってその円筒の一
端または両端が前記セラミックチップの外面に露出して
内設された一対の円筒状内部電極とからなるコンデンサ
内蔵セラミック回路基板用の積層セラミックコンデン
サ。2. A ceramic chip made of a dielectric material, a plurality of layers of planar internal electrodes laminated inside the ceramic chip at intervals, and the planar internal electrode.
A pair of layers electrically connected to each other and having a cylinder axial direction in a direction orthogonal to the plane of the planar internal electrode and one end or both ends of the cylinder being exposed and exposed on the outer surface of the ceramic chip. A monolithic ceramic capacitor for a ceramic circuit board with a built-in capacitor consisting of a cylindrical internal electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34443491A JPH05175071A (en) | 1991-12-26 | 1991-12-26 | Laminated ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34443491A JPH05175071A (en) | 1991-12-26 | 1991-12-26 | Laminated ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05175071A true JPH05175071A (en) | 1993-07-13 |
Family
ID=18369236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34443491A Pending JPH05175071A (en) | 1991-12-26 | 1991-12-26 | Laminated ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05175071A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002057066A (en) * | 2000-08-10 | 2002-02-22 | Taiyo Yuden Co Ltd | Chip array and its manufacturing method |
| JP2007096265A (en) * | 2005-08-31 | 2007-04-12 | Ngk Spark Plug Co Ltd | Integrated capacitor for wiring board, and wiring board |
| JP2008060214A (en) * | 2006-08-30 | 2008-03-13 | Murata Mfg Co Ltd | Mounting structure of laminated ceramic electronic component |
| US7778010B2 (en) | 2005-08-31 | 2010-08-17 | Ngk Spark Plug Co., Ltd. | Method of manufacturing capacitor for incorporation in wiring board, capacitor for incorporation in wiring board, and wiring board |
| KR20160004124A (en) * | 2014-07-02 | 2016-01-12 | 조인셋 주식회사 | Polymer capacitor having a tolerance to esd |
-
1991
- 1991-12-26 JP JP34443491A patent/JPH05175071A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002057066A (en) * | 2000-08-10 | 2002-02-22 | Taiyo Yuden Co Ltd | Chip array and its manufacturing method |
| JP2007096265A (en) * | 2005-08-31 | 2007-04-12 | Ngk Spark Plug Co Ltd | Integrated capacitor for wiring board, and wiring board |
| US7778010B2 (en) | 2005-08-31 | 2010-08-17 | Ngk Spark Plug Co., Ltd. | Method of manufacturing capacitor for incorporation in wiring board, capacitor for incorporation in wiring board, and wiring board |
| JP4550774B2 (en) * | 2005-08-31 | 2010-09-22 | 日本特殊陶業株式会社 | Wiring board built-in capacitor, wiring board, laminated body, capacitor assembly, wiring board built-in capacitor manufacturing method |
| JP2008060214A (en) * | 2006-08-30 | 2008-03-13 | Murata Mfg Co Ltd | Mounting structure of laminated ceramic electronic component |
| KR20160004124A (en) * | 2014-07-02 | 2016-01-12 | 조인셋 주식회사 | Polymer capacitor having a tolerance to esd |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH05166668A (en) | Low-temperature common baking structure containing embedded capacitor | |
| US3740624A (en) | Monolithic capacitor having corner internal electrode terminations | |
| JPH08172025A (en) | Chip capacitor | |
| JPH08124795A (en) | Multilayered capacitor | |
| JP2000058376A (en) | Ceramic capacitor | |
| USH416H (en) | High capacitance flexible circuit | |
| JP2006121046A (en) | Circuit board | |
| JPH05175071A (en) | Laminated ceramic capacitor | |
| US4568999A (en) | Multilayer ceramic capacitor on printed circuit | |
| JP3348523B2 (en) | Multilayer ceramic parts | |
| JPH01216591A (en) | Printed board | |
| JPH1065341A (en) | Manufacturing method of multilayer ceramic board | |
| JPH04267317A (en) | Layered ceramic capacitor | |
| JP3175433B2 (en) | Multilayer ceramic parts | |
| JP2817372B2 (en) | Capacitor | |
| JP2000195741A (en) | Laminated ceramic capacitor | |
| JPS628040B2 (en) | ||
| JPS62210612A (en) | Laminated capacitor | |
| JPH05166672A (en) | Composite part | |
| JP2001319828A (en) | Capacitor array | |
| JP2581211B2 (en) | Dielectric circuit board with built-in capacitor | |
| JP3368650B2 (en) | Multilayer ceramic parts | |
| JPH0745950Y2 (en) | Chip type monolithic ceramic capacitor | |
| JPH0845776A (en) | Low capacitance multilayered chip ceramic capacitor | |
| JP3940582B2 (en) | Capacitor built-in wiring board |