JPH0225054A - Master slice lsi - Google Patents

Master slice lsi

Info

Publication number
JPH0225054A
JPH0225054A JP17551788A JP17551788A JPH0225054A JP H0225054 A JPH0225054 A JP H0225054A JP 17551788 A JP17551788 A JP 17551788A JP 17551788 A JP17551788 A JP 17551788A JP H0225054 A JPH0225054 A JP H0225054A
Authority
JP
Japan
Prior art keywords
master slice
basic cell
buffers
area
basic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17551788A
Other languages
Japanese (ja)
Inventor
Keiichi Suemitsu
末光　啓一
Yoshihiro Okuno
奥野　義弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17551788A priority Critical patent/JPH0225054A/en
Publication of JPH0225054A publication Critical patent/JPH0225054A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the numbers of I/O buffers and pads by a method wherein a basic cell region is shaped polygonal and the corners of a chip are used as regions for the construction of I/O buffers. CONSTITUTION:Basic cells 1 and a wiring region 2 which are elements of a logical circuit are arranged in a polygonal region and, at the corners of the polygonal region, I/O buffers 4 and pads 3 are formed. In such a design, basic cell regions may be effectively utilized in automatic arranging and wiring, and more I/O buffers 4 and pads 3 may be formed without an increase in the chip area.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、マスタースライスＬＳＩにおいてその面積
を有効利用するチップ構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a chip structure that effectively utilizes the area of a master slice LSI.

〔従来の技術〕[Conventional technology]

従来のマスタースライスＬＳＩは、チップ上で基本セル
を敷きつめ７ｃ論理＠Ｊ８１ｔを実現するための長方形
の領域とその周辺のＩ　／　Ｏバッファ及びパッド領域
から構成されていた。A conventional master slice LSI consists of a rectangular area for laying out basic cells on a chip to realize 7c logic @J81t, and an I/O buffer and pad area around the rectangular area.

従来のマスタースライスＬＳＩは、通常計算機を用いて
自動配置配線して回路を作る。各入出力はＩ１０バッフ
ァ全通しパッドにつなぐ。このようにして半導体集積回
路が実現される。Conventional master slice LSIs typically create circuits by automatically placing and wiring them using a computer. Each input/output is connected to the entire I10 buffer pad. In this way, a semiconductor integrated circuit is realized.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のマスタースライスＬＳＩにおける基本セル領域の
四隅は使用頻度が低く、面積を無駄にすることが多いと
いうような問題点があった。（第３．４図の斜線部） この発明は上記のような問題点を解消するためになされ
たもので、半導体チップの面積を有効利用することを目
的とする。The four corners of the basic cell area in a conventional master slice LSI are rarely used, and there is a problem in that the area is often wasted. (Shaded area in Fig. 3.4) This invention was made to solve the above-mentioned problems, and its purpose is to effectively utilize the area of a semiconductor chip.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係るマスタースライスＬＳＩは、基本ｍ域を
多角形としたことによシ、自！１ｉｙＩ配置配線で基本
セル須坂を有効に利用するものである。The master slice LSI according to the present invention has the advantage that the basic m-region is polygonal. This makes effective use of the basic cell Suzaka in 1iyI placement and wiring.

〔作用〕[Effect]

との発明におけるマスタースライスＬＳＩは、基本セル
領域を多角形とすることによυ、チップの四角をＩ１０
バッファ構成領域として使用され、各々のＩ／Ｏバッフ
ァの面積は同じで、機能及び駆動能力等を有する、形状
の異なるＩ／Ｏバッファが従来よυも数多く造れる。The master slice LSI in the invention of
Compared to the conventional art, it is possible to create a larger number of I/O buffers that are used as a buffer configuration area, have the same area, function, drive ability, etc., and have different shapes.

〔実施例〕〔Example〕

以下、この発明を図について説明する。第１図はこの発
明の一実施例によるマスタースライスＬＳＩを示す全体
図であり、図において、（１）は基本セル、（２）は配
線領域、（３）はバットである。第２図は第１図の部分
図であり、（４）はＩ１０バッファである。The invention will now be explained with reference to the drawings. FIG. 1 is an overall diagram showing a master slice LSI according to an embodiment of the present invention. In the figure, (1) is a basic cell, (2) is a wiring area, and (3) is a bat. FIG. 2 is a partial diagram of FIG. 1, and (4) is the I10 buffer.

この発明はマスタースライスＬＳＩを構成する基本セル
領＊　（１）で使用頻度が低い隅部を除くことにより実
現したものである。This invention was realized by eliminating the corners that are used less frequently in the basic cell area *(1) constituting the master slice LSI.

上記隅部は第１図に示すように四隅に限る仁となく、必
要に応じて一隅であってもよい。The corner portions are not limited to four corners as shown in FIG. 1, but may be one corner if necessary.

例えば、隅部の一つを除いた五角形管した内部基本セル
領域以外のすべての領域に周辺のＩ１０バッファ及びＩ
／Ｏバットを形成することができる。For example, all areas other than the pentagonal inner basic cell area except for one of the corners include the surrounding I10 buffer and the I10 buffer.
/O batt can be formed.

また、基本セルはバイポーラトランジスタ及び抵抗、あ
るいはＭＯＳ）ランジスタ及び抵抗からなるものが好ま
しく用いられる。The basic cell preferably includes a bipolar transistor and a resistor, or a MOS transistor and a resistor.

なお、上記実施例では、論理回路構成領域が入角形であ
る場合において説明したが、多角形、もしくけ円形（楕
円も含む）に近い多角形にしても上記実施例と同様の効
果含臭する。In addition, in the above embodiment, the case where the logic circuit configuration area is a rectangular shape is explained, but even if it is a polygon or a polygon close to a circular shape (including an ellipse), the same effect as in the above embodiment is obtained. .

〔発明の効果〕〔Effect of the invention〕

以上のように、仁の発明によればチップ面積を増大させ
るととなく、多くの工／○バッファ及びパッドを造るこ
とができる。As described above, according to Jin's invention, it is possible to create a large number of chip/circle buffers and pads without increasing the chip area.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例によるマスタースライスＬ
ＳＩを示す全体図、第２図は第１図の部分図である。第
３図は従来のマスタースライスＬＳＩ奢示す全体図、第
４図は８３図の部分図である０ 図において、（１）は基本セル、（２）は配線領域、（
３）はパッド、（４）は工／○バッファである。 なお、図中、同一符号は同−又は相当部分を示す。FIG. 1 shows a master slice L according to an embodiment of the present invention.
An overall view showing the SI, and FIG. 2 is a partial view of FIG. 1. FIG. 3 is an overall diagram showing a conventional master slice LSI, and FIG. 4 is a partial diagram of FIG.
3) is a pad, and (4) is a work/○ buffer. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 複数の基本セルが配列をなして基本セル領域が形成され
ていて、前記基本セル領域内の任意の基本セルによつて
複数の論理セルが構成される内部基本セル領域と、その
周辺をＩ／Ｏバッファ及びＩ／Ｏパッドを形成した長方
形のチップ構造のマスタースライスＬＳＩにおいて、内
部基本セル領域の形状を五角形以上にしたことを特徴と
するマスタースライスＬＳＩ。A basic cell area is formed by arranging a plurality of basic cells, and an internal basic cell area where a plurality of logic cells are formed by arbitrary basic cells in the basic cell area and its surroundings are connected to I/O. A master slice LSI having a rectangular chip structure in which an O buffer and an I/O pad are formed, the master slice LSI having an internal basic cell region having a shape of a pentagon or more.
JP17551788A 1988-07-13 1988-07-13 Master slice lsi Pending JPH0225054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17551788A JPH0225054A (en) 1988-07-13 1988-07-13 Master slice lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17551788A JPH0225054A (en) 1988-07-13 1988-07-13 Master slice lsi

Publications (1)

Publication Number Publication Date
JPH0225054A true JPH0225054A (en) 1990-01-26

Family

ID=15997437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17551788A Pending JPH0225054A (en) 1988-07-13 1988-07-13 Master slice lsi

Country Status (1)

Country Link
JP (1) JPH0225054A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6013924A (en) * 1996-12-25 2000-01-11 Fujitsu Limited Semiconductor integrated circuit and method for making wiring layout of semiconductor integrated circuit
JP2010187008A (en) * 2010-04-12 2010-08-26 Fujitsu Semiconductor Ltd Semiconductor integrated circuit and wiring layout method of semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6013924A (en) * 1996-12-25 2000-01-11 Fujitsu Limited Semiconductor integrated circuit and method for making wiring layout of semiconductor integrated circuit
JP2010187008A (en) * 2010-04-12 2010-08-26 Fujitsu Semiconductor Ltd Semiconductor integrated circuit and wiring layout method of semiconductor integrated circuit

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