JPH02194412A - Regulator circuit - Google Patents
Regulator circuitInfo
- Publication number
- JPH02194412A JPH02194412A JP1014422A JP1442289A JPH02194412A JP H02194412 A JPH02194412 A JP H02194412A JP 1014422 A JP1014422 A JP 1014422A JP 1442289 A JP1442289 A JP 1442289A JP H02194412 A JPH02194412 A JP H02194412A
- Authority
- JP
- Japan
- Prior art keywords
- output
- stage
- regulator
- differential amplification
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims abstract description 45
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 45
- 238000001514 detection method Methods 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 2
- 238000007599 discharging Methods 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 5
- 238000013459 approach Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
- Amplifiers (AREA)
Abstract
Description
［産業上の利用分野Ｊ
本発明はレギュレータ負荷が８徴の充放電に関係するレ
ギュレータ回路に関する。
［発明の概要１
本発明は、レギュレーク出力段の負荷側に並列ｔこトラ
ンジスタを挿入し、ゲート電位を制御Ｂする事により２
レギユレー・夕の容置負荷変動に対するリンギングの早
期安定を可能としたものである。
〔従来の技術Ｊ
従来のレギュレータ回路図を第２図に示す、マイナス電
源ｌとブうスミ源２．プラス電源を基準とした基準電圧
回路３の出力は、差動増幅段５のプラス入力に接続され
、差動増幅段の出力は差動増幅出力段６に接続されてい
る。差動増幅段及び、差動増幅出力段の定電流源用トラ
ンジスタのゲート電位は、定電流バイアス回路４の出力
が与えられている。差動増幅出力段出力１３はレギュレ
ータ出力であり、プラス電源と、レギュレータ出力１３
の間に、出力検出回路７が挿入され、出力検出回路出力
は２前述の差動増幅段のマイナス入力に接続されていた
８レギユレータ出力電圧は基準電圧Ｖ□、と、出力電圧
分割電位が等しいときの出力電圧である。
［発明が解決しようとする課題１
しかし前述の従来技術では、ＬＥＤプリンタヘッド用ド
ライバ等のゲート電位としてレギュレータ出力を用いる
ように、負荷が容量の、充放電の形の場合、又、負荷変
動が大きいとき出力のリンギングが大きく、安定するま
での時間が長いという問題を有する。
以下に原因を述べる。
第２図において、レギュレータ出力の負荷に。
容ｆｆ１ｌｌがスイッチ１２を通して接続されたり、オ
ーブン（容量ｌｌの電荷が抜かれる）になったりした場
合のレギュレータ出力１３の電位変動を第３図に示す１
図においてＯＮは容ｆｆ１ｌｌとレギュレータ出力】３
が接続されている時であり、ＯＦＦは、容量１１の電荷
が抜かれている時である。１８は２レギユレータ出力電
圧である。
■ ０ＦＦ−ＯＮの瞬間レギュレータ出力は、容ｆｉｌ
ｌｌのＷ１荷が”０“の為、プラス電源基準まで持ち上
がる。
■ 差動増幅出力段のＮ型トランジスタが深くバイアス
され、容ｆｆ１ｌｌに電荷を充電する。
■ 差動増幅段の応答遅延により、Ｎ型トランジスタは
容ｔｉｉに充電しすぎる。
■ Ｎ型トランジスタが０ＦＦＬ、、差動増幅出力段の
定電流源１５によって容ｆｆ１１１の電荷を１友く。
■ レギュレータ出力電圧が設定の電圧に近づくにつれ
Ｎ型トランジスタが１余々に浅くバイアスされて安定す
る。
ここで、差動増幅段ａ延により、■、■、■は多少（つ
かえされ、収束する。ここで、充電しすぎた容量１１の
電荷を抜くのに、定電流源（高を氏抗負向）の為、負荷
容１１１の容量値が大きければ大きいほど時間がかかり
、レギュレータ出力が安定するのに時間がかかってしま
う、特に、ＬＥＤプリンタ用ドライバのように、レギュ
レータ出力を出力トランジスタのゲートバイアスとする
使用方法を用いると、出力定電流の波形に、そのままレ
ギュレータ出力電圧のリンギングが生じる為高速でＬ
Ｅ Ｄをスイッチングできない。
そこで本発明はこのような問題点を解決するものでその
目的とするところは、容量負荷変動に対するリンギング
の早期安定が可能なレギュレータ回路を提供するところ
にある。[Industrial Field of Application J] The present invention relates to a regulator circuit in which the regulator load is related to eight types of charging and discharging. [Summary of the Invention 1 The present invention provides two transistors by inserting parallel transistors on the load side of the regulator output stage and controlling the gate potential.
This enables early stabilization of ringing in response to fluctuations in the tank load of the regulator. [Prior art J A conventional regulator circuit diagram is shown in FIG. The output of the reference voltage circuit 3 with reference to the positive power supply is connected to the positive input of the differential amplification stage 5, and the output of the differential amplification stage is connected to the differential amplification output stage 6. The output of the constant current bias circuit 4 is given to the gate potential of the constant current source transistors in the differential amplification stage and the differential amplification output stage. The differential amplification output stage output 13 is a regulator output, and the positive power supply and the regulator output 13
In between, an output detection circuit 7 is inserted, and the output detection circuit output is 2. The output voltage of the 8 regulator connected to the negative input of the differential amplifier stage mentioned above is equal to the reference voltage V□, and the output voltage division potential is equal. This is the output voltage when [Problem to be Solved by the Invention 1] However, in the above-mentioned conventional technology, when the load is a capacitive charge/discharge type, such as using a regulator output as the gate potential of a driver for an LED printer head, or when the load fluctuates When it is large, there is a problem that the output ringing is large and it takes a long time to stabilize. The causes are explained below. In Figure 2, to the load of the regulator output. Figure 3 shows potential fluctuations of the regulator output 13 when the capacitor ff1ll is connected through the switch 12 or becomes an oven (the charge of the capacitor ll is removed).
In the figure, ON is capacitor ff1ll and regulator output] 3
is connected, and OFF is when the charge of the capacitor 11 is removed. 18 is the 2 regulator output voltage. ■ The instantaneous regulator output of 0FF-ON is
Since the W1 load of ll is "0", it is lifted up to the positive power supply standard. (2) The N-type transistor in the differential amplifier output stage is deeply biased and charges the capacitor ff1ll. ■ Due to the response delay of the differential amplifier stage, the N-type transistor is charged too much. (2) The N-type transistor is 0FFL, and the constant current source 15 of the differential amplification output stage removes the charge of the capacitor ff111 by 1. - As the regulator output voltage approaches the set voltage, the N-type transistor is biased slightly more than 1 and becomes stable. Here, due to the expansion of the differential amplifier stage a, ■, ■, and ■ are somewhat blocked and converge.Here, in order to remove the charge from the overcharged capacitor 11, Therefore, the larger the capacitance value of the load capacitor 111 is, the longer it takes for the regulator output to stabilize. If you use the bias method, ringing of the regulator output voltage will occur in the output constant current waveform, so it will be low at high speed.
Unable to switch ED. SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and it is an object of the present invention to provide a regulator circuit that can quickly stabilize ringing in response to capacitive load fluctuations.
本発明のレギュレータ回路は。
少なくとも基準電源、定電流バイアス段、差動増幅段、
差動増幅出力段、レギュレータ出力電圧検出段を有し、
前記基準電源の出力を前記差動増４１！段プラス入力に
接続し、前記出力電圧検出段出力を前記差動増幅段マイ
ナス入力に接続し、前記差動増幅段出力を前記差動増幅
出力段の入力とし、前記差動増幅出力段の出力をレギュ
レータ出力とするレギュレータ回路において、前記差動
増幅段出力を前記差動増幅出力段に接続すると共に、第
２の差動増幅出力段に接続し、前記第２の差動増幅出力
段出力の位相を反転する手段を有し、前記反転信号を、
前記レギュレータ出力の基準とする電源と、前記レギュ
レータ出力と番ご各々、ソースとトレインを接続した電
界効果型トランジスタ（プラス電源基準はＰ型、マイナ
スｍｉｄ基準はＮ型）のゲート電極に入力した事を特徴
とする。The regulator circuit of the present invention is as follows. At least a reference power supply, constant current bias stage, differential amplification stage,
It has a differential amplification output stage and a regulator output voltage detection stage.
The output of the reference power source is increased by the differential amplifier 41! The output of the output voltage detection stage is connected to the negative input of the differential amplifier stage, the output of the differential amplifier stage is used as the input of the differential amplifier output stage, and the output of the differential amplifier output stage is connected to the positive input of the differential amplifier stage. In the regulator circuit, the output of the differential amplification stage is connected to the differential amplification output stage, and the output of the second differential amplification output stage is connected to the second differential amplification output stage, and the output of the second differential amplification output stage is connected to the differential amplification output stage. comprising means for inverting the phase of the inverted signal;
The power source used as the reference for the regulator output, and the voltage input to the gate electrode of the field effect transistor (the positive power source reference is P type, the negative mid reference is N type) whose source and train are connected to each of the regulator outputs and numbers. It is characterized by
【作 用］
本発明の上記の構成によれば、出力負荷の容量に電荷を
充電しすぎて、定ｌｆｉＭ源（高抵抗負荷）による放電
時に、並列に挿入したトランジスタがＯＮＬ、、すみや
かに不要な電荷を放電する為、負荷容量変動に対し、レ
ギュレータ出力を早期に安定化する事が可能である。
［実 施 例）
第１図は、本発明の一実施例におけるレギュレ−夕回路
図である。１〜７は、従来のＬ・ギュレータ回路図と同
じである。８は第２の差動増幅出力段であり、差動増幅
段の出力がＮ型トランジスタ１Ｇのゲート１ｉ極に接Ｍ
している。Ｎ型トランジスタのトレインは、定電流源１
７を負荷としている。ここで、第２差動増幅段Ｎ型トラ
ンジスタ１６ ノ？！流ＩＩ幅１３ Ｂ ２ ト、 定
ｉｔＵ源１７ ノ定１！ １Ｉｔ（ａＩ２の関係は第１
の差動増幅段Ｎ型トランジスタ１４の電流増幅率β１と
定電流源１５の定電流値１１との間で次式を満たしでい
る。
Ｉ２／β２＜Ｉ ｌ／βに
こで差動増幅出力段において、定電流負荷のかわりに、
高抵抗負荷を用いたときは、定電流値１１、Ｉ２の変わ
りに、高負荷抵抗の逆数を代入すれば良い、ここの関係
は、第１の差動増幅出力段のＮ型トランジスタが少しで
もＯＮＬ、でいる時は、？Ａ２の差動増幅出力段の出力
を低いレベルに、つけておき、第１の差動増幅出力段の
Ｎ型トランジスタがＯＦＦしたときのみに第２の差動増
幅出力段を高いレベルにもってい（為であり、こうする
事によって第２の差動増幅出力段の出力をインバータ９
で位相反転し、レギュレータ出力負荷側に並列に挿入し
たトランジスタｌＯを、第１の差動増幅出力段Ｎ ｃ
ｈ トランジスタのＯＦＦした時のみにＯＮさせる事が
可能となる。ここでインバータ９の入力閾値電圧は、よ
り高い事により前述の動作をより正確に行わせる事が可
能となる。
第１図において、レギュレータ出力の負荷に、容ｆｆ１
ｌｌかスイッチ１２を通して接続されたり。
オープン（容ｆｆ１ｌｌの電荷が抜かれる）になったり
した場合のレギュレータ出力１３の電位変動１９を第４
図に示す０図において、ＯＮは容量１１とレギュレータ
出力１３が接続されている時であり、ＯＦＦは容量ｉｉ
のＴｔ！荷が抜かれている時である。
■ ０ＦＦ−ＯＮの瞬間レギュレータ出力は、容量ｚの
電荷が“０°°の為、プラス電源電位まで持ち上がる。
■ 差動増幅出力段のＮ型トランジスタが深くバイアス
され、容ｆｆｔｌｌに電荷を充電する。
■ 差動増幅段の応答遅延により、Ｎ型トランジスタは
容Ｉｌｌに充電しすぎる。
■ Ｎ型トランジスタが０ＦＦＬ、第２の差動増幅出力
段Ｎ型トランジスタも０ＦＦＩ、、第２の差動増幅出力
段の出力レベルが高いレベルとなり１次段インバータ９
の出力が反転しレギュレータ出力の負荷側に挿入したト
ランジスタ１０がＯＮする為、トランジスタ１０と、定
電流源１５によって容量ｔｉの電荷を抜く。
■ レギュレータ出力電圧が設定の電位に近づくにつれ
Ｎ Ｍ ）ランジスタが１１＜バイアスされ安定する１
例えば、レギュレート電圧が電源電圧の半分であったと
き、第１の差動増幅出力段Ｎ型トランジスタ１４のＯＮ
抵抗は、定電流源トランジスタ１５のＯＮ抵抗と等しく
なる１次に、第２の差動増幅出力段のＮ型トランジスタ
１６と第２の差動増幅出力段の定電流源の関係は前述の
ように、Ｉ２７β２くＩ】／β１ が成立する為、１１
とＩ２が等しいとして、β２＝ｌＯｘＢｌとすると。
第２の差動増幅出力段の出力は７マイナス電位からみて
レギュレート電圧の約ｌ／１０となり、次段インバータ
９の出力は、プラス電源レベルとなり、レギュレータ出
力負荷と並列に挿入されたトランジスタ１０はＯＦ Ｆ
される。
ここで差動増幅段遅延により、■、■、■は多少くりか
えされ収束する。
尚、第４図の１９は、レギュレータ出力１３の電位変動
で、２０は、第２の差動増幅出力段電位であり、２１は
、第２の差動増幅出力１９次段のインバータの出力電位
波形である。又、本実施例はプラス基準で述べたが、マ
イナス基準も容易に可能である。
【発明の効果１
以上述べたように発明によれば、レギュレータ出力負荷
容量が充電されすぎたとき、出力負荷と並列のトランジ
スタがＯＮし、電荷の放電に寄与する為出力リンギング
が速＜ｇさまるという効果を有する。又、出力負荷と並
列に１不入されたトランジスタは、第２の差動増幅用ノ
ｊ段の定電流源とＮ型トランジスクの電ｉ市増幅率との
関係を第１の葦Ｉｌｌ増幅出力ＩＱより低いｌｌｔ圧！
、：第２の差動増幅出力段が設定さ１・するようになっ
ている為、出力負荷容量が充電されすＹたときのみＯＮ
するだけであり、低消費電流で高速応答を実現できると
いつ効果も有する。従来のレギュレータ回路に最低５−
〕のトう゛ノジスタを加えるだけで実現可能であり、１
基板上に、集積できるという効果も有する。
・マイノース電源
・・プラス電源
基準１ｆｉｆ：ｉ
定電流バイ゛７；２．峻
・差！７１州幅段
・差ＩＩＪ ｊｆ’！輔出力を女
・出力電圧検出ｒ、Ｑ
・第２の差動増幅出力段
・位相反転ｔ９[Function] According to the above configuration of the present invention, when the capacitance of the output load is overcharged and discharged by a constant lfiM source (high resistance load), the transistor inserted in parallel becomes ONL, and is quickly unnecessary. Since this type of charge is discharged, it is possible to quickly stabilize the regulator output in response to load capacitance fluctuations. [Embodiment] FIG. 1 is a regulator circuit diagram in an embodiment of the present invention. 1 to 7 are the same as the conventional L regulator circuit diagram. 8 is a second differential amplification output stage, and the output of the differential amplification stage is connected to the gate 1i pole of the N-type transistor 1G.
are doing. The train of N-type transistors is a constant current source 1
7 as the load. Here, the second differential amplifier stage N-type transistor 16 ? ! Flow II width 13 B 2 g, constant itU source 17 no constant 1! 1It (the relationship of aI2 is the first
The following equation is satisfied between the current amplification factor β1 of the N-type transistor 14 of the differential amplifier stage and the constant current value 11 of the constant current source 15. I2/β2<I l/β In the differential amplification output stage, instead of a constant current load,
When using a high resistance load, the constant current value 11, I2 can be replaced by the reciprocal of the high load resistance.The relationship here is that the N-type transistor in the first differential amplifier output stage ONL, when are you? The output of the differential amplification output stage of A2 is kept at a low level, and the second differential amplification output stage is kept at a high level only when the N-type transistor of the first differential amplification output stage is turned off. (This is because, by doing this, the output of the second differential amplifier output stage is transferred to the inverter 9.
A transistor IO whose phase is inverted at
h It becomes possible to turn on only when the transistor is turned off. Here, since the input threshold voltage of the inverter 9 is higher, the above-described operation can be performed more accurately. In Fig. 1, the load of the regulator output has a capacitance ff1
ll or connected through switch 12. The potential fluctuation 19 of the regulator output 13 when the regulator output 13 becomes open (the charge of the capacitor ff1ll is removed) is expressed as the fourth
In Figure 0 shown in the figure, ON is when capacitor 11 and regulator output 13 are connected, and OFF is when capacitor ii
Tt! This is when the load is being unloaded. ■ The instantaneous regulator output at 0FF-ON rises to the positive power supply potential because the charge on the capacitor z is "0°." ■ The N-type transistor in the differential amplifier output stage is deeply biased and charges the capacitor fftll. ■ Due to the response delay of the differential amplifier stage, the N-type transistor is charged too much to the capacity Ill. ■ The N-type transistor is 0FFL, and the N-type transistor in the second differential amplifier output stage is also 0FFI. The output level of the output stage becomes a high level and the primary stage inverter 9
Since the output of is inverted and the transistor 10 inserted on the load side of the regulator output is turned on, the charge of the capacitor ti is removed by the transistor 10 and the constant current source 15. ■ As the regulator output voltage approaches the set potential, the N M ) transistor becomes 11<biased and stabilized 1
For example, when the regulated voltage is half the power supply voltage, the first differential amplification output stage N-type transistor 14 is turned on.
The resistance is equal to the ON resistance of the constant current source transistor 15.The relationship between the N-type transistor 16 of the second differential amplification output stage and the constant current source of the second differential amplification output stage is as described above. Since I27β2kuI]/β1 holds true, 11
Assuming that and I2 are equal, let β2=lOxBl. The output of the second differential amplification output stage is approximately 1/10 of the regulated voltage when viewed from the negative potential of 7, and the output of the next stage inverter 9 is at the positive power supply level, and the transistor 10 inserted in parallel with the regulator output load is OF F
be done. Here, due to the differential amplification stage delay, (1), (2), and (2) are repeated somewhat and converge. In addition, 19 in FIG. 4 is the potential fluctuation of the regulator output 13, 20 is the second differential amplification output stage potential, and 21 is the output potential of the inverter at the next stage of the second differential amplification output 19. It is a waveform. Further, although this embodiment has been described using a plus criterion, a minus criterion is also easily possible. [Effect of the invention 1] As described above, according to the invention, when the regulator output load capacitance is overcharged, the transistor in parallel with the output load is turned on and contributes to discharging the charge, so that the output ringing is reduced to speed <g. It has the effect of In addition, one transistor connected in parallel with the output load expresses the relationship between the constant current source of the second differential amplification stage and the amplification factor of the N-type transistor as the first amplification output. llt pressure lower than IQ!
,: The second differential amplifier output stage is set to 1, so it turns ON only when the output load capacitance is no longer charged.
However, it is always effective to achieve high-speed response with low current consumption. Minimum 5- to conventional regulator circuit
], it can be realized by simply adding a converter, and 1
It also has the advantage of being able to be integrated on a substrate.・Minus power supply...Positive power supply reference 1fif:i Constant current bypass 7;2. Sharp difference! 71 state width step/difference IIJ jf'!・Output voltage detection r, Q ・Second differential amplification output stage ・Phase inversion t9
第１図は本発明のレギュレータ回路の一実施例を示すレ
ギュレータ回路図。
第２［−］は従来のレギュレータ回路図。
第３図は従来のレギュレータ回路の応答波；１３図。
第、１図は本実施例のレギュレータ回路の応答波出願人
セイコーＬブソン株Δ二会社
代理人 弁理士 十 柳 雅 誉（伯１名）形［Ａ。FIG. 1 is a regulator circuit diagram showing one embodiment of the regulator circuit of the present invention. The second [-] is a conventional regulator circuit diagram. Figure 3 shows the response wave of a conventional regulator circuit; Figure 13. Fig. 1 shows the response wave of the regulator circuit of this embodiment.Applicant: Seiko L.Buson Co., Ltd.A.
Claims (1)
差動増幅出力段、レギュレータ出力電圧検出段を有し、
前記基準電源の出力を前記差動増幅段プラス入力に接続
し、前記出力電圧検出段出力を前記差動増幅段マイナス
入力に接続し、前記差動増幅段出力を前記差動増幅出力
段の入力とし、前記差動増幅出力段の出力をレギュレー
タ出力とするレギュレータ回路において、前記差動増幅
段出力を前記差動増幅出力段に接続すると共に、第２の
差動増幅出力段に接続し、前記第２の差動増幅出力段出
力の位相を反転する手段を有し、前記反転信号を、前記
レギュレータ出力の基準とする電源と、前記レギュレー
タ出力とに各々、ソースとドレインを接続した電界効果
型トランジスタ（プラス電源基準はＰ型、マイナス電源
基準はＮ型）のゲート電極に入力した事を特徴としたレ
ギュレータ回路。At least a reference power supply, constant current bias stage, differential amplification stage,
It has a differential amplification output stage and a regulator output voltage detection stage.
The output of the reference power supply is connected to the positive input of the differential amplifier stage, the output of the output voltage detection stage is connected to the negative input of the differential amplifier stage, and the output of the differential amplifier stage is connected to the input of the differential amplifier output stage. In a regulator circuit in which the output of the differential amplification output stage is a regulator output, the output of the differential amplification stage is connected to the differential amplification output stage and also connected to the second differential amplification output stage, and the output of the differential amplification stage is connected to the second differential amplification output stage, and a field-effect type having a means for inverting the phase of the output of the second differential amplification output stage, and having a source and a drain connected to a power supply that uses the inverted signal as a reference for the regulator output, and to the regulator output, respectively; A regulator circuit characterized by input to the gate electrode of a transistor (P type for positive power supply reference, N type for negative power supply reference).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1014422A JPH02194412A (en) | 1989-01-24 | 1989-01-24 | Regulator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1014422A JPH02194412A (en) | 1989-01-24 | 1989-01-24 | Regulator circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02194412A true JPH02194412A (en) | 1990-08-01 |
Family
ID=11860584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1014422A Pending JPH02194412A (en) | 1989-01-24 | 1989-01-24 | Regulator circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02194412A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000039923A (en) * | 1998-07-23 | 2000-02-08 | Nec Corp | Voltage regulator |
| JP2008217577A (en) * | 2007-03-06 | 2008-09-18 | Renesas Technology Corp | Internal voltage generation circuit |
| JP2009037303A (en) * | 2007-07-31 | 2009-02-19 | Ricoh Co Ltd | Arithmetic amplifier circuit, constant voltage circuit using the arithmetic amplifier circuit and equipment using the constant voltage circuit |
-
1989
- 1989-01-24 JP JP1014422A patent/JPH02194412A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000039923A (en) * | 1998-07-23 | 2000-02-08 | Nec Corp | Voltage regulator |
| JP2008217577A (en) * | 2007-03-06 | 2008-09-18 | Renesas Technology Corp | Internal voltage generation circuit |
| JP2009037303A (en) * | 2007-07-31 | 2009-02-19 | Ricoh Co Ltd | Arithmetic amplifier circuit, constant voltage circuit using the arithmetic amplifier circuit and equipment using the constant voltage circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4129794A (en) | Electrical integrated circuit chips | |
| JPH02194412A (en) | Regulator circuit | |
| US4468576A (en) | Inverter circuit having transistors operable in a shallow saturation region for avoiding fluctuation of electrical characteristics | |
| JPS59178014A (en) | Oscillation circuit | |
| US4668921A (en) | Power supply circuit | |
| JP3124179B2 (en) | Pulse width modulation circuit | |
| JP3714688B2 (en) | Control feedback type charge / voltage converter | |
| US3064141A (en) | Transistor amplifier circuits for square waves, with level setting and noise elimination | |
| TWI755242B (en) | Voltage converter and class-d amplifier | |
| US20050078530A1 (en) | Method and circuit configuration for digitizing a signal in an input buffer of a DRAM device | |
| JP2009159344A (en) | Oscillation circuit | |
| JPH029727B2 (en) | ||
| JPH06112737A (en) | Through rate increasing circuit | |
| KR100462119B1 (en) | offset voltage blanking circuit | |
| JPS5947396B2 (en) | hold circuit | |
| SU1314440A1 (en) | Differential amplifier | |
| EP1355427A9 (en) | Differential comparator circuit | |
| KR0136434B1 (en) | Oscillation circuit | |
| JP2587686Y2 (en) | Buffer amplifier | |
| JP3439142B2 (en) | Drive circuit | |
| JPH0256112A (en) | Frequency multiplier circuit | |
| JPH03162010A (en) | Gate driving circuit for static induction transistor | |
| KR0120534B1 (en) | Pulse compression circuit | |
| SU1050094A2 (en) | Power amplifier | |
| SU1387019A1 (en) | Device for extracting signal absolute value |