JPH0256112A - Frequency multiplier circuit - Google Patents
Frequency multiplier circuitInfo
- Publication number
- JPH0256112A JPH0256112A JP20125088A JP20125088A JPH0256112A JP H0256112 A JPH0256112 A JP H0256112A JP 20125088 A JP20125088 A JP 20125088A JP 20125088 A JP20125088 A JP 20125088A JP H0256112 A JPH0256112 A JP H0256112A
- Authority
- JP
- Japan
- Prior art keywords
- output
- capacitor
- constant current
- circuit
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 23
- 238000007599 discharging Methods 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims description 2
- 230000000737 periodic effect Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 230000008878 coupling Effects 0.000 abstract description 2
- 238000010168 coupling process Methods 0.000 abstract description 2
- 238000005859 coupling reaction Methods 0.000 abstract description 2
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は周波数てい倍回路に関し、特に遅延回路と排他
的論理和回路とによって周波数てい倍を行なう回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a frequency multiplier circuit, and more particularly to a circuit that performs frequency multiplication using a delay circuit and an exclusive OR circuit.
従来、この種の周波数てい倍回路は、第５図の回路図に
示すものがある。すなわち、入力端子１をインバータ２
の入力に接続し、インバータ２の出力をインバータ２２
の入力に抵抗２１を介して接続し、このインバータ２２
の入力に、一端を接地したコンデンサ２３の他端を接続
し、インバータ２２の出力と入力端子からの入力を入力
する排他的論理和（ＥＸ−ＯＲ＞回路１０の出力を出力
端子１１に接続する構成となっていた。Conventionally, this type of frequency multiplier circuit is shown in the circuit diagram of FIG. In other words, input terminal 1 is connected to inverter 2
and connect the output of inverter 2 to the input of inverter 22.
is connected to the input of this inverter 22 via a resistor 21.
Connect the other end of the capacitor 23 whose one end is grounded to the input of , and input the output of the inverter 22 and the input from the input terminal. It was configured.
上述した従来の周波数てい倍回路は、入力周波数ｆ（Ｈ
ｚ）、抵抗２１の抵抗値ＲΩ、コンデンサ２３の容量Ｃ
（Ｆ）、インバータ２２の論理スレッショルド電圧■↑
Ｈ（Ｖ）、電源電圧Ｅ （Ｖ）とすると、出力デユーテ
ィＤｒ（％）は次式で示される。The conventional frequency multiplier circuit described above has an input frequency f(H
z), resistance value RΩ of resistor 21, capacitance C of capacitor 23
(F), logic threshold voltage of inverter 22■↑
H (V) and the power supply voltage E (V), the output duty Dr (%) is expressed by the following equation.
この式から出力デユーティＤｒは、Ｃ，Ｒ。From this formula, the output duty Dr is C, R.
Ｖ７Ｈの製造バラツキの影響を直接受け、さらにｆ、Ｅ
の使用条件によっても変動を受けるといった重大の欠点
があった。Directly affected by manufacturing variations in V7H, f and E
It had a serious drawback that it was subject to fluctuations depending on the conditions of use.
本発明の目的は、このような問題を解決し、出力デユー
ティがコンデンサの容量値、抵抗値等の製造バラツキに
影響されず安定に出力される周波数てい倍回路の提供す
ることにある。SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and provide a frequency multiplier circuit whose output duty is stable without being affected by manufacturing variations in capacitance values, resistance values, etc. of capacitors.
本発明の構成は、周期的信号の入力信号を遅延させる遅
延回路と、この遅延回路の出力信号と前記入力信号との
排他的論理和をとる排他的論理和回路とを有し、この排
他的論理和回路の出力を前記入力信号のてい倍出力とし
た周波数てい倍回路において、前記遅延回路が、定電流
源と接続され前記入力信号により切換えられるスイッチ
ング回路とこのスイッチング回路の出力端に並列接続さ
れる第１のコンデンサとからなる充放電回路と、この充
放を回路の出力端から第２のコンデンサを介して結合さ
れたコンデンサ結合増幅器とを備えることを特徴とする
。The configuration of the present invention includes a delay circuit that delays an input signal of a periodic signal, and an exclusive OR circuit that takes an exclusive OR of the output signal of this delay circuit and the input signal, and In the frequency multiplier circuit in which the output of the OR circuit is multiplied by the input signal, the delay circuit is connected in parallel to a switching circuit connected to a constant current source and switched by the input signal, and an output terminal of this switching circuit. The present invention is characterized by comprising a charging/discharging circuit consisting of a first capacitor, and a capacitor-coupled amplifier in which this charging/discharging is coupled from the output end of the circuit via a second capacitor.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の回路図、第２図はけ本実施
例の動作を示すタイミング図である。第１図で入力端子
１はインバータ２の入力に接続され、このインバータ２
の出力とＭＯＳトランジスタ３．４のゲートが接続され
る。また、定電流源５を電源Ｖｌ）ｏとＭＯＳトランジ
スタ３のソースとの間に接続し、定電流源６をＭＯＳト
ランジスタ４のソースと接地との間に接続し、ＭｏＳト
ランジスタ３．４の両ドレインを一端を接地したコンデ
ンサ７の他端と接続し、この両トレインからコンデンサ
８を介して増幅器９の入力端と接続し、入力端子１と増
幅器９の出力とを入力とする排他的論理和１０の出力を
出力端子１１と接続している。FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a timing diagram showing the operation of this embodiment. In Fig. 1, input terminal 1 is connected to the input of inverter 2, and this inverter 2
The output of MOS transistor 3.4 is connected to the gate of MOS transistor 3.4. Further, a constant current source 5 is connected between the power supply Vl)o and the source of the MOS transistor 3, a constant current source 6 is connected between the source of the MOS transistor 4 and the ground, and both of the MoS transistors 3 and 4 are connected. The drain is connected to the other end of the capacitor 7 whose one end is grounded, and both trains are connected to the input end of the amplifier 9 via the capacitor 8, and the input terminal 1 and the output of the amplifier 9 are input. 10 outputs are connected to output terminal 11.
本実施例の回路によれば、増幅器９の入力波形は、第２
図に示す様に、定電流源５，６の値とコンデンサ７の値
で定まる傾斜を持った三角波となるため、増幅器９の入
力ではそのスレッショルド電圧Ｖ７Ｈを境に傾斜部が対
称となり、てい倍出力はデユーティ５０％の出力波形と
なる。According to the circuit of this embodiment, the input waveform of the amplifier 9 is
As shown in the figure, it becomes a triangular wave with a slope determined by the values of constant current sources 5 and 6 and the value of capacitor 7, so at the input of amplifier 9, the slope part becomes symmetrical with respect to the threshold voltage V7H as a boundary, and it is multiplied by The output is an output waveform with a duty of 50%.
なお、定電流値、コンデンサの容量値等に製造バラツキ
があっても、三角波の波高値を変化させるだけであり、
その傾斜部の対称性は損なわないので、出力デユーティ
はその影響を受けず、常に５０％となる。Furthermore, even if there are manufacturing variations in the constant current value, capacitance value, etc., it only changes the peak value of the triangular wave.
Since the symmetry of the slope is not impaired, the output duty is not affected by it and is always 50%.
第３図は本発明の第２の実施例の回路図である。本実施
例は、第１の実施例の定電流源５．６の代りに電圧制御
型定電流源５’、６’を用いて出力波形が５０％のデユ
ーティとなるようにフィードバック制御していることを
特徴とする。すなわち、入力端子１とインバータ２の入
力を接続し、インバータ２の出力とＭＯＳトランジスタ
３．４のゲートを接続し、一端を電源Ｖｒ、Ｄに接続し
た電圧制御定電流源５′の他端をＭＯＳ）ランジスタ３
のソースに接続し、一端を接地した電圧制御定電流源６
′の他端をＭＯＳトランジスタ４のソースに接続し、Ｍ
ＯＳトランジスタ３，４を両ドレンインと一端を接地し
たコンデンサ７の他端と、一端を増幅器９の入力と接続
したコンデンサ８の他端とを接続し、入力端子１と増幅
器９の出力を入力とする排他的論理和１０の出力を出力
端子１１とインバータ１２の入力に接続し、インバータ
１２の出力を入力とする積分器１３の出力を比較器１４
のプラス入力に接続し、基準電圧１５を比較器１４のマ
イナス入力に接続し、比較器１４の出力を入力とする積
分器１６の出力を電圧制御定電流源５’ 、６’の電圧
制御入力に接続する。この基準電圧１５は電源電圧ＶＤ
Ｄの１／２としている。FIG. 3 is a circuit diagram of a second embodiment of the present invention. In this embodiment, voltage-controlled constant current sources 5' and 6' are used in place of the constant current sources 5 and 6 of the first embodiment, and feedback control is performed so that the output waveform has a duty of 50%. It is characterized by That is, the input terminal 1 and the input of the inverter 2 are connected, the output of the inverter 2 and the gate of the MOS transistor 3.4 are connected, and the other end of the voltage controlled constant current source 5' is connected to the power source Vr, D. MOS) transistor 3
Voltage controlled constant current source 6 connected to the source of
'The other end is connected to the source of MOS transistor 4, and M
The OS transistors 3 and 4 are connected to both drains, the other end of a capacitor 7 whose one end is grounded, and the other end of a capacitor 8 whose one end is connected to the input of an amplifier 9, and the input terminal 1 and the output of the amplifier 9 are connected as inputs. The output of the exclusive OR 10 is connected to the output terminal 11 and the input of the inverter 12, and the output of the integrator 13 whose input is the output of the inverter 12 is connected to the comparator 14.
The reference voltage 15 is connected to the negative input of the comparator 14, and the output of the integrator 16 whose input is the output of the comparator 14 is used as the voltage control input of the voltage controlled constant current sources 5' and 6'. Connect to. This reference voltage 15 is the power supply voltage VD
It is set to 1/2 of D.
この回路によれは、第４図の様に、出力端子１１のデユ
ーティが５０％を越えるときには、積分器１３の出力は
、基準電圧１５のＶ ＤＤ／ ２未満となり、比較器１
４の出力はロウレベルとなり、積分器１６の出力を徐々
に低下させる。この積分器１６の出力が低下すると、電
圧制御定電流源５’ 、６’の電流値が小さくなり、遅
延時間が長くなりｄ３カデューティを５０％に近づける
ことができる。また、逆に出力デユーティが５０％を丁
形るときには、前述の場合と全く反対の動作をし、積分
器１６の出力が徐々に上昇し、電圧制御定電流源５’、
６’の電流値を大きくし、遅延時間が短くなり、出力デ
ユーティを５０％に近づけることができる。According to this circuit, when the duty of the output terminal 11 exceeds 50% as shown in FIG.
The output of the integrator 16 becomes low level, and the output of the integrator 16 gradually decreases. When the output of the integrator 16 decreases, the current value of the voltage-controlled constant current sources 5' and 6' decreases, the delay time increases, and the d3 caduality can approach 50%. Conversely, when the output duty reaches 50%, the operation is completely opposite to that in the above case, and the output of the integrator 16 gradually increases, and the voltage-controlled constant current source 5',
By increasing the current value of 6', the delay time becomes shorter, and the output duty can be brought closer to 50%.
以上説明したように本発明は、コンデンサの充放電を定
電流源で行ない、その出力三角波をコンデンサ結合増幅
し、入力信号と増幅器出力の排他的論理和をとることに
より、定電流値、コンデンサの容量値等の製造バラツキ
や使用条件によらず、出力デユーティがほぼ５０％の周
波数でい倍回路を得ることができるという効果がある。As explained above, the present invention charges and discharges a capacitor using a constant current source, amplifies the output triangular wave by coupling the capacitor, and takes the exclusive OR of the input signal and the output of the amplifier. There is an effect that a frequency multiplier circuit with an output duty of approximately 50% can be obtained regardless of manufacturing variations in capacitance values, etc., or usage conditions.
第１図、第３図は本発明の周波数てい倍回路の第１およ
び第２の実施例の回路図、第２図、第４図は第１図およ
び第３図の動作タイミング図、第５図は従来の周波数て
い倍回路の一例の回路図である。
１・・・入力端子、２．１２．２２・・・インバータ、
３．４・・・ＭＯＳトランジスタ、５．６・・・定電流
源、５’、６’・・・電圧制御型定電流源、７，８゜２
３・・・コンデンサ、９・・・増幅器、１０・・・排他
的論理和回路、１１・・・出力端子、１３．１６・・・
積分器、１４・・・比較器、１５・・・基準電源、２１
・・・抵抗。1 and 3 are circuit diagrams of the first and second embodiments of the frequency multiplier circuit of the present invention, FIGS. 2 and 4 are operation timing diagrams of FIGS. 1 and 3, and FIG. The figure is a circuit diagram of an example of a conventional frequency multiplier circuit. 1...Input terminal, 2.12.22...Inverter,
3.4...MOS transistor, 5.6...constant current source, 5', 6'...voltage controlled constant current source, 7,8゜2
3... Capacitor, 9... Amplifier, 10... Exclusive OR circuit, 11... Output terminal, 13.16...
Integrator, 14... Comparator, 15... Reference power supply, 21
···resistance.
Claims (2)
この遅延回路の出力信号と前記入力信号との排他的論理
和をとる排他的論理和回路とを有し、この排他的論理和
回路の出力を前記入力信号のてい倍出力とした周波数て
い倍回路において、前記遅延回路が、定電流源と接続さ
れ前記入力信号により切換えられるスイッチング回路と
このスイッチング回路の出力端に並列接続される第１の
コンデンサとからなる充放電回路と、この充放電回路の
出力端から第２のコンデンサを介して結合されたコンデ
ンサ結合増幅器とを備えることを特徴とする周波数てい
倍回路。(1) a delay circuit that delays an input signal of a periodic signal;
A frequency multiplier circuit comprising an exclusive OR circuit that takes an exclusive OR of the output signal of the delay circuit and the input signal, and the output of the exclusive OR circuit is an output multiple of the input signal. The delay circuit includes a charging/discharging circuit comprising a switching circuit connected to a constant current source and switched by the input signal, and a first capacitor connected in parallel to the output terminal of the switching circuit; A frequency multiplier circuit comprising: a capacitor-coupled amplifier coupled from an output end via a second capacitor.
流源が出力波形を積分した電圧により制御されたもので
ある請求項１記載の周波数てい倍回路。(2) The frequency multiplier circuit according to claim 1, wherein the constant current source is a voltage-controlled constant current source, and the constant current source is controlled by a voltage obtained by integrating an output waveform.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63201250A JP2690512B2 (en) | 1987-11-06 | 1988-08-12 | Frequency multiplier circuit |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-281455 | 1987-11-06 | ||
| JP28145587 | 1987-11-06 | ||
| JP63201250A JP2690512B2 (en) | 1987-11-06 | 1988-08-12 | Frequency multiplier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0256112A true JPH0256112A (en) | 1990-02-26 |
| JP2690512B2 JP2690512B2 (en) | 1997-12-10 |
Family
ID=26512686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63201250A Expired - Lifetime JP2690512B2 (en) | 1987-11-06 | 1988-08-12 | Frequency multiplier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2690512B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100464932B1 (en) * | 1997-03-31 | 2005-02-28 | 매그나칩 반도체 유한회사 | Method and apparatus for doubling a clock signal using phase interpolation |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53122351A (en) * | 1977-04-01 | 1978-10-25 | Hitachi Ltd | Generating circuit for double frequency signal |
| JPS59156017A (en) * | 1983-02-25 | 1984-09-05 | Nec Corp | Clock multiplying circuit |
-
1988
- 1988-08-12 JP JP63201250A patent/JP2690512B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53122351A (en) * | 1977-04-01 | 1978-10-25 | Hitachi Ltd | Generating circuit for double frequency signal |
| JPS59156017A (en) * | 1983-02-25 | 1984-09-05 | Nec Corp | Clock multiplying circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100464932B1 (en) * | 1997-03-31 | 2005-02-28 | 매그나칩 반도체 유한회사 | Method and apparatus for doubling a clock signal using phase interpolation |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2690512B2 (en) | 1997-12-10 |
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