JPH02105455A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH02105455A JPH02105455A JP63258665A JP25866588A JPH02105455A JP H02105455 A JPH02105455 A JP H02105455A JP 63258665 A JP63258665 A JP 63258665A JP 25866588 A JP25866588 A JP 25866588A JP H02105455 A JPH02105455 A JP H02105455A
- Authority
- JP
- Japan
- Prior art keywords
- collector
- transistor
- power supply
- constant potential
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000000034 method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Dram (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に係り、特にＥＣＬ（エミ
ッタ結合論理）インターフェース・デバイ−の１０にタ
イプと１００にタイプとの半導体記憶素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuit devices, and more particularly to semiconductor memory elements of type 10 and type 100 of ECL (emitter-coupled logic) interface devices.
第６図に示すように、従来の１００にタイプのＥＣＬイ
ンターフェース・デバイスは、Ｓ入力端子９．８入力端
子１０を各々ベースに有する第１゜第２のトランジスタ
３，４からなる差動増幅器を設け、第１のトランジスタ
３のコレクタが抵抗５を介してＶｃｃ定電位源に接続さ
れ、第２のトランジスタ４のコレクタが抵抗６を介して
ｓ ＶＣＣ定電位源に接続され、第２のトランジスタ４
のコレクタがベースに接続された出力トランジスタ１３
を設け、この出力トランジスタ１３のエミッタが０出力
端子に接続され、コレクタがＶＣＣＡ定電位源に接続さ
れる。As shown in FIG. 6, the conventional 100 type ECL interface device includes a differential amplifier consisting of first and second transistors 3 and 4 each having an S input terminal 9 and an input terminal 10 at their bases. The collector of the first transistor 3 is connected to the VCC constant potential source through the resistor 5, the collector of the second transistor 4 is connected to the VCC constant potential source through the resistor 6, and the second transistor 4 is connected to the VCC constant potential source through the resistor 6.
an output transistor 13 whose collector is connected to its base;
The emitter of this output transistor 13 is connected to the 0 output terminal, and the collector is connected to a VCCA constant potential source.
また、抵抗５，６は共通接続され、さらに第７図にも示
すように、デュアル・インライン・パッケージ１１の端
のリード１５に接続され、一方出力トランジスタ１３の
コレクタ拡他の端のリード１６に接続される６また、第
１．第２のトランジスタ３，４のコレクタ間には、互い
に逆極性に接続されたダイオード１．２の並列体と抵抗
１２との直列体が接続される。この直列体は、１０にタ
イプのＥＣＬインターフェース・デバイスでは除去され
る。Further, the resistors 5 and 6 are connected in common, and furthermore, as shown in FIG. 6 also connected to the first. Between the collectors of the second transistors 3 and 4, a parallel body of diodes 1.2 connected with opposite polarities and a series body of a resistor 12 are connected. This series is eliminated in 10-type ECL interface devices.
以上水したように、ＥＣＬインターフェース・デバイス
には、１０にタイプと１ｏｏＫタイプとがある。双方を
外部から識別する場合、双方のビンコネタシ１ンが異な
る時は容易であるが、１０にと１００にとで同じ場合に
は判別が困難である。しかしながら１０ タイプの出力
レベルは、温度に対して傾きをもっているが１ １００
にタイプは温度補償回路があるため、第８図、第９図に
示すように。As mentioned above, there are 10 types and 1ooK types of ECL interface devices. When identifying both machines from the outside, it is easy when the bin connections 1 and 10 are different, but it is difficult to identify them when the machines 10 and 100 are the same. However, the output level of the 10 type has a slope with respect to temperature.
This type has a temperature compensation circuit, as shown in Figures 8 and 9.
温度に対してほぼフラットな出力特性を示す。Shows almost flat output characteristics with respect to temperature.
第８図において、出力レベルのうち高位（ｈｉｇｈ）側
の温度特性が示されている。１０にタイプ（電源電圧−
５，２■で使用されるタイプ）は点線で示され、温度特
性を有するが、１００にタイプ（電源電圧４．５■で使
用されるタイプ）は実線で示され、温度特性がは譬一定
である。In FIG. 8, temperature characteristics on the high side of the output level are shown. Type 10 (power supply voltage -
The type used in 5, 2■) is shown by a dotted line and has temperature characteristics, but the type 100 (type used at a power supply voltage of 4.5■) is shown as a solid line, and the temperature characteristics are not constant. It is.
第９図において、出力レベルのうち低位（＋ｏｗ）側の
温度特性が示されておシ、同様に１００にタイプは温度
特性がはソ一定である。この特性を利用して、出力レベ
ルの温度特性をしらべ、１０にと１００にとを外部から
識別することができる。In FIG. 9, the temperature characteristics on the lower (+OW) side of the output level are shown.Similarly, the temperature characteristics of type 100 are constant. Using this characteristic, it is possible to examine the temperature characteristics of the output level and distinguish between 10 and 100 from the outside.
前述した従来の方法では、出力レベルの温度特性をひと
つひとつとらなければならないので、非常に手間がかか
るし、また製品の製造バラツキや、測定系の不具合によ
っては温度特性からだけでは。In the conventional method mentioned above, the temperature characteristics of each output level must be determined one by one, which is extremely time-consuming, and depending on manufacturing variations or problems with the measurement system, temperature characteristics alone cannot be used.
判断しがたいという欠点もある。It also has the disadvantage of being difficult to judge.
本発明の目的は、前記欠点が解決され、温度特性を測定
せずとも、タイプの識別ができるようにした半導体集積
回路装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device in which the above drawbacks are solved and the type can be identified without measuring temperature characteristics.
本発明の構成は、第１．第２のトランジスタを備えた差
動増幅回路を設け、前記第１のトランジスタのコレクタ
が第１の抵抗を介して第１の定電位源に接続され、前記
第２のトランジスタのコレクタが第２の抵抗を介して第
２の定電位源に接続され、前記第１又は第２のトランジ
スタのコレクタにベースが接続された出力トランジスタ
を設け、前記出力トランジスタのコレクタが前記第２の
定電位源に接続されていることを特徴とする。The configuration of the present invention is as follows. A differential amplifier circuit including a second transistor is provided, the collector of the first transistor is connected to a first constant potential source via a first resistor, and the collector of the second transistor is connected to a second constant potential source. an output transistor connected to a second constant potential source via a resistor and having a base connected to a collector of the first or second transistor; a collector of the output transistor is connected to the second constant potential source; It is characterized by being
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の半導体集積回路装置を示す
回路図、第２図は第１図の半導体素子を内蔵したパッケ
ージを示す上面図である。これら図において、本発明の
一実施例の半導体集積回路装置が従来例と異なる点は、
出力トランジスタ１３０ベースに接続している抵抗６を
つる最高電位ＶｃｃｌｌＥ源と出力トランジスタ１３の
コレクタをつるＶＣＣＡ電源とが電気的にショートされ
、もう−方の抵抗５をつるｖｃｃ ２電源とは電気的に
分離されている点である。さらにｓ ＶＣＣＡ電源とシ
ョートされたＶＣＣｌ電源と、ＶＣＣ！電源とは、第２
図に示すように、パッケージ上でも別々のり−ド７゜８
に接続されている。即ちｓ ＶＣＣ２電源はパッケージ
１１のリード７に接続され、ＶＣＣＩ＋ＶＣＣＡ電源は
共に、パッケージ１１のリード８に接続される。FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a top view showing a package incorporating the semiconductor element of FIG. 1. In these figures, the semiconductor integrated circuit device according to the embodiment of the present invention differs from the conventional example as follows.
The highest potential VccllE source that connects the resistor 6 connected to the base of the output transistor 130 and the VCCA power source that connects the collector of the output transistor 13 are electrically shorted, and the Vcc2 power source that connects the other resistor 5 is electrically shorted. The point is that it is separated into two parts. In addition, the VCCA power supply and the VCCl power supply, which is shorted, and the VCC! The power supply is the second
As shown in the figure, separate glue 7°8 on the package.
It is connected to the. That is, the s VCC2 power supply is connected to lead 7 of package 11, and the VCCI+VCCA power supplies are both connected to lead 8 of package 11.
この構成では、ｖｃｃ２電源電圧と出力ビン（リード）
との間の電圧−電流特性を、リード７とリード８との間
に測定器を接続して測定ができる。第５図に示すように
、ＶＣＣ２電源と、出力トランジスタ１３のエミッタ（
出力ＰＩＮ）とのＶ−Ｉ特性を測定してみれば、１００
にタイプのときはダイオード２を介して％ ２段分の順
方向電圧２Ｖｆで電流が流れだす。一方、１０にタイプ
のときはダイオード２がないため、ダイオード１がブレ
ークダウンするまで電流は流れない。このことによって
、外部から１０にタイプと１００にタイプとの識別が可
能となる。In this configuration, the vcc2 supply voltage and the output bin (lead)
The voltage-current characteristics between the leads 7 and 8 can be measured by connecting a measuring device between the leads 7 and 8. As shown in FIG. 5, the VCC2 power supply and the emitter of the output transistor 13 (
If you measure the V-I characteristic with output PIN), it will be 100
In the case of type 2, a current starts to flow through diode 2 with a forward voltage of 2Vf for 2 stages. On the other hand, in the case of type 10, there is no diode 2, so no current flows until diode 1 breaks down. This makes it possible to distinguish between the 10th type and the 100th type from the outside.
第３図は本発明の他の実施例の半導体集積回路装置を示
す回路図、第４図は第５図の半導体素子を内蔵したパッ
ケージを示す上面図である。これら図において、本実施
例は、出力トランジスタ１３のベースとコレクタを別々
の最高電位源に接続している。即チ、ベースはトランジ
スタ３のコレクタに、コレクタはリード８に接続されて
おり、出力の影響が、出力のベースに伝達しない様にし
ている。これにより、出力の発振等の可能性はなくなる
。FIG. 3 is a circuit diagram showing a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 4 is a top view showing a package incorporating the semiconductor element of FIG. 5. In these figures, in this embodiment, the base and collector of the output transistor 13 are connected to separate highest potential sources. That is, the base is connected to the collector of the transistor 3, and the collector is connected to the lead 8, so that the influence of the output is not transmitted to the base of the output. This eliminates the possibility of output oscillation.
本実施例も、最高電位ＰＩＮと出力ＰＩＮとのＶ−Ｉ特
性を見ることで、１０にタイプと１００にタイプとの識
別ができる。In this embodiment as well, the 10 type and the 100 type can be distinguished by looking at the VI characteristics of the highest potential PIN and the output PIN.
以上説明したように、本発明は、外部よりＶｃｃＰＩＮ
と出力ＰＩＮとの間のＶ−Ｉ％性をみることＫよシ、１
０にと１００にとの識別が可能となる効果がある。As explained above, the present invention allows VccPIN to be input from the outside.
Check the V-I% between the output PIN and the output PIN.
This has the effect of making it possible to distinguish between 0 and 100.
積回路装置を示す回路図、第７図は第６図の装置を内蔵
したパッケージを示す上面図、第８図は従来の半導体集
積回路装置の出力レベル（高位）の温度特性を示す特性
図、第９図は従来の半導体集積回路装置の出力レベル（
低位）の温度特性を示す特性図である。7 is a top view showing a package incorporating the device shown in FIG. 6; FIG. 8 is a characteristic diagram showing the temperature characteristics of the output level (high level) of a conventional semiconductor integrated circuit device; Figure 9 shows the output level (
FIG.
１．２・・・ダイオード、３，４．１３・・・トランジ
スタ、５，６．１２・・・抵抗、７，８・・・リード、
９，１０・・・入力端子、１１・・・パッケージ、１４
・・・出力端子。1.2...Diode, 3,4.13...Transistor, 5,6.12...Resistor, 7,8...Lead,
9, 10... Input terminal, 11... Package, 14
...Output terminal.
ζζ
Claims (1)
、前記第１のトランジスタのコレクターが第１の抵抗を
介して第１の定電位源に接続され、前記第２のトランジ
スタのコレクタが第２の抵抗を介して第２の定電位源に
接続され、前記第１又は第２のトランジスタのコレクタ
にベースが接続された出力トランジスタを設け、前記出
力トランジスタのコレクタが前記第２の定電位源に接続
されていることを特徴とする半導体集積回路装置。A differential amplifier circuit including first and second transistors is provided, the collector of the first transistor is connected to a first constant potential source via a first resistor, and the collector of the second transistor is connected to a first constant potential source through a first resistor. an output transistor connected to a second constant potential source via a second resistor and having a base connected to the collector of the first or second transistor; the collector of the output transistor is connected to the second constant potential source; A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is connected to a power source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63258665A JP2705142B2 (en) | 1988-10-13 | 1988-10-13 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63258665A JP2705142B2 (en) | 1988-10-13 | 1988-10-13 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02105455A true JPH02105455A (en) | 1990-04-18 |
| JP2705142B2 JP2705142B2 (en) | 1998-01-26 |
Family
ID=17323400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63258665A Expired - Lifetime JP2705142B2 (en) | 1988-10-13 | 1988-10-13 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2705142B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0428088A (en) * | 1990-05-23 | 1992-01-30 | Samsung Electron Co Ltd | Semiconductor ic chip |
-
1988
- 1988-10-13 JP JP63258665A patent/JP2705142B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0428088A (en) * | 1990-05-23 | 1992-01-30 | Samsung Electron Co Ltd | Semiconductor ic chip |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2705142B2 (en) | 1998-01-26 |
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