JP2521486B2 - Classification method of integrated circuit device - Google Patents
Classification method of integrated circuit deviceInfo
- Publication number
- JP2521486B2 JP2521486B2 JP62179744A JP17974487A JP2521486B2 JP 2521486 B2 JP2521486 B2 JP 2521486B2 JP 62179744 A JP62179744 A JP 62179744A JP 17974487 A JP17974487 A JP 17974487A JP 2521486 B2 JP2521486 B2 JP 2521486B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- classifying
- circuit device
- circuit devices
- characteristic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、集積回路装置の分類方法に関するものであ
る。The present invention relates to a method of classifying integrated circuit devices.
（従来の技術） 従来、オペアンプ、コンパレータ等同一機能、同一電
極配列、同一電極数のものが増えてきており、この種の
分類検査としては、そのものの特性を如実に示す交流特
性値であるノイズ特性、スルーレート、立上り特性、立
下り特性等の交流特性値を測定して識別し、品種分類を
していた。(Prior Art) Conventionally, an operational amplifier, a comparator, and the like having the same function, the same electrode arrangement, and the same number of electrodes have been increasing. As a classification inspection of this type, noise that is an AC characteristic value that clearly shows the characteristics of itself is increasing. AC characteristic values such as characteristics, slew rate, rising characteristics, and falling characteristics were measured and identified, and product types were classified.
（発明が解決しようとする問題点） 上記従来の方法は完成品での交流特性検査工程であ
り、量産製造工程での最終工程でもあり、集積回路装置
の量産製造工程において、マーキング工程その他工程の
煩雑化を招き、原価低減ができず、量産製造工程の自動
化を阻む欠点があった。(Problems to be Solved by the Invention) The above-described conventional method is an AC characteristic inspection process for a finished product and is also a final process in a mass production process. In the mass production process of an integrated circuit device, a marking process and other processes are performed. There is a drawback that it causes complication, cost cannot be reduced, and automation of mass production process is prevented.
本発明の目的は、従来の欠点を解消し、集積回路装置
の特性改良等のバージョン分類方法は特定の電極間のダ
イオード素子特性またはダイオード素子と抵抗素子の直
列特性検査項目で電気的特性を判別する集積回路装置の
分類方法を提供することである。The object of the present invention is to solve the conventional drawbacks and to determine the electrical characteristics by the version classification method such as the characteristic improvement of the integrated circuit device by the diode element characteristic between specific electrodes or the series characteristic inspection item of the diode element and the resistance element. A method of classifying integrated circuit devices is provided.
（問題点を解決するための手段） 本発明の集積回路装置の分類方法は、同一機能、同一
の電極配列、同一の電極数を有する集積回路装置の特性
改良のバージョンを分類する手段として、特定の電極間
に特性改良毎あるいは品種毎に異なるダイオード素子を
埋設することにより分類を行うものであり、また異なる
ダイオード素子として、単一でなく複数個直列接続した
ものであり、また異なるダイオード素子として、ダイオ
ードと直列に抵抗素子を接続形成したものであり、さら
に異なるダイオード素子として、ツェナーダイオード素
子を接続形成したものである。(Means for Solving Problems) The method for classifying integrated circuit devices according to the present invention is specified as means for classifying versions of improved characteristics of integrated circuit devices having the same function, the same electrode arrangement, and the same number of electrodes. Classification is made by embedding different diode elements for each characteristic improvement or for each product type between the electrodes of, and as different diode elements, a plurality of diodes are connected in series instead of a single diode element. A resistor element is connected and formed in series with the diode, and a Zener diode element is further connected and formed as a different diode element.
（作用） 本発明によれば、半導体集積回路装置の特性改良等の
バージョン分類方法は特定の電極間のダイオード素子の
直列特性またはダイオード素子と抵抗素子の並列接続特
性であり、直列特性検査項目で電気的特性を判別するこ
とにより分類が可能である。(Operation) According to the present invention, the version classification method such as the characteristic improvement of the semiconductor integrated circuit device is the series characteristic of the diode element between the specific electrodes or the parallel connection characteristic of the diode element and the resistance element. Classification is possible by discriminating the electrical characteristics.
（実施例） 本発明の一実施例を第１図ないし第３図に基づいて説
明する。第１図は本発明の実施回路図である。同図にお
いて、点線で囲んだ部分が本発明による分類区分のため
のダイオード素子である。端子1,2はオフセット調整端
子、３は正転入力端子、４は反転入力端子、５は負電源
電圧印加端子、６は正電源電圧印加端子であり、７は出
力端子である。(Embodiment) An embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is an implementation circuit diagram of the present invention. In the figure, the portion surrounded by a dotted line is a diode element for classification according to the present invention. Terminals 1 and 2 are offset adjustment terminals, 3 is a normal input terminal, 4 is an inverting input terminal, 5 is a negative power supply voltage application terminal, 6 is a positive power supply voltage application terminal, and 7 is an output terminal.
たとえば、プロセスの変更や、マスク設計ルールの変
更、チップシュリンク化、特性改良による素子変更、あ
るいは回路の変更等があったとき、同一機能、同一電極
配列、同一電極数の場合には分類が難しい。しかし、本
発明によれば、端子５に電流を印加し、端子１を接地す
ることにより、第１図の回路では第３図Ａに示すような
１個のダイオード素子特性（1VBE＝0.7V）を示し、第１
図の点線部分をさらに改良変更した実施回路図を示す第
２図の回路では第３図Ｂに示すような２個のダイオード
素子特性（2VBE＝1.4V）を示し、直流検査により容易に
判別することが可能である。勿論、特定電極として従来
技術による集積回路装置と機能特性が変化しない電極を
選択して実施する。なお、Q1〜Q20はトランジスタ、C1
は容量、R1〜R11は抵抗器であり、D1,D2はダイオードで
ある。For example, if there is a process change, mask design rule change, chip shrinking, element change due to characteristic improvement, or circuit change, it is difficult to classify if there is the same function, same electrode arrangement, and same number of electrodes. . However, according to the present invention, by applying a current to the terminal 5 and grounding the terminal 1, one diode element characteristic (1V BE = 0.7V in the circuit of FIG. 1 as shown in FIG. 3A) is obtained. ) Indicates the first
The circuit shown in Fig. 2, which shows the implementation circuit diagram in which the dotted line part of the figure is further improved and modified, shows two diode element characteristics (2V BE = 1.4V) as shown in Fig. 3B, which can be easily identified by DC inspection. It is possible to Of course, as the specific electrode, an integrated circuit device according to the prior art and an electrode whose functional characteristics do not change are selected and implemented. Q 1 to Q 20 are transistors, C 1
Is a capacitance, R 1 to R 11 are resistors, and D 1 and D 2 are diodes.
なお、本発明はバイポラー集積回路に限らず、他の半
導体集積回路装置において同様に適用することができ
る。The present invention is not limited to the bipolar integrated circuit, but can be similarly applied to other semiconductor integrated circuit devices.
（発明の効果） 本発明によれば、半導体集積回路装置の同一機能、同
一電極配列、同一電極を有する集積回路装置の分類を交
流特性の差だけで分類するのでなく直流特性で検査可能
となり、また直流検査装置の使用により高速、高精度で
分類が可能となり、この種類の集積回路装置の混入防止
等の作業性改善、能率、信頼性向上がはかれ、その実用
上の効果は大である。(Effect of the Invention) According to the present invention, the classification of integrated circuit devices having the same function, the same electrode arrangement, and the same electrodes of the semiconductor integrated circuit device can be inspected not only by the difference in the AC characteristics but also by the DC characteristics. In addition, the use of a DC inspection device enables high-speed and high-accuracy classification, which improves workability such as prevention of mixing of this type of integrated circuit device, improves efficiency and reliability, and has a great practical effect. .
第１図は本発明の一実施例による実施回路図、第２図は
第１図の一部をさらに改良変更した実施回路図、第３図
は第１図および第２図にダイオード素子を追加したとき
の特性図である。 1,2……オフセット調整端子、３……正転入力端子、４
……反転入力端子、５……負電源電圧印加端子、６……
正電源電圧印加端子、７……出力端子、Q1〜Q20……ト
ランジスタ、C1……容量、R1〜R11……抵抗器、D1,D2…
…ダイオード。FIG. 1 is an implementation circuit diagram according to an embodiment of the present invention, FIG. 2 is an implementation circuit diagram in which a part of FIG. 1 is further improved and modified, and FIG. 3 is a diode element added to FIGS. 1 and 2. It is a characteristic diagram when doing. 1,2 …… Offset adjustment terminal, 3 …… Forward rotation input terminal, 4
…… Inverting input terminal, 5 …… Negative power supply voltage applying terminal, 6 ……
A positive power supply voltage application terminal, 7 ...... output terminal, Q 1 to Q 20 ...... transistor, C 1 ...... capacity, R 1 to R 11 ...... resistor, D 1, D 2 ...
…diode.
Claims (4)
を有する集積回路装置の特性改良のバージョンを分類す
る手段として、特定の電極間に特性改良毎あるいは品種
毎に異なるダイオード素子を埋設することにより分類を
行うことを特徴とする集積回路装置の分類方法。1. As a means for classifying the version of the characteristic improvement of an integrated circuit device having the same function, the same electrode arrangement, and the same number of electrodes, different diode elements are embedded between specific electrodes for each characteristic improvement or each product type. A method for classifying integrated circuit devices, characterized in that classification is performed by
複数個直列接続してなることを特徴とする特許請求の範
囲第（１）項記載の集積回路装置の分類方法。2. The method for classifying integrated circuit devices according to claim 1, wherein a plurality of different diode elements are connected in series instead of being single.
と直列に抵抗素子を接続形成してなることを特徴とする
特許請求の範囲第（１）項記載の集積回路装置の分類方
法。3. A method of classifying integrated circuit devices according to claim 1, wherein a resistance element is connected and formed in series with the diode as a different diode element.
イオード素子を接続形成してなることを特徴とする特許
請求の範囲第（１）項記載の集積回路装置の分類方法。4. A method of classifying integrated circuit devices according to claim 1, wherein Zener diode elements are connected and formed as different diode elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62179744A JP2521486B2 (en) | 1987-07-18 | 1987-07-18 | Classification method of integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62179744A JP2521486B2 (en) | 1987-07-18 | 1987-07-18 | Classification method of integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6423546A JPS6423546A (en) | 1989-01-26 |
| JP2521486B2 true JP2521486B2 (en) | 1996-08-07 |
Family
ID=16071105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62179744A Expired - Fee Related JP2521486B2 (en) | 1987-07-18 | 1987-07-18 | Classification method of integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2521486B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2751701B2 (en) * | 1991-12-24 | 1998-05-18 | 日本電気株式会社 | Semiconductor integrated circuit |
| US6965160B2 (en) | 2002-08-15 | 2005-11-15 | Micron Technology, Inc. | Semiconductor dice packages employing at least one redistribution layer |
-
1987
- 1987-07-18 JP JP62179744A patent/JP2521486B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6423546A (en) | 1989-01-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |