JPH01189102A - Manufacture of electrodes of circuit component - Google Patents
Manufacture of electrodes of circuit componentInfo
- Publication number
- JPH01189102A JPH01189102A JP1431088A JP1431088A JPH01189102A JP H01189102 A JPH01189102 A JP H01189102A JP 1431088 A JP1431088 A JP 1431088A JP 1431088 A JP1431088 A JP 1431088A JP H01189102 A JPH01189102 A JP H01189102A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- elements
- layers
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims description 20
- 239000010410 layer Substances 0.000 abstract description 73
- 239000011241 protective layer Substances 0.000 abstract description 6
- 239000003795 chemical substances by application Substances 0.000 abstract description 3
- 229910002482 Cu–Ni Inorganic materials 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 229910045601 alloy Inorganic materials 0.000 abstract 1
- 239000000956 alloy Substances 0.000 abstract 1
- 229910052802 copper Inorganic materials 0.000 abstract 1
- 229910052759 nickel Inorganic materials 0.000 abstract 1
- 230000000717 retained effect Effects 0.000 abstract 1
- 229910052709 silver Inorganic materials 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 1
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical class [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000008096 xylene Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、各種電気、電子機器に用いられる回路部品の
電極製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing electrodes of circuit components used in various electrical and electronic devices.
（従来の技術）
この種の回路部品の電極製造方法の従来例を、第７図に
示す集合体処理により製造されるチップ型部品としての
抵抗器２０を例にとって説明する。(Prior Art) A conventional method for manufacturing electrodes of this type of circuit component will be described by taking as an example a resistor 20 as a chip type component manufactured by an assembly process shown in FIG.
従来方法は、基板２１上に抵抗体層２２を形成し、さら
にこの抵抗体層２２の両側上面に接合電極層２３ａ、２
３ｂを形成した後、前記接合電極層２３ａ、２３ｂの上
面からそれぞれ抵抗体層２２の両側端部、基板２１の上
面２両側面を経てこの基板２１の下面側に至る領域まで
対称配置に一対の端部電極部２４ａ、２４ｂを形成する
。In the conventional method, a resistor layer 22 is formed on a substrate 21, and bonding electrode layers 23a, 2 are further formed on both upper surfaces of this resistor layer 22.
After forming the bonding electrode layers 23a and 23b, a pair of symmetrically arranged electrodes are formed from the upper surface of the bonding electrode layers 23a and 23b to the region extending through both ends of the resistor layer 22, both sides of the upper surface 2 of the substrate 21, and to the lower surface side of the substrate 21. End electrode portions 24a and 24b are formed.
この俊、前記端部電極部２４ａ、２４ｂの上面の一部９
両接合電極層２３ａ、２３ｂの露出部分及び抵抗体層２
２の露出部分を例えば合成樹脂製の保護層２５により被
覆することにより、有効抵抗値エリア（縦方向の長さ０
．９ａｎ程度）Ｗ２の抵抗器２０を得るようにしている
。In this case, a portion 9 of the upper surface of the end electrode portions 24a, 24b
Exposed portions of both junction electrode layers 23a and 23b and resistor layer 2
By covering the exposed portion of 2 with a protective layer 25 made of synthetic resin, for example, the effective resistance value area (vertical length 0
．． 9an) W2 resistor 20 is obtained.
しかしながら、上述したような方法で形成される抵抗器
２０の端部電極部２４ａ、２４ｂは、その一部が保護層
２５で覆われ、かつ基板２１の両端部分で階段状となる
ため、端部寸法が個々の製品毎にばらつき他の回路部品
２回路パターンに対する良好な接続状態を得る上で支障
が生じるという問題がある。また、上述したような端部
電極部２４ａ、２４ｂの形状に起因してこの端部電極部
２４ａ、２４ｂと接合電極層２３ａ、２３ｂとの密着強
度の点でも不十分となる。However, the end electrode portions 24a and 24b of the resistor 20 formed by the method described above are partially covered with the protective layer 25 and have a stepped shape at both end portions of the substrate 21. There is a problem in that the dimensions vary from product to product, making it difficult to obtain a good connection between two circuit patterns of other circuit components. Further, due to the shape of the end electrode portions 24a, 24b as described above, the adhesion strength between the end electrode portions 24a, 24b and the bonding electrode layers 23a, 23b is insufficient.
ざらに、上述した端部電極部２４ａ、２４ｂを形成すべ
き抵抗体層２２及び接合電極層２３ａ。In general, the resistor layer 22 and the bonding electrode layer 23a on which the above-mentioned end electrode portions 24a and 24b are to be formed.
２３ｂに着目すると、抵抗体層２２の両側上面のある程
度の面積を占める部分に接合電極層２３ａ。Focusing on 23b, the bonding electrode layer 23a is formed in a portion occupying a certain area on both upper surfaces of the resistor layer 22.
２３ｂを形成したものであるから、有効抵抗値エリアＷ
２が小さくなりこの抵抗器２０の抵抗値の取得範囲が狭
くなるという問題がある。23b, the effective resistance value area W
2 becomes smaller, and there is a problem that the range in which the resistance value of this resistor 20 can be obtained becomes narrower.
（発明が解決しようとする課題）
上述したように、従来方法においては端部電極部の寸法
のばらつきが生じ、密着強度の点でも不十分であり、さ
らに有効素子エリアも小さいという問題を包含している
。(Problems to be Solved by the Invention) As described above, in the conventional method, the dimensions of the end electrode portion vary, the adhesion strength is insufficient, and the effective device area is also small. ing.
そこで本発明は、端部電極部の寸法の正確性を期するこ
とができ、充分な密着強度が得られ、ざらに、有効素子
エリアの拡大を図ることができる回路部品の電極製造方
法を提供することを目的とするものである。Therefore, the present invention provides a method for manufacturing electrodes for circuit components, which can ensure the accuracy of the dimensions of the end electrode portion, obtain sufficient adhesion strength, and roughly expand the effective element area. The purpose is to
［発明の構成］
（課題を解決するための手段）
本発明は、集合体処理により製造される回路部品の電極
製造方法であって、基板及びこの基板上に多数形成され
た回路素子のそれぞれの平坦な開放面に、この各回路素
子よりも狭面積を占める剥離層を対応配置に形成する工
程と、前記各回路素子を基板毎個別に分割する工程と、
分割された回路素子、基板及び剥離層の全周に下地電極
層を形成する工程と、前記剥離層及びこれに対応する領
域の下地電極層を除去する工程と、残余の下地電極層の
外周に端部電極部を形成する工程とを有するものである
。[Structure of the Invention] (Means for Solving the Problems) The present invention is a method for manufacturing electrodes of circuit components manufactured by assembly processing, which includes a method for manufacturing electrodes for a circuit component manufactured by assembly processing, and for each of a substrate and a large number of circuit elements formed on the substrate. forming release layers occupying a smaller area than each of the circuit elements in a corresponding arrangement on a flat open surface; and dividing each of the circuit elements into individual substrates;
A step of forming a base electrode layer around the entire circumference of the divided circuit element, substrate and release layer, a step of removing the release layer and the base electrode layer in a corresponding area, and a step of forming a base electrode layer on the outer periphery of the remaining base electrode layer. The method includes a step of forming an end electrode portion.
（作 用）
上述した構成からなる本発明方法は、まず各回路素子及
び基板のそれぞれの平坦な開放面に、各回路素子よりも
狭面積の剥離層を対応配置に形成し、次いで、各回路素
子を基板毎個別に分割した後、分割された回路素子、基
板及び剥離層の全周に下地電極層を形成し、さらに、剥
離層及びこれに対応する領域の下地電極層を除去し、回
路素子及び基板の外周に残存している下地電極層の外周
に端部電極部を形成するようにしたものである。(Function) The method of the present invention having the above-mentioned configuration first forms a peeling layer having a narrower area than each circuit element on each flat open surface of each circuit element and a substrate, and then forms a peeling layer in a corresponding arrangement on each circuit element and each flat open surface of the substrate. After dividing the device into individual substrates, a base electrode layer is formed all around the divided circuit elements, the substrate, and the peeling layer, and then the peeling layer and the base electrode layer in the corresponding area are removed, and the circuit An end electrode portion is formed on the outer periphery of the base electrode layer remaining on the outer periphery of the element and the substrate.
したがって、剥離層除去後の端部電極部を形成する領域
が下地電極層により明確に画されることになり、これに
より、端部電極部の寸法が全て正確となる。Therefore, the region where the end electrode portion is to be formed after the peeling layer is removed is clearly demarcated by the base electrode layer, and thereby the dimensions of the end electrode portion are all accurate.
また、電極部は下地電極層と端部電極部との二重構造と
なり、かつこれらが回路素子及び基板の外周の一部（端
部外周）を包囲する状態となるので、密着強度が大とな
ると共に、基板上の有効素子エリアも従来例に比べ拡大
することができる。In addition, the electrode part has a double structure of the base electrode layer and the end electrode part, and these parts surround a part of the outer periphery (the outer periphery of the end part) of the circuit element and the board, so the adhesion strength is high. At the same time, the effective element area on the substrate can also be expanded compared to the conventional example.
（実施例） 以下に本発明の実施例を詳細に説明する。(Example) Examples of the present invention will be described in detail below.
第１図は本実施例方法により下地電極層２ａ。FIG. 1 shows a base electrode layer 2a formed by the method of this embodiment.
２ｂ及び端部電極部３ａ、３ｂが形成された回路部品と
しての抵抗器１を示すものである。この抵抗器１は、ア
ルミナ製の基板４と、この基板４の平坦な上面に形成さ
れた回路素子としての抵抗素子５と、この基板４及び抵
抗素子５の両端部外周にそれぞれ形成された前記下地電
極１１２ａ、２ｂ及び端部電極部３ａ、３ｂとを有し、
その外形寸法が２．０７１．ＩＩＸ １．２５ ＭＸ
Ｏ１５調となっている。2b and end electrode portions 3a, 3b are shown as a circuit component. This resistor 1 includes a substrate 4 made of alumina, a resistance element 5 as a circuit element formed on the flat upper surface of this substrate 4, and a resistance element 5 formed on the outer periphery of both ends of this substrate 4 and resistance element 5, respectively. It has base electrodes 112a, 2b and end electrode parts 3a, 3b,
Its external dimensions are 2.071. IIX 1.25 MX
It is in the key of O15.
前記抵抗素子５は、基板４の上面における端部領域を除
く面に形成された抵抗体層６と、基板４の上面における
両端部領域において抵抗体層６に接合する状態に形成さ
れた接合電極層７ａ、７ｂと、この接合電極層７ａ、７
ｂの上面の一部及び抵抗体層６の上面を覆う状態に形成
された合成樹脂製の保護層８とを具備している。The resistor element 5 includes a resistor layer 6 formed on the upper surface of the substrate 4 excluding the end regions, and a bonding electrode formed to be connected to the resistor layer 6 at both end regions on the upper surface of the substrate 4. layers 7a, 7b and the bonding electrode layers 7a, 7
A protective layer 8 made of synthetic resin is formed to cover a portion of the upper surface of b and the upper surface of the resistor layer 6.
そして、前記抵抗体層６が接合電極層７ａ。The resistor layer 6 is a bonding electrode layer 7a.
７ｂで覆われない領域を、有効抵抗値エリア（縦方向の
長さ１．４調程度＞Ｗｌとして機能させるようになって
いる。The area not covered by 7b is made to function as an effective resistance value area (vertical length approximately 1.4 scale>Wl).
次に、前記抵抗器１の製造工程について第２図乃至第６
図を参照して説明する。Next, the manufacturing process of the resistor 1 will be explained in FIGS. 2 to 6.
This will be explained with reference to the figures.
まず、第２図に示すように基板４上に集合体処理により
４個の抵抗素子５を一定間隔を有するように形成した抵
抗素子集合体１０を用意する。First, as shown in FIG. 2, a resistive element assembly 10 is prepared in which four resistive elements 5 are formed at regular intervals on a substrate 4 by an assembly process.
そして、各抵抗素子５を構成する保護層８の上面に、第
３図に示すように前記有効抵抗値エリアＷ１よりも若干
狭面積を占めるように、かつ所定の厚さとなるように４
個の上面剥離層９ａを形成すると共に、基板４の下面側
にも前記各上面剥離層９ａに対応する位置に４個の下面
剥離層９ｂを形成する。この下面剥離層９ｂは、上面剥
離層９ａと同大で、かつ等厚に形成する。尚、上面。Then, as shown in FIG. 3, on the upper surface of the protective layer 8 constituting each resistance element 5, a layer 4 is formed so as to occupy an area slightly smaller than the effective resistance value area W1 and to have a predetermined thickness.
Four upper release layers 9a are formed, and four lower release layers 9b are also formed on the lower surface of the substrate 4 at positions corresponding to the upper release layers 9a. The lower release layer 9b is formed to have the same size and thickness as the upper release layer 9a. Furthermore, the top surface.
下面剥離層９ａ、９ｂは幅１．２７７１ｆｆｉ、厚さ約
１０μｍでおる。The lower peeling layers 9a and 9b have a width of 1.2771ffi and a thickness of about 10 μm.
次に、上面及び下面剥離層９ａ・、９ｂを形成した抵抗
素子集合体１０を、第４図に示すように基板４の切断端
面と接合電極層７ｂ（又は７ａ）とが垂直方向に合致す
るように切断処理し個別に分割してスティック状とする
。Next, the resistance element assembly 10 with the upper and lower peeling layers 9a and 9b formed thereon is placed so that the cut end surface of the substrate 4 and the bonding electrode layer 7b (or 7a) match in the vertical direction, as shown in FIG. Cut it into individual pieces and make them into sticks.
さらに、分割された基板４及び抵抗素子５に対して、こ
れらの外周全体に第５図に示すように導電性の有る金属
（ＣＬ、ｌ、Ｃｕ合金等）製の下地電極部２をＣＩＪ−
Ｎｉ合金を用いたスパッタリング等の方法で約２０００
Ａの厚さに形成する。Further, as shown in FIG. 5, a base electrode portion 2 made of a conductive metal (CL, l, Cu alloy, etc.) is attached to the entire outer periphery of the divided substrate 4 and resistance element 5 by CIJ-
Approximately 2,000 yen by a method such as sputtering using Ni alloy
Form to thickness A.
尚、下地電極層２ａ、 ２ｂは必要に応じてＣｒ又はＮ
ｉＣｒを１００乃至５００Ａの厚さに形成した後、ＣＬ
Ｊを約１５００への厚さで積層し、ざらにＣｕ−Ｎｉを
約５００への厚さで積層する方法等でもよい。Note that the base electrode layers 2a and 2b may be made of Cr or N as required.
After forming iCr to a thickness of 100 to 500A, CL
A method may also be used in which J is laminated to a thickness of approximately 1,500 mm, and Cu-Ni is laminated to a thickness of approximately 500 mm.
この後、キシレン、活性ソーダの稀薄水溶液。After this, xylene, a dilute aqueous solution of activated soda.
レジスト専用剥離剤等の剥離剤を用いて、前記上面及び
下面剥離層９ａ、９ｂ及びこれらに接触してる領域の下
地電極部２の一部を剥離し、第６図に示すように前記基
板４の端部領域、接合電極層７ａ、７ｂの露出領域及び
保護層８の端部領域を包囲し、かつ上下対称配置の下地
電極層２ａ、２ｂを形成する。Using a stripping agent such as a resist stripping agent, the upper and lower stripping layers 9a and 9b and a portion of the underlying electrode section 2 in the area in contact with these layers are stripped off, and the substrate 4 is removed as shown in FIG. , the exposed areas of the bonding electrode layers 7a and 7b, and the end areas of the protective layer 8, and are arranged vertically symmetrically to form underlying electrode layers 2a and 2b.
さらに、下地電極＠２ａ、２ｂの外周全域に湿式バレル
メッキの方法により、ｃｕ、Ｎｒ、Ａｇ。Furthermore, Cu, Nr, and Ag are deposited on the entire outer periphery of the base electrodes @2a and 2b by wet barrel plating.
Ａｕ、Ｓｎ等の導電性金属製の端部電極部３ａ。An end electrode portion 3a made of a conductive metal such as Au or Sn.
３ｂを形成することにより、第１図に示す抵抗器１を製
造する。尚、端部電極部３ａ、３ｂとしては、Ｎｉを約
２μｍの厚さにメツキした後、３ｎを約３μｍの厚さに
積層したものが好適である。3b, the resistor 1 shown in FIG. 1 is manufactured. The end electrode portions 3a and 3b are preferably formed by plating Ni to a thickness of approximately 2 μm and then laminating 3N to a thickness of approximately 3 μm.
上述した工程からなる本実施例方法によれば、上面及び
下面剥離層８ａ、８ｂの剥離工程を経て形成される下地
電極層２ａ、２ｂが、端部電極部３ａ、３ｂを形成する
際の寸法ガイドとして機能し、これにより端部電極部３
ａ、３ｂの寸法が画一化されその正確性を期することが
できる。According to the method of this embodiment, which includes the steps described above, the base electrode layers 2a and 2b formed through the peeling process of the upper and lower peeling layers 8a and 8b have the same dimensions as when forming the end electrode parts 3a and 3b. It functions as a guide, and thereby the end electrode part 3
The dimensions of a and 3b are standardized and their accuracy can be ensured.
また、下地電極層２ａ、２ｂをスパッタリングの方法に
より形成し、端部電極部３ａ、３ｂを湿式バレルメッキ
の方法により形成するものであるから、下地電極層２ａ
、２ｂと接合電極層７ａ。Furthermore, since the base electrode layers 2a and 2b are formed by sputtering, and the end electrode portions 3a and 3b are formed by wet barrel plating, the base electrode layers 2a and 2b are formed by a wet barrel plating method.
, 2b and the bonding electrode layer 7a.
７ｂとの密着強度が大きく、また、下地電極層２ａ、
２ｂに対する端部電極部３ａ、３ｂのメツキ時の付き回
りも良好なものとすることができる。The adhesion strength with the base electrode layer 2a is large, and the base electrode layer 2a,
The coverage of the end electrode portions 3a, 3b with respect to the electrode portion 2b during plating can also be made good.
ざらに、上述したような抵抗器１の場合には、従来例の
場合と異なり保護層８の端部領域まで下地電極層２ａ、
２ｂ及び端部電極部３ａ、３ｂを覆うことができるので
、接合電極層７ａ、７ｂを従来例の場合よりも基板４上
のより端部側に形成でき、この結果、有効抵抗値エリア
Ｗ１を縦方向の長さ約１．４Ｍとすることができ、従来
例の有効抵抗値エリアＷ２より大きくなり、この抵抗器
１の抵抗値の取得範囲の拡大が図れる。Roughly speaking, in the case of the resistor 1 as described above, unlike the case of the conventional example, the base electrode layer 2a,
2b and the end electrode portions 3a, 3b, the bonding electrode layers 7a, 7b can be formed closer to the end portions of the substrate 4 than in the conventional example, and as a result, the effective resistance value area W1 can be The length in the vertical direction can be approximately 1.4M, which is larger than the effective resistance value area W2 of the conventional example, and the range in which the resistance value of this resistor 1 can be obtained can be expanded.
本発明は上述した実施例に限定されるものではなく、そ
の要旨の範囲内で種々の変形が可能である。The present invention is not limited to the embodiments described above, and various modifications can be made within the scope of the invention.
例えば、上述した実施例では回路素子として抵抗素子を
用いた場合について説明したが、これに限らず、インダ
クタンス素子、コンデンサ、トランス等各種のチップ部
品を製造する場合にも適用可能である。For example, in the above-described embodiments, a case was explained in which a resistance element was used as a circuit element, but the present invention is not limited to this, and can be applied to the manufacture of various chip components such as an inductance element, a capacitor, and a transformer.
［発明の効果］
以上詳述した本発明によれば、電極部の寸法の正確性を
記すことができ、電極部の密着強度も大きく、しかも、
有効素子エリアの拡大をも図ることができる回路部品の
電極製造方法を提供することができる。[Effects of the Invention] According to the present invention described in detail above, it is possible to accurately mark the dimensions of the electrode part, the adhesion strength of the electrode part is high, and,
It is possible to provide a method for manufacturing electrodes for circuit components that can also expand the effective element area.
第１図は本発明の実施例方法を適用して得られる回路部
品としての抵抗器を示す断面図、第２図乃至第６図はれ
それぞれ本発明の実施例方法による製造工程を示す断面
図、第７図は従来方法で得られる抵抗器を示す断面図で
ある。
１・・・回路部品の一例としての抵抗器、２ａ、２ｂ・
・・下地電極層、
３ａ、３ｂ・・・端部電極部、４・・・基板、５・・・
回路素子の一例としての抵抗素子。FIG. 1 is a sectional view showing a resistor as a circuit component obtained by applying an embodiment method of the present invention, and FIGS. 2 to 6 are sectional views each showing a manufacturing process by an embodiment method of the present invention. , FIG. 7 is a sectional view showing a resistor obtained by a conventional method. 1... Resistors as an example of circuit components, 2a, 2b.
...Base electrode layer, 3a, 3b... End electrode part, 4... Substrate, 5...
A resistance element as an example of a circuit element.
Claims (1)
あって、基板及びこの基板上に多数形成された回路素子
のそれぞれの平坦な開放面に、この各回路素子よりも狭
面積を占める剥離層を対応配置に形成する工程と、前記
各回路素子を基板毎個別に分割する工程と、分割された
回路素子、基板及び剥離層の全周に下地電極層を形成す
る工程と、前記剥離層及びこれに対応する領域の下地電
極層を除去する工程と、残余の下地電極層の外周に端部
電極部を形成する工程とを有することを特徴とする回路
部品の電極製造方法。A method for manufacturing electrodes for circuit components manufactured by assembly processing, wherein a release layer is provided on each flat open surface of a substrate and a large number of circuit elements formed on the substrate, the peeling layer occupying an area smaller than each of the circuit elements. a step of forming the circuit elements in a corresponding arrangement, a step of dividing each circuit element into individual substrates, a step of forming a base electrode layer all around the divided circuit elements, the substrate and the release layer; A method for manufacturing an electrode for a circuit component, comprising the steps of: removing a base electrode layer in a corresponding region; and forming an end electrode portion on the outer periphery of the remaining base electrode layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63014310A JP2668375B2 (en) | 1988-01-25 | 1988-01-25 | Circuit component electrode manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63014310A JP2668375B2 (en) | 1988-01-25 | 1988-01-25 | Circuit component electrode manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01189102A true JPH01189102A (en) | 1989-07-28 |
| JP2668375B2 JP2668375B2 (en) | 1997-10-27 |
Family
ID=11857524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63014310A Expired - Lifetime JP2668375B2 (en) | 1988-01-25 | 1988-01-25 | Circuit component electrode manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2668375B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03165501A (en) * | 1989-10-20 | 1991-07-17 | Sfernice Soc Fr Des Electro Resistance | Chip type electric resistor and its manufacture |
| KR100495130B1 (en) * | 2002-11-19 | 2005-06-14 | 엘에스전선 주식회사 | Method of manufacturing surface mountable electrical device for printed circuit board using heat welding and surface mountable electrical device made by the method |
| JP2009277834A (en) * | 2008-05-14 | 2009-11-26 | Taiyosha Electric Co Ltd | Method of manufacturing chip resistor, and chip resistor |
| WO2013137338A1 (en) * | 2012-03-16 | 2013-09-19 | コーア株式会社 | Chip resistor for incorporation into substrate, and method for producing same |
| JP2019096834A (en) * | 2017-11-27 | 2019-06-20 | パナソニックＩｐマネジメント株式会社 | Resistor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6314402A (en) * | 1986-07-04 | 1988-01-21 | 多摩電気工業株式会社 | Manufacture of chip resistor |
-
1988
- 1988-01-25 JP JP63014310A patent/JP2668375B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6314402A (en) * | 1986-07-04 | 1988-01-21 | 多摩電気工業株式会社 | Manufacture of chip resistor |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03165501A (en) * | 1989-10-20 | 1991-07-17 | Sfernice Soc Fr Des Electro Resistance | Chip type electric resistor and its manufacture |
| KR100495130B1 (en) * | 2002-11-19 | 2005-06-14 | 엘에스전선 주식회사 | Method of manufacturing surface mountable electrical device for printed circuit board using heat welding and surface mountable electrical device made by the method |
| JP2009277834A (en) * | 2008-05-14 | 2009-11-26 | Taiyosha Electric Co Ltd | Method of manufacturing chip resistor, and chip resistor |
| WO2013137338A1 (en) * | 2012-03-16 | 2013-09-19 | コーア株式会社 | Chip resistor for incorporation into substrate, and method for producing same |
| CN104160459A (en) * | 2012-03-16 | 2014-11-19 | 兴亚株式会社 | Chip resistor for incorporation into substrate, and method for producing same |
| JPWO2013137338A1 (en) * | 2012-03-16 | 2015-08-03 | コーア株式会社 | Chip resistor for built-in substrate and manufacturing method thereof |
| JP2019096834A (en) * | 2017-11-27 | 2019-06-20 | パナソニックＩｐマネジメント株式会社 | Resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2668375B2 (en) | 1997-10-27 |
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