JPH01110761A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01110761A JPH01110761A JP62268462A JP26846287A JPH01110761A JP H01110761 A JPH01110761 A JP H01110761A JP 62268462 A JP62268462 A JP 62268462A JP 26846287 A JP26846287 A JP 26846287A JP H01110761 A JPH01110761 A JP H01110761A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- polycrystalline silicon
- gate electrode
- gate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 29
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 48
- 239000010410 layer Substances 0.000 description 42
- 238000005468 ion implantation Methods 0.000 description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000001204 N-oxides Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
絶縁膜の厚さの異なる複数のトランジス、りを有する半
導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having a plurality of transistors having insulating films of different thicknesses.
従来、この種の複数のトランジスタを有する半導体装置
を製造するためには、通常の電源電圧で動作するトラン
ジスタ、たとえば電源電圧５Ｖで動作するトランジスタ
に加えて、電源電圧が５Ｖよシ高い電圧で動作するトラ
ンジスタを同一基板上に形成するために、膜厚の異なる
ゲート絶縁膜を形成することが必要である。Conventionally, in order to manufacture a semiconductor device having multiple transistors of this kind, in addition to transistors that operate at a normal power supply voltage, such as transistors that operate at a power supply voltage of 5V, it is necessary to create a transistor that operates at a power supply voltage higher than 5V. In order to form transistors on the same substrate, it is necessary to form gate insulating films with different thicknesses.
従来の技術による半導体装置の製造方法としては、２種
類のゲート絶縁膜の膜厚をｄｌ ＋ ｄｚ （ｄｌ＞ｄ
２ ）とするとき、第１のゲート絶縁膜形成工程でｃｔ
、−ｃｔ。In the conventional method of manufacturing a semiconductor device, the film thicknesses of two types of gate insulating films are dl + dz (dl>d
2), ct in the first gate insulating film forming step
,-ct.
の厚さの絶縁膜を形成し、その後、通常の電源電圧で動
作するトランジスタ形成領域の絶縁膜を選択的にエツチ
ングして除去し、第２のゲート絶縁膜形成工程でｄ２の
厚さの絶縁膜を形成するという二度の形成工程によシ、
半導体装置のゲート絶縁膜を形成していた。An insulating film with a thickness of d2 is formed, and then the insulating film in the transistor formation area that operates at a normal power supply voltage is selectively etched and removed, and an insulating film with a thickness of d2 is formed in a second gate insulating film forming step. Through the two-step process of forming a film,
It was used to form gate insulating films for semiconductor devices.
上述した従来の半導体装置の製造方法は、ゲート絶１Ｆ
ｆｆの厚いトランジスタの絶縁膜を二度のゲート絶縁膜
形成工程により形成していたために、ゲート絶縁膜の厚
さのばらつきが犬きく、また、−度目のゲート絶縁膜形
成工程と二度目のゲート絶縁膜形成工程との間に付着す
るごみ等によるゲート絶縁膜の耐圧の劣化が起こりやす
いという欠点を有していた。The conventional semiconductor device manufacturing method described above is
Since the insulating film of the transistor with a thick ff was formed by two gate insulating film forming processes, there was considerable variation in the thickness of the gate insulating film. This method has a disadvantage in that the withstand voltage of the gate insulating film is likely to deteriorate due to dust and the like adhering during the process of forming the insulating film.
本発明の目的は、ゲート絶縁膜の厚さのばらつきが少（
、かつゲート絶縁膜の欠陥による耐圧の劣化の少ない半
導体装置の製造方法を提供することにある。An object of the present invention is to reduce variations in the thickness of the gate insulating film (
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which the breakdown voltage is less degraded due to defects in the gate insulating film.
本発明の半導体装置の製造方法は、半導体基板上にフィ
ールド絶縁膜と膜厚の厚い第１絶縁膜とを選択的に形成
する工程と、全面に第１多結晶シリコン層を形成したの
ちバターニングし前記第１絶縁膜上に第１ゲート電極を
形成する工程と、前記第１ゲート電極下を除き前記第１
絶縁膜を除去したのち全面に膜厚の薄い第２絶縁膜を形
成する工程と、全面に第２多結晶シリコン層を形成した
のちバターニングし前記第２絶縁膜上に第２ゲート電極
を形成する工程とを含んで構成される。The method of manufacturing a semiconductor device according to the present invention includes a step of selectively forming a field insulating film and a thick first insulating film on a semiconductor substrate, and a step of forming a first polycrystalline silicon layer on the entire surface, and then patterning. a step of forming a first gate electrode on the first insulating film; and a step of forming a first gate electrode on the first insulating film;
After removing the insulating film, a second insulating film with a thin film thickness is formed on the entire surface, and after forming a second polycrystalline silicon layer on the entire surface, buttering is performed and a second gate electrode is formed on the second insulating film. The process includes the steps of:
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｈ）は本発明の一実施例を説明するだ
めの工程項に示した半導体チップの断面図である。FIGS. 1A to 1H are cross-sectional views of a semiconductor chip shown in the process section for explaining an embodiment of the present invention.
まず第１図（ａ）に示すように、半導体基板１０１にイ
オン注入法によ、９Ｎ型及びＰ型不純物を導入し、Ｎウ
ェル１０２及びＰウェル１０３を形成する。続いて選択
酸化法によシ厚さ約１μｍのフィールド酸化膜１０４と
厚さ１００ＯＡの第１絶縁膜１０５とを形成する。First, as shown in FIG. 1(a), 9N type and P type impurities are introduced into a semiconductor substrate 101 by ion implantation to form an N well 102 and a P well 103. Subsequently, a field oxide film 104 with a thickness of about 1 μm and a first insulating film 105 with a thickness of 100 OA are formed by selective oxidation.
次にｉｉ図（ｂ）に示すように、全面に厚さ５０００Ａ
のｍｌ多結晶シリコ７層１０６を形成したのちパターニ
ングし、ｉｉ図（Ｃ）に示すように、第１絶縁膜１０５
上に第１ゲート電極１０６Ａ、１０６Ｂを形成する。Next, as shown in Figure ii (b), the entire surface has a thickness of 5000A.
After forming 7 ml polycrystalline silicon layers 106, patterning is performed to form the first insulating film 105 as shown in FIG. ii (C).
First gate electrodes 106A and 106B are formed thereon.
次に第１図（ｄ）に示すように、第１ゲート電極１０６
Ａ、１０６Ｂ下を除き第１絶縁膜１０５を除去したのち
、熱酸化法により全面に５ｉ０２からなる厚さ約４０Ｏ
Ａの第２絶縁膜１０７を形成する。Next, as shown in FIG. 1(d), the first gate electrode 106
A, after removing the first insulating film 105 except under 106B, a layer of 5i02 with a thickness of approximately 400 nm is formed on the entire surface by thermal oxidation.
A second insulating film 107 is formed.
次にｍ１図（ｅ）に示すように、全面に厚さ約５００Ｏ
Ａの第２多結晶シリコン層１０８を形成したのちパター
ニングし、第１図（ｆｌに示すように、第２絶縁膜１０
７上に第２ゲート電極１０８Ａ、１０８Ｂを形成する。Next, as shown in Figure m1 (e), the entire surface is coated with a thickness of about 5000
After forming the second polycrystalline silicon layer 108 of A, patterning is performed to form the second insulating film 108 as shown in FIG.
Second gate electrodes 108A and 108B are formed on 7.
次で熱酸化法によシｆｇ２ゲート電極１０８Ａ、１０８
Ｂ表面に絶縁膜１１３を形成する。Next, the fg2 gate electrodes 108A, 108 are processed by thermal oxidation method.
An insulating film 113 is formed on the B surface.
以下第１図（ｇ）に示すように、常法に従いＰチャネル
トランジスタ（Ｔｒ ）及びＮチャネルトランジスタ（
Ｔｒ ）のソース・ドレインを形成するための不純物拡
散層を形成する。As shown in FIG. 1(g) below, a P-channel transistor (Tr) and an N-channel transistor (Tr) are constructed according to the conventional method.
An impurity diffusion layer is formed to form the source and drain of Tr.
まず、Ｎ−拡酸層１１２が形成される所のみ残して他の
部分をマスク材でおおい低ドーズのリンのイオン注入を
行う。続いてＮ＋拡散ｉ １０９．１０９Ａが形成場れ
るところを除いてマスク材でおおい、高１−”−ズのヒ
素のイオン注入を行う。この時Ｎ”拡散層１０９Ａが形
成されるところは、第１ゲート電極１０６ Ｉ３ （１
１！ｌは關ドーズのヒ素のイオン注入が行なわれないよ
うにマスク材でおおう。First, a low-dose phosphorus ion implantation is performed by covering only the area where the N-oxide expansion layer 112 is to be formed and covering the other areas with a mask material. Subsequently, the area where the N+ diffusion layer 109.109A will be formed is covered with a mask material, and arsenic ion implantation with a high 1-'' is carried out.At this time, the area where the N'' diffusion layer 109A is to be formed is 1 gate electrode 106 I3 (1
1! 1 is covered with a mask material to prevent arsenic ion implantation at a high dose.
次に、ｒ拡散）＠ Ｉ ｌ １が形成されるところのみ
残して、マスク材でおおい、低ドーズのボロンのイオン
注入を行う。次で、不純物活性化のため熱処理を行う。Next, only the region where r diffusion)@I l 1 is formed is covered with a mask material, and low-dose boron ions are implanted. Next, heat treatment is performed to activate impurities.
続いて、Ｐ＋拡散層１１０． ｌｌ０Ａを形成する部分
を残してマスク材でおおい、高ドーズのボロンのイオン
注入を行う。この時、Ｐ＋拡散Ｎ１１０Ａが形成される
ところは、第１ゲート電極１０６ＡｉｌＱには、イオン
注入されないようにマスク材でおおう。Subsequently, a P+ diffusion layer 110. The portion where ll0A is to be formed is covered with a mask material, and high-dose boron ions are implanted. At this time, the area where the P+ diffusion N110A is formed is covered with a mask material to prevent ion implantation into the first gate electrode 106AilQ.
次に詔１図（１１）に示すように、各トランジスタのソ
ース・ドレイン形成後、リンをドープしｆｃ層間絶縁膜
１１３を堆積し、熱処理により平担化し、さらにコンタ
クト孔を開孔し１．金属配線であるアルミニウム１１４
を形成する。Ｐ＋拡散層１１０Ａ。Next, as shown in Figure 1 (11) of Edict 1, after forming the source and drain of each transistor, phosphorus-doped fc interlayer insulating film 113 is deposited, flattened by heat treatment, and contact holes are formed.1. Aluminum 114 metal wiring
form. P+ diffusion layer 110A.
Ｐ−拡散層１１１の二重拡散構造は共に不純物原子はボ
ロンであるが、Ｐ＋拡散層形成前に一度熱処理を行いＰ
−拡散層を深めに拡散することＫよシ実現可能であシ、
またＮ＋拡散層１０９Ａ、Ｎ−拡散層１１２の二重拡散
構造は、不純物原子がヒ素とリンであるため両者の拡散
係数の差によシ実現可能である。また第１ゲート電極１
０６Ａ及び第２ゲート電極１０８ＢはＰ＋型に、そして
第１ゲート電極１０６Ｂ及び第２ゲート電極１０８Ａは
Ｎ”Ｗとなる。In the double diffusion structure of the P- diffusion layer 111, the impurity atoms are boron, but heat treatment is performed once before forming the P+ diffusion layer.
- It is possible to deeply diffuse the diffusion layer,
Further, since the impurity atoms are arsenic and phosphorous, the double diffusion structure of the N+ diffusion layer 109A and the N- diffusion layer 112 can be realized by the difference in the diffusion coefficients of the two. Also, the first gate electrode 1
06A and the second gate electrode 108B are of P+ type, and the first gate electrode 106B and the second gate electrode 108A are of N''W type.
上記の製造工程によシ、ゲート絶縁膜の厚さが１００Ｏ
Ａと４００Ａのトランジスタを製造することができる。Due to the above manufacturing process, the thickness of the gate insulating film is 100O
A and 400A transistors can be manufactured.
上記の実施例では、一部の拡散層をＮ−、Ｎ”！。In the above embodiment, some of the diffusion layers are N-, N''!.
Ｐ−、Ｐ＋型の二重構造にしているが、これはトランジ
スタに印加される電圧によって決まるものであシ、特に
、上記実施例は通常用いられている５■電源電圧に加え
て、２０ｖ以上の電圧で動作可能なトランジスタを製造
する例を示している。Although it has a P- and P+ type double structure, this is determined by the voltage applied to the transistor.In particular, in the above embodiment, in addition to the normally used 5■ power supply voltage, it is determined by the voltage applied to the transistor. An example of manufacturing a transistor that can operate at a voltage of
このように本実施例によれば、厚さの異なるゲート絶縁
膜を別の工程でしかも一度の工程で形成できるため、ゲ
ート絶縁膜の厚さのばらつきが少くなシ、かつごみ等の
付着によるゲート絶縁膜の欠陥、が防止される。As described above, according to this embodiment, gate insulating films with different thicknesses can be formed in separate processes and in a single process, so there is little variation in the thickness of the gate insulating films, and there is no problem with the adhesion of dust, etc. Defects in the gate insulating film are prevented.
上記の実施例においては、第１多結晶シリコン層１０６
及び第２多結晶シリコン層１０８への不純物の導入は、
Ｗ拡散層１０９又はＰ＋拡散層１１０を形成するときの
イオン注入による不純物の導入と同時に行われている。In the above embodiment, the first polycrystalline silicon layer 106
And the introduction of impurities into the second polycrystalline silicon layer 108 is as follows:
This is done simultaneously with the introduction of impurities by ion implantation when forming the W diffusion layer 109 or the P+ diffusion layer 110.
第１ゲート電極１０６ Ａを有するトランジスタを第１
Ｐチヤネルトランジスタ、第２ゲート電極１０８Ａを有
するトランジスタを第１Ｎチヤネルトランジスタ、第１
ゲート電極１０６Ｂを有するトランジスタを第２Ｎチヤ
ネルトランジスタ、第２ゲート電極１０８Ｂを有するト
ランジスタを第２Ｐチヤネルトランジスタとすると、上
記の実施例においては第１及び第２Ｐチヤネルトランジ
スタのゲート電極である多結晶シリコンの導電型はＰ型
となシ、第１及び第２Ｎチヤネルトランジスタのゲー）
［極である多結晶シリコンの導ｇ、世はＮ型である。こ
の実施例のように多結晶シリコンへの不純物導入をＮ＋
拡散層、Ｐ＋型拡散層形成のためのイオン注入で行う場
合、多結晶シリコンのシート抵抗は１０００〜１５００
程度となる。A transistor having a first gate electrode 106A is
The P-channel transistor and the transistor having the second gate electrode 108A are referred to as the first N-channel transistor and the first
Assuming that the transistor having the gate electrode 106B is a second N-channel transistor and the transistor having the second gate electrode 108B is a second P-channel transistor, in the above embodiment, the gate electrodes of the first and second P-channel transistors are made of polycrystalline silicon. The conductivity type is P type (the first and second N-channel transistors are connected)
[The polarity of polycrystalline silicon is N type. As in this example, the introduction of impurities into polycrystalline silicon is
When performing ion implantation to form a diffusion layer or P+ type diffusion layer, the sheet resistance of polycrystalline silicon is 1000 to 1500.
It will be about.
一方、第１多結晶シリコン層１０６堆積後、パターニン
グし廟１ゲート電極１０６Ａ、１０６Ｂを形成する前に
、第１多結晶シリコン層１０６に熱拡散によりリンを拡
散させ、同様に第２多結晶シリコンＰ４１０８堆積後、
パターニングに第２ゲート質極１０８Ａ、１０８Ｂを形
成する前例熱拡散法によりリンを拡散させることによシ
、第１．第２多結晶シリコ：）層へ不純物を導入するこ
とによ、す、低シート抵抗を有するゲート電極を形成す
ることができ、配線による遅延を小さくすることに有用
である。リンを拡散した多結晶シリコン層のシート抵抗
は、３００〜２０Ω程度と前記の値に対して小さい値に
なっている。このとき、第１，２Ｐチヤネルトランジス
タ及び第ｔ、２Ｎチャネルトランジスタのゲート電極で
ある多結晶シリコンの導電型は共にＮ型となる。On the other hand, after depositing the first polycrystalline silicon layer 106 and before patterning and forming the first gate electrodes 106A and 106B, phosphorus is diffused into the first polycrystalline silicon layer 106 by thermal diffusion, and the second polycrystalline silicon layer is similarly deposited. After P4108 deposition,
In the patterning process, the first gate material electrodes 108A and 108B are formed by diffusing phosphorus using a thermal diffusion method. By introducing impurities into the second polycrystalline silicon layer, it is possible to form a gate electrode with low sheet resistance, which is useful for reducing delays due to wiring. The sheet resistance of the polycrystalline silicon layer in which phosphorus is diffused is about 300 to 20 Ω, which is smaller than the above value. At this time, the conductivity types of the polycrystalline silicon serving as the gate electrodes of the first and second P channel transistors and the t and 2N channel transistors are both N type.
また、第１多結晶シリコン層１０６堆積後、不純物とし
て熱拡散によ）リンを拡散し、第１ゲート電極１０６Ａ
、１０６Ｂを形成し、第２多結晶シリコン層１０８へは
前実施例と同様に、ソース領域。Further, after depositing the first polycrystalline silicon layer 106, phosphorus is diffused as an impurity (by thermal diffusion) to form the first gate electrode 106A.
, 106B are formed, and a source region is formed on the second polycrystalline silicon layer 108 as in the previous embodiment.
ドレイン領域形成のためのイオン注入によって行うこと
も可能であシ、このとき、第１Ｐチヤネルトランジスタ
の第１ゲート電極１０６Ａの導電型はＮ型、第２Ｐチヤ
ネルトランジスタの第２ゲート電極１０８Ｂの導電型は
Ｐ型、第１，２Ｎチヤネルトランジスタのゲート電極の
導電型は共にＮ型である。第１多結晶シリコン層１０６
のシート抵抗は第２多結晶シリコン層１０８に比べて十
分に小さいので、低抵抗の配線として利用でき、第１Ｐ
チヤネルトランジスタの第１ゲート電極の導電型はＮ型
であシ、ゲート酸化膜は厚く、第２Ｐチヤネルトランジ
スタの第２ゲート電極の導電型はＰ型であシ、ゲート酸
化膜は薄いので、第１．２Ｐチヤネルトランジスタは同
一導電型のトランジスタで、チャネル部分の表面濃度が
同一でありながらしきい値電圧が異なる。このように、
同一導電型であυながらしきい値電圧を変えるための追
加工程なしに、異なるしきい値のトランジスタが得られ
るために回路設計の自由度が増すことになる。It is also possible to perform ion implantation for forming the drain region. In this case, the conductivity type of the first gate electrode 106A of the first P-channel transistor is N type, and the conductivity type of the second gate electrode 108B of the second P-channel transistor. is P-type, and the conductivity types of the gate electrodes of the first and second N-channel transistors are both N-type. First polycrystalline silicon layer 106
Since the sheet resistance of
The conductivity type of the first gate electrode of the channel transistor is N type and the gate oxide film is thick, and the conductivity type of the second gate electrode of the second P channel transistor is P type and the gate oxide film is thin. The 1.2P channel transistors are transistors of the same conductivity type, and have the same surface concentration in the channel portion but different threshold voltages. in this way,
Since transistors of the same conductivity type but with different threshold voltages can be obtained without an additional step to change the threshold voltage, the degree of freedom in circuit design increases.
更に酊１多結晶シリコン層１０６には、ン＝ス・ドレイ
ン領域形成のためのイオン注入により不純物導入を行い
、第２多結晶シリコンＡｊ１１０ Ｂ堆積後、熱拡散に
よシネ鈍物としてリンを拡散し、第２多結晶シリコン層
１０８を形成するということも可能であり、このとき、
第１．２Ｎチャネルトランジスタのゲート電極である多
結晶シリコンの導電型はＮ型であシ、第１Ｐチヤネルト
ランジスタのゲート電極である多結晶シリコンの導電型
はＦＷであり、第２Ｐチヤネルトランジスタのゲート電
極である多結晶シリコンの導電型はＮ型となる。第２多
結晶シリコン層１０８は不純物としてリンを拡散してい
るので低抵抗の配線として利用でき、第１Ｆチヤネルト
ランジスタはゲート酸化膜は厚くゲート電極の導電型は
Ｐ型であシ、第２Ｐチヤネルトランジスタはゲート酸化
膜は薄（ゲート電極の導電型はＮ型となる。前記同様に
、同一導電型でありながら、新たに工程を追加すること
なく、シきい値の異なるトランジスタを得られるために
回路設計の自由度が増す。Further, impurities are introduced into the first polycrystalline silicon layer 106 by ion implantation to form a source and drain region, and after the second polycrystalline silicon layer 106 is deposited, phosphorus is diffused as a cine duller by thermal diffusion. However, it is also possible to form the second polycrystalline silicon layer 108, and in this case,
The conductivity type of the polycrystalline silicon that is the gate electrode of the 1.2nd N-channel transistor is N type, the conductivity type of the polycrystalline silicon that is the gate electrode of the 1st P-channel transistor is FW, and the conductivity type of the polycrystalline silicon that is the gate electrode of the 2nd P-channel transistor is FW. The conductivity type of the polycrystalline silicon that is the electrode is N type. Since the second polycrystalline silicon layer 108 has phosphorus diffused as an impurity, it can be used as a low-resistance wiring.The first F channel transistor has a thick gate oxide film and the conductivity type of the gate electrode is P type, The transistor has a thin gate oxide film (the conductivity type of the gate electrode is N type).Similarly to the above, it is possible to obtain transistors of the same conductivity type but with different threshold values without adding a new process. Increased freedom in circuit design.
これらの例では、ＰチャネルトランジスタのみＫしきい
値の異なるトランジスタが得られることを説明したが、
第１又は第２多結晶シリコン層の少なくとも一方に不純
物としてリンを導入しない場合には、第２図に示すよう
に、Ｎ型及びＰ型多結晶シリコン２０８Ａ、２０８Ｂで
ゲート電極を構成することにより、Ｎチャネルトランジ
スタにも、しきい値の異なるトランジスタを形成するこ
とが可能である。In these examples, it has been explained that only P channel transistors can have different K thresholds.
If phosphorus is not introduced as an impurity into at least one of the first or second polycrystalline silicon layers, as shown in FIG. , N-channel transistors can also be formed with different threshold voltages.
すなわち、第２図に示すように、Ｐウェル１０３上に形
成されたＮチャネルトランジスタのゲート電極を構成す
る多結晶シリコンへの不純物の導入を多結晶シリコンの
中心部を除いてソース・ドレイン領域形成のためのＮ型
の不純物であるヒ素をイオン注入して行い、次で中心部
のみにＰ型の不純物であるほう素をイオン注入すること
により、ゲー）［極の導電型をＮ型、Ｐ型両方の導電型
とすることができる。これにより、ゲート電極の一部分
の仕事関数が異なるためにチャネル部分の表面濃度が同
一であっても、トランジスタのしきい値電圧が異なった
ものになる。That is, as shown in FIG. 2, impurities are introduced into the polycrystalline silicon constituting the gate electrode of the N-channel transistor formed on the P-well 103 except for the center of the polycrystalline silicon to form source and drain regions. By ion-implanting arsenic, which is an N-type impurity, and then ion-implanting boron, which is a P-type impurity, only in the center, Both conductivity types can be used. As a result, the threshold voltages of the transistors differ even if the surface concentration of the channel portion is the same because the work functions of the portions of the gate electrode are different.
本発明は、通常用いられている５ｖ電源電圧に加えて、
たとえば、３Ｖ［源電圧端子をもつもの又は内部で３Ｖ
ｍ源電圧を発生させる回路を内蔵するよう々半導体集積
回路を製造する方法にも適用可能である。１半導体装置
は年々微細化され、これにより、半導体装置のホットエ
レクトロンによる劣化は重要な問題となりつつある。こ
のため内部素子は、微細化された半導体装置で高集積度
を実現し、電源電圧３ｖで動作させ、データの入出力部
は従来と同様に５ＶＷ源電圧で動作させるものに適用で
きる。さらにＬＤＤ構造及びＤＤＤ構造を適用した半導
体装置を製造する場合にも適用可能である。In addition to the commonly used 5V power supply voltage, the present invention provides
For example, 3V [with a source voltage terminal or 3V internally]
The present invention can also be applied to a method of manufacturing a semiconductor integrated circuit having a built-in circuit for generating m source voltage. 1. Semiconductor devices are becoming smaller year by year, and as a result, deterioration of semiconductor devices due to hot electrons is becoming an important problem. For this reason, the internal elements can be applied to devices that realize a high degree of integration using miniaturized semiconductor devices, operate at a power supply voltage of 3V, and operate the data input/output section at a power supply voltage of 5VW as in the conventional case. Furthermore, it is also applicable to the case of manufacturing semiconductor devices to which an LDD structure and a DDD structure are applied.
以上説明したように本発明は、動作電圧の異なるトラン
ジスタを同一基板に形成する際に、厚さの異なるゲート
絶縁膜とゲー）［極とを異なる工程で形成することによ
り、それぞれのゲート絶縁膜の膜厚のばらつきを少（で
き、また、それぞれのゲート絶縁膜を一度の工程で形成
するので、ごみ等によるゲート絶縁膜の欠陥による耐圧
の劣化を防ぐことができるという効果がある。As explained above, when forming transistors with different operating voltages on the same substrate, the present invention enables gate insulating films and gate electrodes with different thicknesses to be formed in different processes. Furthermore, since each gate insulating film is formed in one process, it is possible to prevent deterioration of breakdown voltage due to defects in the gate insulating film due to dust or the like.
第１図（ａ）〜（ｈ）は本発明の一実施例を説明するだ
めの工程順に示した半導体チップの断面図、第２図は第
１図におけるＮチャネルトランジスタの他の例を説明す
るための断面図である。
１０１・・・・・・半導体基板、１０２・・・・・・Ｎ
ウェル、１０３・−・・・・Ｐウェル、１０４・・・・
・・フィールド絶縁膜、１０５・・・・・・第１絶縁膜
、１０６・・・・・・第１多結晶シリコン層、１０６Ａ
、１０６Ｂ・・・・・・第１ゲ ）電極、１０７・・・
・・・第２絶縁膜、１０８・・・・・・第２多結晶シリ
コン層、１０８Ａ、 １０８Ｂ・・・・・・第２ゲー
ト電極、１０９，１０９Ａ・・・・・・Ｎ＋拡散層、
１１０・・・・・・戸拡散層、１１１・・・・・・Ｐ−
拡散層、１１２・・・・・・Ｎ−拡散層、１１３・・・
・・・層間絶縁膜、１１４・・・・・・アルミニウム。
代理人 弁理士 内 原 晋
一
９ −コ＋
Ｊ＋＋Ｉ
２θδＡＮ型彰臂台１５シリコシ
第２ 図1(a) to (h) are cross-sectional views of a semiconductor chip shown in the order of steps to explain one embodiment of the present invention, and FIG. 2 is a diagram illustrating another example of the N-channel transistor in FIG. 1. FIG. 101... Semiconductor substrate, 102...N
Well, 103...P well, 104...
...Field insulating film, 105...First insulating film, 106...First polycrystalline silicon layer, 106A
, 106B...first gear) electrode, 107...
...Second insulating film, 108...Second polycrystalline silicon layer, 108A, 108B...Second gate electrode, 109, 109A...N+ diffusion layer,
110...Diffusion layer, 111...P-
Diffusion layer, 112...N-diffusion layer, 113...
. . . Interlayer insulating film, 114 . . . Aluminum. Agent Patent Attorney Shinichi Uchihara 9 -ko+
J++I 2θδAN type honor stand 15 Sirikoshi Fig. 2
Claims (2)
１絶縁膜とを選択的に形成する工程と、全面に第１多結
晶シリコン層を形成したのちパターニングし前記第１絶
縁膜上に第１ゲート電極を形成する工程と、前記第１ゲ
ート電極下を除き前記第１絶縁膜を除去したのち全面に
膜厚の薄い第２絶縁膜を形成する工程と、全面に第２多
結晶シリコン層を形成したのちパターニングし前記第２
絶縁膜上に第２ゲート電極を形成する工程とを含むこと
を特徴とする半導体装置の製造方法。(1) A step of selectively forming a field insulating film and a thick first insulating film on a semiconductor substrate, and forming a first polycrystalline silicon layer on the entire surface and then patterning it on the first insulating film. forming a first gate electrode; forming a thin second insulating film on the entire surface after removing the first insulating film except under the first gate electrode; and forming a second polycrystalline silicon film on the entire surface. After forming the layer, patterning is performed to form the second layer.
A method for manufacturing a semiconductor device, comprising the step of forming a second gate electrode on an insulating film.
晶シリコン層に不純物を導入する工程及びまたは第２多
結晶シリコン層を形成したのち該第２多結晶シリコン層
に不純物を導入する工程を含む特許請求の範囲第（１）
項記載の半導体装置の製造方法。(2) Step of forming a first polycrystalline silicon layer and then introducing an impurity into the first polycrystalline silicon layer; and/or forming a second polycrystalline silicon layer and then introducing an impurity into the second polycrystalline silicon layer. Claim No. (1) including a process
A method for manufacturing a semiconductor device according to section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62268462A JPH01110761A (en) | 1987-10-23 | 1987-10-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62268462A JPH01110761A (en) | 1987-10-23 | 1987-10-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01110761A true JPH01110761A (en) | 1989-04-27 |
Family
ID=17458837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62268462A Pending JPH01110761A (en) | 1987-10-23 | 1987-10-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01110761A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6541823B1 (en) | 1997-06-09 | 2003-04-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including multiple field effect transistors and manufacturing method thereof |
| EP1347511A1 (en) * | 2002-03-22 | 2003-09-24 | STMicroelectronics S.r.l. | Method for manufacturing a MOS transistor and MOS transistor. |
| US8541279B2 (en) | 2009-09-24 | 2013-09-24 | Seiko Instruments Inc. | Method for manufacturing a semiconductor device having high-voltage and low-voltage transistors |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57107067A (en) * | 1980-12-25 | 1982-07-03 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1987
- 1987-10-23 JP JP62268462A patent/JPH01110761A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57107067A (en) * | 1980-12-25 | 1982-07-03 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6541823B1 (en) | 1997-06-09 | 2003-04-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including multiple field effect transistors and manufacturing method thereof |
| US6853030B2 (en) | 1997-06-09 | 2005-02-08 | Renesas Technology Corp. | Semiconductor device including multiple field effect transistors, with first FETs having oxide spacers and the second FETs having oxide nitride oxidation protection |
| EP1347511A1 (en) * | 2002-03-22 | 2003-09-24 | STMicroelectronics S.r.l. | Method for manufacturing a MOS transistor and MOS transistor. |
| US8541279B2 (en) | 2009-09-24 | 2013-09-24 | Seiko Instruments Inc. | Method for manufacturing a semiconductor device having high-voltage and low-voltage transistors |
| US8975710B2 (en) | 2009-09-24 | 2015-03-10 | Seiko Instruments Inc. | Semiconductor device having a thick gate insulating film covering bird's beak region |
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