JPH01283956A - Semiconductor device and preparation thereof - Google Patents
Semiconductor device and preparation thereofInfo
- Publication number
- JPH01283956A JPH01283956A JP63113935A JP11393588A JPH01283956A JP H01283956 A JPH01283956 A JP H01283956A JP 63113935 A JP63113935 A JP 63113935A JP 11393588 A JP11393588 A JP 11393588A JP H01283956 A JPH01283956 A JP H01283956A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- side wall
- gate electrode
- transistor
- ion implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 44
- 238000005468 ion implantation Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- -1 arsenic ions Chemical class 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 238000005457 optimization Methods 0.000 abstract description 2
- 238000000992 sputter etching Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、Ｎチャネル、Ｐチャネルの両トランジスタの
ゲート電極側壁にスペーサを有する半導体装置とその製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having spacers on the side walls of gate electrodes of both N-channel and P-channel transistors, and a method for manufacturing the same.
従来の技術
半導体装置はますます微細化される傾向にあるが、Ｎチ
ャネル、Ｐチャネルの両トランジスタを有するＣＭＯ８
集積回路においても様々な問題が発生している。Ｎチャ
ネルトランジスタにおいては、ホットキャリア発生によ
る特性の劣化が問題となる。そのためドレイン付近の電
界を弱めるＬｌｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｌｎ構
造（以下ＬＤＤ構造と呼ぶ）が採用されるようになって
きている。このＬＤＤ構造はゲート電極形成後、ｎ″層
形成のためのイオン注入を行い、その後ゲート電極側面
に側壁スペーサＪｔ［し、ソース・ドレインｎ４拡散層
形成のためのイオン注入を行うものである。Ｐチャネル
トランジスタにおいては、通常埋め込みチャネル構造と
なるため、ショートチャネル効果があられれやすい。そ
のためゲート電極側面に側壁スペーサを形成した後にソ
ース・ドレイン形成のためのイオン注入を行い、実効チ
ャネル長を大きくしている。Conventional technology Semiconductor devices are becoming increasingly miniaturized, and CMO8, which has both N-channel and P-channel transistors,
Various problems are also occurring in integrated circuits. In N-channel transistors, deterioration of characteristics due to hot carrier generation poses a problem. Therefore, an Lightly Doped Draln structure (hereinafter referred to as an LDD structure) that weakens the electric field near the drain is increasingly being adopted. In this LDD structure, after forming a gate electrode, ion implantation is performed to form an n'' layer, then sidewall spacers Jt are formed on the side surfaces of the gate electrode, and ion implantation is performed to form a source/drain n4 diffusion layer. P-channel transistors usually have a buried channel structure, so they are prone to short channel effects.Therefore, after forming sidewall spacers on the sides of the gate electrode, ion implantation is performed to form the source and drain, increasing the effective channel length. are doing.
以下に上記の構造を採用した従来例について述べる。第
２図（ａ）〜（Ｃ）に従来例の断面図を主な工程の順に
示している。例えばＰ型Ｓｉ基板１上にＮウェル２、フ
ィールド酸化膜３を形成した後、例えば膜厚１５ｎｍの
ゲート酸化膜４上にｎ４多結晶シリコンを堆積し、ゲー
ト電極５を形成する［第２図（ａ）］。次に、Ｎウェル
２を形成していないＮチャネル領域にＬＤＤ構造のため
のｎ−拡散層形成を、例えば燐をドーズ量２×１０”ｃ
ｍ−”でイオン注入して行う。その後ＣＶＤ法により例
えば膜厚２５０ｎｍのＳｉＯａｇを堆積し、この膜に対
して例えばＣＨＦ ｓガスによる異方性を持つ反応性イ
オンエツチングを施すことにより、ゲート電極５側面に
側壁スペーサ１１を形成する［第２図（ｂ）コ。この状
態でＮチャネル領域には例えば砒素を４Ｘ１０”ｃｍ−
”のドーズ量で、Ｎウェル中のＰチャネル領域には例え
ばＢＦ２イオンを３Ｘ１０Ｉｓｃｍ−”のドーズ量でイ
オン注入し、熱処理を行うことにより、それぞれのソー
ス−ドレイン領域８．１０を形成する［第２図（Ｃ）］
。A conventional example employing the above structure will be described below. FIGS. 2(a) to 2(C) show sectional views of a conventional example in the order of main steps. For example, after forming an N well 2 and a field oxide film 3 on a P-type Si substrate 1, N4 polycrystalline silicon is deposited on a gate oxide film 4 with a thickness of 15 nm, for example, to form a gate electrode 5 [Fig. (a)]. Next, an n-diffusion layer for the LDD structure is formed in the N-channel region where the N-well 2 is not formed, for example, by dosing phosphorus at a dose of 2×10”c.
This is done by ion implantation with 250 nm thick film by CVD method, and this film is subjected to anisotropic reactive ion etching using, for example, CHF s gas to form the gate electrode. Sidewall spacers 11 are formed on the 5 sides [FIG. 2(b)]. In this state, for example, arsenic is applied to the N channel region at a thickness of 4 x 10" cm.
For example, BF2 ions are implanted into the P channel region in the N well at a dose of 3×10 Iscm-, and heat treatment is performed to form respective source-drain regions 8.10. Figure 2 (C)]
.
この後、層間絶縁膜を形成し、コンタクト孔を開孔して
、例えばＡ１合金による配線層を形成するとトランジス
タは完成する。Thereafter, an interlayer insulating film is formed, a contact hole is opened, and a wiring layer made of, for example, an A1 alloy is formed to complete the transistor.
以上のような従来の方法によれば、Ｎチャネルトランジ
スタにおいてはＬＤＤ構造が実現され、Ｐチャネルトラ
ンジスタにおいては側壁スペーサ１１の存在により実効
チャネル長を大きくすることができる。According to the conventional method as described above, an LDD structure is realized in the N-channel transistor, and the effective channel length can be increased in the P-channel transistor due to the presence of the sidewall spacer 11.
発明が解決しようとする課題
しかしながら上に述べた方法によれば、ゲート電極５側
面に形成した側壁スペーサ１１の幅（断面表示における
厚みをさし、以下スペーサ幅と呼ぶ）が両チャネルに共
通となっているため、必ずしもそれぞれのチャネルに対
して適切なスペーサ幅となっていない。Ｎチャネルトラ
ンジスタにおけるＬＤＤ構造では、スペーサ幅が大きい
とｎ−拡散層が長くなり、ソース争ドレインへの直列抵
抗の付加が大きくなる。逆に、スペーサ幅が小さすぎる
と電界緩和効果が得られないが、ある程度のスペーサ幅
があれば電界緩和効果が得られる。Problems to be Solved by the Invention However, according to the method described above, the width of the sidewall spacer 11 formed on the side surface of the gate electrode 5 (referring to the thickness in cross-sectional view, hereinafter referred to as spacer width) is common to both channels. Therefore, the spacer width is not necessarily appropriate for each channel. In the LDD structure of an N-channel transistor, if the spacer width is large, the n-diffusion layer becomes long, and the addition of series resistance between the source and the drain becomes large. Conversely, if the spacer width is too small, the electric field relaxation effect cannot be obtained, but if the spacer width is to a certain extent, the electric field relaxation effect can be obtained.
一方、Ｐチャネルトランジスタにおいては、スペーサ幅
の増加によって実効チャネル長が増大し、ショートチャ
ネル効果が抑えられる。したがって、それぞれのチャネ
ルにより最適なスペーサ幅が存在するので、別々にスペ
ーサ幅を設定できることが望まれる。On the other hand, in a P-channel transistor, increasing the spacer width increases the effective channel length and suppresses the short channel effect. Therefore, since there is an optimal spacer width for each channel, it is desirable to be able to set the spacer widths separately.
そこで、本発明はＮチャネルとＰチャネルの両トランジ
スタがそれぞれ最適な状態で形成された半導体装置およ
びその製造方法を提供することを目的としている。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device in which both N-channel and P-channel transistors are formed in optimal conditions, and a method for manufacturing the same.
課題を解決するための手段
本発明の技術的手段は、ソース書ドレイン領域形成のた
めの自己整合的なイオン注入のマスクとなる側壁スペー
サの幅を、ＮチャネルとＰチャネルのそれぞれのトラン
ジスタで別々に設定することである。Means for Solving the Problems The technical means of the present invention is to separate the widths of sidewall spacers, which serve as masks for self-aligned ion implantation for forming source write/drain regions, for N-channel and P-channel transistors. It is to set it to .
作用
本発明によれば前記した構造により、Ｎチャネルトラン
ジスタの特性の最適化とＰチャネルトランジスタの特性
の最適化がそれぞれ独立に行え、両トランジスタとも最
適の特性が得られるようになる。According to the present invention, with the above-described structure, the characteristics of the N-channel transistor and the P-channel transistor can be optimized independently, and the optimal characteristics can be obtained for both transistors.
実施例
本発明の実施例の断面図を第１図（ａ）〜（ｃ）に示し
た。以下に工程の順を追って説明する。Embodiment Cross-sectional views of an embodiment of the present invention are shown in FIGS. 1(a) to 1(c). The steps will be explained step by step below.
例えばＰ型Ｓｉ基板１上にＮウェル２、フィールド酸化
ｒ！Ｘ３を形成した後、例えば膜厚１５ｎｍゲート酸化
膜４上にｎ４多結晶シリコンを堆積し、ゲート電極５を
形成し、Ｎチャネル領域にＬＤＤ構造のためのｎ−拡散
層形成を、例えば燐をドーズｆｆ１２Ｘ １０”ｃｍ−
２でイオン注入して行う工程までは従来例と同様である
。次に、ＣＶＤ法により例えば膜厚１５０ｎｍの５ｉｎ
２膜を堆積し、この膜に対して例えばＣＨＦ ａガスに
よる異方性を持つ反応性イオンエツチングを施すことに
より、ゲート電極５の側面に約１５０ｎｍの幅を持つ第
１の側壁スペーサ７を形成する［第１図（ａ）］。For example, on a P-type Si substrate 1, an N well 2 and a field oxidation r! After forming X3, for example, N4 polycrystalline silicon is deposited on the gate oxide film 4 with a film thickness of 15 nm, a gate electrode 5 is formed, and an n- diffusion layer for an LDD structure is formed in the N channel region by, for example, phosphorus. Dose ff12X 10”cm-
The steps up to step 2 of ion implantation are the same as in the conventional example. Next, for example, a 5-inch film with a film thickness of 150 nm is formed by the CVD method.
A first sidewall spacer 7 having a width of about 150 nm is formed on the side surface of the gate electrode 5 by depositing two films and subjecting this film to anisotropic reactive ion etching using, for example, CHFa gas. [Figure 1(a)].
ゲート電極５と第１の側壁スペーサ７とを自己整合的な
イオン注入のマスクとして、Ｎチャネル領域のみに例え
ば砒素を４Ｘ １０Ｉ′ｃｍ−’のドーズ量でイオン注
入する［第１図（ｂ）コ０ さらに１ＣＶＤ法により例
えば膜厚１５０ｎｍのＳ ｉ ０２膜を堆積し、これに
異方性エツチングを施すことにより、第１の側壁スペー
サ７の外側に約１５０ｎｍの幅を持つ第２の側壁スペー
サ９を形成し、ゲート電極５と第１の側壁スペーサ７と
第２の側壁スペーサ９とを自己整合的なイオン注入のマ
スクとして、Ｐチャネル領域にのみ例えばＢＦ２イオン
を３Ｘ １０”ｃｍ”のドーズ量でイオン注入する。Using the gate electrode 5 and the first sidewall spacer 7 as a mask for self-aligned ion implantation, ions of arsenic, for example, are implanted only into the N channel region at a dose of 4×10 I'cm [FIG. 1(b)] Further, by depositing a SiO2 film with a thickness of, for example, 150 nm by CVD method and subjecting it to anisotropic etching, a second side wall spacer having a width of about 150 nm is formed outside the first side wall spacer 7. 9, and using the gate electrode 5, the first sidewall spacer 7, and the second sidewall spacer 9 as masks for self-aligned ion implantation, for example, BF2 ions are implanted only in the P channel region at a dose of 3×10 cm. ions are implanted in large amounts.
その後熱処理を行うことにより、それぞれのチャネルの
トランジスタのソース・ドレイン領域８．１０を形成す
る［第２図（Ｃ）］。さらに、層間絶縁膜を形成し、コ
ンタクト孔を開孔して、例えばＡ１合金による配線層を
形成してトランジスタを完成させる工程は従来例と同様
である。Thereafter, a heat treatment is performed to form source/drain regions 8.10 of transistors of each channel [FIG. 2(C)]. Further, the steps of forming an interlayer insulating film, opening contact holes, and forming a wiring layer made of, for example, A1 alloy to complete the transistor are the same as in the conventional example.
以上のように、本実施例によれば、Ｎチャネルトランジ
スタとＰチャネル−トランジスタとの自己整合的なソー
ス・ドレインへのイオン注入のマスクとしてそれぞれ異
なる側壁スペーサ幅を設定できる。すなわち、上記の例
でいえば自己整合的なイオン注入のマスクの幅は、Ｎチ
ャネルでは、ゲート電極５に第１の側壁スペーサ７の幅
を加えたものとなり、ＰチャネルではＮチャネルのマス
ク幅にさらに第２の側壁スペーサ９の幅を加えたものと
なっている。As described above, according to this embodiment, different sidewall spacer widths can be set as masks for self-aligned ion implantation into the sources and drains of an N-channel transistor and a P-channel transistor. That is, in the above example, the width of the mask for self-aligned ion implantation is the width of the gate electrode 5 plus the width of the first sidewall spacer 7 for the N channel, and the width of the mask for the N channel for the P channel. , plus the width of the second side wall spacer 9.
なお、実施例において第１の側壁スペーサ７のスペーサ
幅を約１５０ｎｍとし、第２の側壁スペーサ９のスペー
サ幅を約１５０ｎｍとしたが、最適なスペーサ幅はトラ
ンジスタのゲート酸化膜の膜厚や基板の不純物プロファ
イル等により異なるので、上記のスペーサ幅がすべての
トランジスタに有効というわけではなく、スペーサ幅は
変えてもよいことは言うまでもない。In the example, the spacer width of the first sidewall spacer 7 was approximately 150 nm, and the spacer width of the second sidewall spacer 9 was approximately 150 nm, but the optimal spacer width depends on the thickness of the gate oxide film of the transistor and the substrate. It goes without saying that the above spacer width is not effective for all transistors because it differs depending on the impurity profile, etc., and that the spacer width may be changed.
発明の詳細
な説明したように、本発明によれば、ＮチャネルとＰチ
ャネルのそれぞれのトランジスタのソース・ドレイン形
成のためのイオン注入において、自己整合的なイオン注
入のマスクの幅をチャネルごとに独立に設定することが
でき、その結果、ＮチャネルにおいてはＬＤＤ構造のＲ
適化が図られ、またＰチャネルトランジスタにおいては
実効チャネル長の増大によるショートチャネル効果の改
善が図られるので、その実用的効果は大きい。As described in detail, according to the present invention, in ion implantation for forming sources and drains of N-channel and P-channel transistors, the width of a self-aligned ion implantation mask is adjusted for each channel. can be set independently, and as a result, in the N channel, the R of the LDD structure
This has a great practical effect because optimization is achieved, and in the case of P-channel transistors, the short channel effect is improved by increasing the effective channel length.
第１図は本発明における実施例を工程順に示した半導体
装置の断面図、第２図は従来例を工程順に示した半導体
装置の断面図である。
１・・・・Ｐ型Ｓｔ基板、２・・・・Ｎウェル、５・・
・・ゲート電極、６・・・・ｎ−拡散層、７・・・・第
１の側壁スペーサ、８・・・・ｎ″″拡散層、９・・・
・第２の側壁スペーサ、１０・・・・ｐ４拡散層、１１
・・・・側壁スペーサ。
代理人の氏名 弁理士 中尾敏男 はが１名ト ト
Φ
派 −
１Ω
′−〇
ヘ リFIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view of a semiconductor device showing a conventional example in the order of steps. 1...P type St substrate, 2...N well, 5...
...gate electrode, 6...n-diffusion layer, 7...first sidewall spacer, 8...n'' diffusion layer, 9...
・Second sidewall spacer, 10...p4 diffusion layer, 11
...Side wall spacer. Name of agent: Patent attorney Toshio Nakao, 1 person, Φ faction − 1Ω
′−〇Heli
Claims (2)
Ｓトランジスタを有し、ゲート電極側面に形成され、ソ
ース・ドレイン領域形成のための自己整合的なイオン注
入のマスクとなる側壁スペーサの幅をそれぞれのチャネ
ルごとに設定することを特徴とする半導体装置。(1) Both N-channel and P-channel MO on a semiconductor substrate
A semiconductor device having an S transistor, characterized in that the width of a sidewall spacer formed on a side surface of a gate electrode and serving as a mask for self-aligned ion implantation for forming a source/drain region is set for each channel. .
ーサを形成し、Ｎチャネルトランジスタのソース・ドレ
イン形成のためのイオン注入を行った後、前記第１の側
壁スペーサの外側に第２の側壁スペーサを形成し、Ｐチ
ャネルトランジスタのソース・ドレイン形成のためのイ
オン注入を行うことを特徴とする半導体装置の製造方法
。(2) After forming a first sidewall spacer on the side surface of the gate electrode on the semiconductor substrate and performing ion implantation to form the source and drain of an N-channel transistor, a second sidewall spacer is formed on the outside of the first sidewall spacer. A method of manufacturing a semiconductor device, comprising forming sidewall spacers and performing ion implantation to form a source and drain of a P-channel transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63113935A JPH01283956A (en) | 1988-05-11 | 1988-05-11 | Semiconductor device and preparation thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63113935A JPH01283956A (en) | 1988-05-11 | 1988-05-11 | Semiconductor device and preparation thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01283956A true JPH01283956A (en) | 1989-11-15 |
Family
ID=14624885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63113935A Pending JPH01283956A (en) | 1988-05-11 | 1988-05-11 | Semiconductor device and preparation thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01283956A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05110003A (en) * | 1991-10-16 | 1993-04-30 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
| US5296401A (en) * | 1990-01-11 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof |
| JPH06268165A (en) * | 1991-02-27 | 1994-09-22 | Samsung Electron Co Ltd | Preparation of semiconductor transistor and its structure |
| JPH06342884A (en) * | 1991-07-09 | 1994-12-13 | Samsung Electron Co Ltd | Mos semiconductor device and its manufacture |
| JPH07122649A (en) * | 1993-10-26 | 1995-05-12 | Matsushita Electric Ind Co Ltd | Fabrication of cmos transistor |
| JPH08321557A (en) * | 1995-05-24 | 1996-12-03 | Nec Corp | Fabrication of cmos semiconductor device |
| KR100234700B1 (en) * | 1996-11-27 | 1999-12-15 | 김영환 | Manufacturing method of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS593918A (en) * | 1982-06-29 | 1984-01-10 | Toshiba Corp | Manufacture of complementary semiconductor device |
| JPS6484659A (en) * | 1987-09-28 | 1989-03-29 | Toshiba Corp | Manufacture of semiconductor device |
-
1988
- 1988-05-11 JP JP63113935A patent/JPH01283956A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS593918A (en) * | 1982-06-29 | 1984-01-10 | Toshiba Corp | Manufacture of complementary semiconductor device |
| JPS6484659A (en) * | 1987-09-28 | 1989-03-29 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5296401A (en) * | 1990-01-11 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof |
| JPH06268165A (en) * | 1991-02-27 | 1994-09-22 | Samsung Electron Co Ltd | Preparation of semiconductor transistor and its structure |
| JPH06342884A (en) * | 1991-07-09 | 1994-12-13 | Samsung Electron Co Ltd | Mos semiconductor device and its manufacture |
| JPH05110003A (en) * | 1991-10-16 | 1993-04-30 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
| JPH07122649A (en) * | 1993-10-26 | 1995-05-12 | Matsushita Electric Ind Co Ltd | Fabrication of cmos transistor |
| JPH08321557A (en) * | 1995-05-24 | 1996-12-03 | Nec Corp | Fabrication of cmos semiconductor device |
| KR100234700B1 (en) * | 1996-11-27 | 1999-12-15 | 김영환 | Manufacturing method of semiconductor device |
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