JPS63272066A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63272066A JPS63272066A JP62104736A JP10473687A JPS63272066A JP S63272066 A JPS63272066 A JP S63272066A JP 62104736 A JP62104736 A JP 62104736A JP 10473687 A JP10473687 A JP 10473687A JP S63272066 A JPS63272066 A JP S63272066A
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- element region
- forming
- type element
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000000034 method Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 239000011248 coating agent Substances 0.000 claims abstract 2
- 238000000576 coating method Methods 0.000 claims abstract 2
- 238000009792 diffusion process Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- -1 arsenic ions Chemical class 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 235000014548 Rubus moluccanus Nutrition 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に相補型ＭＯ
３半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
3. This invention relates to a method for manufacturing a semiconductor device.
一部に、相補型ＭＯ３（以下、Ｃ−ＭＯＳと称する）半
導体装置は、消費電力が小さいという利点を有している
が、Ｐチャネル、Ｎチャネルの各ＭＯ３）ランジスタを
形成しなければならないため、製造工程が煩雑であると
いう欠点がある。In part, complementary MO3 (hereinafter referred to as C-MOS) semiconductor devices have the advantage of low power consumption, but because they require the formation of P-channel and N-channel MO3) transistors, However, it has the disadvantage that the manufacturing process is complicated.
例えば、従来のＣ−ＭＯＳの製造方法を第３図（ａ）乃
至（ｄ）に示す。For example, a conventional C-MOS manufacturing method is shown in FIGS. 3(a) to 3(d).
先ず、同図（ａ）のように、例えばＰ型シリコン基板３
１の一部に選択的にＮ型ウェル領域３２を形成した後、
フィールド酸化膜３３を形成して活性化領域を画成する
。そして、この上にゲート酸化膜３４を形成し、更に全
面に多結晶シリコンを成長した上で、これを写真蝕刻技
術を用いてパターニングすることによりゲート電極３５
Ｎ、３５Ｐを形成する。First, as shown in the same figure (a), for example, a P-type silicon substrate 3 is
After selectively forming an N-type well region 32 in a part of 1,
A field oxide film 33 is formed to define an active region. Then, a gate oxide film 34 is formed on this, polycrystalline silicon is further grown on the entire surface, and this is patterned using photolithography to form a gate electrode 35.
N, forming 35P.
次いで、同図（ｂ）のように、ＰＭＯ３形成領域をレジ
スト３６で覆い、砒素（Ａｓ）をイオン注入で導入し、
ＮチャネルＭＯ３Ｉ−ランジスタのソース・ドレイン領
域３７Ｎを形成する。Next, as shown in FIG. 3(b), the PMO3 formation region is covered with a resist 36, and arsenic (As) is introduced by ion implantation.
Source/drain regions 37N of an N-channel MO3I-transistor are formed.
続いて、第３図（Ｃ）のように、今度はＮＭＯ３形成領
域をレジスト３８で覆い、ボロン（Ｂ）をイオン注入で
導入し、ＰチャネルＭＯＳトランジスタのソース・ドレ
イン領域３７Ｐを形成する。Subsequently, as shown in FIG. 3C, the NMO3 formation region is covered with a resist 38, and boron (B) is ion-implanted to form the source/drain region 37P of the P-channel MOS transistor.
以下、通常の工程に従って眉間絶縁膜３９の堆積、コン
タクトホール３９ａの開孔、配線４０の形成を行なうこ
とにより、同図（ｄ）のように、Ｃ−ＭＯ３半導体装置
が完成される。Thereafter, a glabellar insulating film 39 is deposited, a contact hole 39a is formed, and a wiring 40 is formed according to the usual steps, thereby completing a C-MO3 semiconductor device as shown in FIG. 2D.
しかしながら、従来のＣ−ＭＯＳの形成方法では、上述
したように写真蝕刻技術がゲート電極３５Ｎ、３５Ｐの
形成からソース・ドレイン領域３７Ｎ、３７Ｐの形成ま
で３回あり、工程が複雑でコストが高くなるという問題
が生じている。However, in the conventional C-MOS formation method, as mentioned above, the photolithography process is performed three times from the formation of the gate electrodes 35N and 35P to the formation of the source/drain regions 37N and 37P, resulting in a complicated process and high cost. This problem has arisen.
また、最近ＭＯ３）ランジスタのゲート実効長が短くな
るにつれて、ホットエレクトロンによるトランジスタの
劣化等の対策のため、ソース・ドレイン領域に低濃度不
純物領域を形成したＬＤＤ（Ｌｉｇｈｔｌｙ Ｄｏｐｅ
ｄ Ｄｒａｉｎ ）構造のトランジスタが採用されてい
るが、この種のトランジスタの製造方法では、ＬＤＤを
形成するために写真蝕刻工程を更に増加させる必要があ
る。In addition, as the effective gate length of MO3) transistors has recently become shorter, LDDs (Lightly Dope
d Drain ) structure has been adopted, but in the method of manufacturing this type of transistor, it is necessary to further increase the number of photolithographic processes to form an LDD.
本発明は工程の簡略化及び低コスト化を可能にした半導
体装置の製造方法を提供することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that enables simplified steps and lower costs.
本発明の半導体装置の製造方法は、一の導電型の半導体
基板に第１導電型素子及び第２導電型素子の各領域を画
成しかつ各領域にゲート絶縁膜を形成する工程と、半導
体基板上に多結晶半導体膜を形成する工程と、この多結
晶半導体膜を第２導電型素子領域でそのまま残し、第１
導電型素子領域でゲート電極に形成する工程と、前記第
１導電型素子領域に第１導電型不純物を導入してソース
・ドレイン領域を形成する工程と、前記第１導電型素子
領域をフォトレジスト等で被覆した上で、第２導電型素
子領域に前記多結晶半導体膜でゲート電極を形成する工
程と、前記第２導電型素子領域に第２導電型不純物を導
入してソース・ドレイン領域を形成する工程を含んでい
る。A method for manufacturing a semiconductor device according to the present invention includes the steps of defining regions of a first conductivity type element and a second conductivity type element on a semiconductor substrate of one conductivity type and forming a gate insulating film in each region; A step of forming a polycrystalline semiconductor film on the substrate, leaving this polycrystalline semiconductor film as it is in the second conductivity type element region, and forming the polycrystalline semiconductor film on the substrate.
a step of forming a gate electrode in a conductive type element region, a step of introducing a first conductive type impurity into the first conductive type element region to form a source/drain region, and a step of forming a photoresist on the first conductive type element region. and forming a gate electrode using the polycrystalline semiconductor film in the second conductivity type element region, and introducing a second conductivity type impurity into the second conductivity type element region to form source/drain regions. It includes a step of forming.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）乃至（ｄ）は本発明の第１実施例を製造工
程順に示す断面図である。FIGS. 1(a) to 1(d) are cross-sectional views showing a first embodiment of the present invention in the order of manufacturing steps.
先ず、第１図（ａ）のようにＰ型シリコン基板１１の一
部にＮ型ウェル領域１２を形成した後、選択酸化力によ
りフィールド酸化膜１３を１．ｃｚｍの厚さに形成する
。また、活性化領域にはゲート酸化膜１４を厚さ５００
人で形成する。そして、全面に多結晶シリコン１５を堆
積する。First, as shown in FIG. 1(a), after forming an N-type well region 12 in a part of a P-type silicon substrate 11, a field oxide film 13 is oxidized by selective oxidation. Formed to a thickness of czm. In addition, a gate oxide film 14 is formed in the active region to a thickness of 500 mm.
Formed by people. Then, polycrystalline silicon 15 is deposited on the entire surface.
続いて、同図（ｂ）のように、フォトレジスト１６を利
用した写真蝕刻技術を用いてＮＭＯ３形成領域の多結晶
シリコン１５のみをパターニングしてＮチャネルＭＯＳ
トランジスタのゲート電極１５Ｎを形成する。そして、
形成後に砒素のイオン注入を行い、ＮチャネルＭｏＳト
ランジスタのソース・ドレイン領域１７Ｎを形成する。Subsequently, as shown in FIG. 3B, only the polycrystalline silicon 15 in the NMO3 formation region is patterned using photolithography using a photoresist 16 to form an N-channel MOS.
A gate electrode 15N of the transistor is formed. and,
After the formation, arsenic ions are implanted to form source/drain regions 17N of an N-channel MoS transistor.
次に、同図（Ｃ）のように、前記フォトレジスト１６を
除去した後、改めてフォトレジスト１８を利用した写真
蝕刻技術によりＰＭＯＳ形成領域に残された多結晶シリ
コン１５をパターニングしてＰチャネルＭＯ３Ｉ−ラン
ジスタのゲート電極１５Ｐを形成する。このとき、Ｎ
Ｍ ＯＳ 領域は前記フォトレジスト１８で覆っておく
。そして、この状態でボロンのイオン注入を行い、Ｐチ
ャネルＭＯＳトランジスタのソース・ドレイン領域１７
ｐを形成する。Next, as shown in FIG. 3C, after removing the photoresist 16, the polycrystalline silicon 15 remaining in the PMOS formation region is patterned again by photolithography using the photoresist 18 to form a P-channel MO3I. - Form the gate electrode 15P of the transistor. At this time, N
The MOS region is covered with the photoresist 18. In this state, boron ions are implanted into the source/drain regions 17 of the P-channel MOS transistor.
form p.
以下、同図（ｄ）のようにフォトレジスト１８を除去後
、通常の工程に従い、層間絶縁膜１９の堆積、コンタク
トホール１９ａの開孔、配線２０を形成することにより
、Ｃ−ＭＯ３半導体装置を完成する。After removing the photoresist 18, as shown in FIG. 2D, the C-MO3 semiconductor device is manufactured by depositing an interlayer insulating film 19, forming contact holes 19a, and forming interconnections 20 in accordance with the usual process. Complete.
以上の工程では、ゲート電極１５Ｎ、１５Ｐの形成から
ソース・ドレイン領域１７Ｎ、１７Ｐの形成まで２回の
写真蝕刻工程で形成でき、工程の簡略化を達成できる。In the above steps, the steps from forming the gate electrodes 15N and 15P to forming the source/drain regions 17N and 17P can be formed in two photolithography steps, thereby simplifying the steps.
第２図（ａ）及び（ｂ）は本発明の第２実施例の主要工
程を示す断面図であり、この実施例ではＬＤＤ構造のト
ランジスタに本発明を適用した例を示している。FIGS. 2(a) and 2(b) are cross-sectional views showing the main steps of a second embodiment of the present invention, and this embodiment shows an example in which the present invention is applied to a transistor having an LDD structure.
先ず、第２図（ａ）のように、第１実施例と同様にＰ型
シリコン基板２１にＮ型ウェル２２．フィールド酸化Ｍ
、２３．ゲート酸化膜２４を順次形成し、更に多結晶シ
リコン２５を形成してこれをフォトレジスト２６により
パターニングしてＮチャネルＭＯ３）ランジスタの電極
２５Ｎを形成する。そして、砒素を低ドーズ量でイオン
注入して浅い拡散層２７Ｎ′を形成する。First, as shown in FIG. 2(a), an N-type well 22. is formed in a P-type silicon substrate 21 as in the first embodiment. field oxidation M
, 23. A gate oxide film 24 is sequentially formed, and then polycrystalline silicon 25 is formed and patterned using a photoresist 26 to form an electrode 25N of an N-channel MO3) transistor. Then, arsenic is ion-implanted at a low dose to form a shallow diffusion layer 27N'.
続いて、同図（ｂ）に示すように、シリコン酸化膜等の
絶縁膜を堆積させた上で、これを異方性エツチング法に
よりエッチバックして、前記ゲート電極２５Ｎの側壁に
サイドウオール２５′を形成し、この状態で砒素を高ド
ーズ量でイオン注入して深い拡散層２７Ｎ＃を形成する
。これにより、ＬＤＤ構造のソース・ドレイン領域２７
Ｎが形成され、ＮチャネルＭＯ３）ランジスタが形成さ
れる。Subsequently, as shown in FIG. 2B, an insulating film such as a silicon oxide film is deposited and then etched back by an anisotropic etching method to form a side wall 25 on the side wall of the gate electrode 25N. ' is formed, and in this state, arsenic is ion-implanted at a high dose to form a deep diffusion layer 27N#. As a result, the source/drain region 27 of the LDD structure
N is formed, and an N-channel MO3) transistor is formed.
以下、説明は省略するが、第１実施例の第１図（Ｃ）及
び（ｄ）の工程を実行することにより、ＬＤＤ構造のＮ
チャネルＭＯＳトランジスタと、通常のＰチャネルＭＯ
３）ランジスタとで構成されるＣ−ＭＯ３半導体装置が
完成される。Although the explanation will be omitted below, by carrying out the steps shown in FIGS. 1(C) and (d) of the first embodiment, the N
Channel MOS transistor and normal P channel MO
3) A C-MO3 semiconductor device composed of transistors is completed.
この実施例においても、ゲート電極からソース・ドレイ
ン領域の形成まで、２回の写真蝕刻技術で製造できる。In this embodiment as well, the steps from the gate electrode to the formation of the source/drain regions can be manufactured by two photolithography steps.
なお、前記実施例はＮチャネルＭＯＳトランジスタにつ
いて説明したが、ＰチャネルＭＯ３Ｉ−ランジスタにお
いても同様に適用できる。It should be noted that, although the above embodiment has been described with respect to an N-channel MOS transistor, it can be similarly applied to a P-channel MO3I-transistor.
以上説明したように本発明は、半導体基板上に形成した
多結晶半導体膜を第２導電型素子領域でそのまま残し、
第１導電型素子領域でゲート電極に形成するとともにソ
ース・ドレイン領域を形成し、次いで第１導電型素子領
域をフォトレジスト等で被覆した上で、第２導電型素子
領域に前記多結晶半導体膜でゲート電極を形成するとと
もにソース・ドレイン領域を形成しているので、ゲート
電極形成からＣ−ＭＯ３完成までにおける写真蝕刻工程
数を低減でき、工程の簡略及び低コスト化を実現で・き
る。また、これはＬＤＤ構造のトランジスタを製造する
場合でも同様である。As explained above, the present invention leaves a polycrystalline semiconductor film formed on a semiconductor substrate as it is in the second conductivity type element region,
A gate electrode is formed in the first conductivity type element region, and a source/drain region is formed, and then the first conductivity type element region is covered with a photoresist or the like, and then the polycrystalline semiconductor film is formed in the second conductivity type element region. Since the gate electrode is formed and the source/drain regions are also formed, the number of photolithography steps from gate electrode formation to completion of C-MO3 can be reduced, and process simplification and cost reduction can be realized. Further, this also applies when manufacturing a transistor having an LDD structure.
第１図（ａ）乃至第１図（ｄ）は本発明の第１実施例を
工程順に示す断面図、第２図（ａ）及び第２図（ｂ）は
第２実施例の主要工程を示す断面図、第３図（ａ）乃至
第３図（ｄ）は従来の製造方法を工程順に示す断面図で
ある。
１１．２１．３１・・・Ｐ型シリコン基板、１２，２２
．３２・・・Ｎ型ウェル、１３，２３．３３・・・フィ
ールド酸化膜、１４，２４．３４・・・ゲート酸化膜、
１５．２５・・・多結晶シリコン、１５Ｎ、２５Ｎ。
３５Ｎ・・・ＮＭＯＳゲート電極、１５Ｐ、２５Ｐ。
３５Ｐ・・・ＰＭＯＳゲート電極、１６，２６．３６・
・・フォトレジスト、１７Ｎ、２７Ｎ、３７Ｎ・・・Ｎ
ＭＯＳソース・ドレイン領域、１７Ｐ、２７Ｐ。
３７Ｐ・・・ＰＭＯＳソニス・ドレイン領域、２７Ｎ’
・・・低ドーズ量浅い拡散層、２７Ｎ″・・・高ドーズ
領域深い拡散層、１８．３８・・・フォトレジスト、１
９．３９・・・層間絶縁膜、２０．４０・・・配線。
第１図
第１図
１／Ｎ
第３図
第３図FIGS. 1(a) to 1(d) are cross-sectional views showing the first embodiment of the present invention in the order of steps, and FIGS. 2(a) and 2(b) are sectional views showing the main steps of the second embodiment. The cross-sectional views shown in FIGS. 3(a) to 3(d) are cross-sectional views showing the conventional manufacturing method in the order of steps. 11.21.31...P-type silicon substrate, 12,22
．． 32...N-type well, 13,23.33...Field oxide film, 14,24.34...Gate oxide film,
15.25...Polycrystalline silicon, 15N, 25N. 35N...NMOS gate electrode, 15P, 25P. 35P...PMOS gate electrode, 16,26.36.
...Photoresist, 17N, 27N, 37N...N
MOS source/drain region, 17P, 27P. 37P...PMOS sonis drain region, 27N'
...Low dose shallow diffusion layer, 27N''...High dose region deep diffusion layer, 18.38...Photoresist, 1
9.39...Interlayer insulating film, 20.40...Wiring. Figure 1 Figure 1 1/N Figure 3 Figure 3
Claims (2)
２導電型素子の各領域を画成しかつ各領域にゲート絶縁
膜を形成する工程と、前記半導体基板上に多結晶半導体
膜を形成する工程と、この多結晶半導体膜を第２導電型
素子領域でそのまま残し、第１導電型素子領域でゲート
電極に形成する工程と、前記第１導電型素子領域に第１
導電型不純物を導入してソース・ドレイン領域を形成す
る工程と、前記第１導電型素子領域をフォトレジスト等
で被覆した上で、第２導電型素子領域に前記多結晶半導
体膜でゲート電極を形成する工程と、前記第２導電型素
子領域に第２導電型不純物を導入してソース・ドレイン
領域を形成する工程を含むことを特徴とする半導体装置
の製造方法。(1) A step of defining each region of a first conductivity type element and a second conductivity type element on a semiconductor substrate of one conductivity type and forming a gate insulating film in each region, and forming a polycrystalline semiconductor on the semiconductor substrate. forming a polycrystalline semiconductor film, leaving the polycrystalline semiconductor film as it is in the second conductivity type element region and forming a gate electrode in the first conductivity type element region, and forming a first conductivity type film in the first conductivity type element region.
A step of introducing conductivity type impurities to form source/drain regions, and coating the first conductivity type element region with a photoresist or the like, and forming a gate electrode using the polycrystalline semiconductor film in the second conductivity type element region. A method of manufacturing a semiconductor device, comprising the steps of: forming a source/drain region; and introducing a second conductivity type impurity into the second conductivity type element region to form a source/drain region.
して浅い拡散層を形成する工程と、その後絶縁膜を堆積
しかつこれを異方性エッチングしてゲート電極の側面に
絶縁膜を残す工程と、高ドーズ量で不純物を導入して深
い拡散層を形成する工程を含む特許請求の範囲第１項記
載の半導体装置の製造方法。(2) After forming the gate electrode, a process of introducing impurities at a low dose to form a shallow diffusion layer, followed by depositing an insulating film and etching it anisotropically to leave the insulating film on the sides of the gate electrode. 2. The method of manufacturing a semiconductor device according to claim 1, comprising the step of forming a deep diffusion layer by introducing impurities at a high dose.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62104736A JPS63272066A (en) | 1987-04-30 | 1987-04-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62104736A JPS63272066A (en) | 1987-04-30 | 1987-04-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63272066A true JPS63272066A (en) | 1988-11-09 |
Family
ID=14388781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62104736A Pending JPS63272066A (en) | 1987-04-30 | 1987-04-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63272066A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0786423A (en) * | 1993-09-14 | 1995-03-31 | Nec Corp | Manufacture of mis type semiconductor integrated circuit device |
| JP2002368123A (en) * | 2001-06-07 | 2002-12-20 | Nec Corp | Production method for mos-type semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5843556A (en) * | 1981-09-08 | 1983-03-14 | Toshiba Corp | Manufacture of complementary semiconductor device |
| JPS61183967A (en) * | 1985-02-08 | 1986-08-16 | Toshiba Corp | Manufacture of semiconductor device |
-
1987
- 1987-04-30 JP JP62104736A patent/JPS63272066A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5843556A (en) * | 1981-09-08 | 1983-03-14 | Toshiba Corp | Manufacture of complementary semiconductor device |
| JPS61183967A (en) * | 1985-02-08 | 1986-08-16 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0786423A (en) * | 1993-09-14 | 1995-03-31 | Nec Corp | Manufacture of mis type semiconductor integrated circuit device |
| JP2002368123A (en) * | 2001-06-07 | 2002-12-20 | Nec Corp | Production method for mos-type semiconductor device |
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