JPS62249486A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62249486A JPS62249486A JP9512486A JP9512486A JPS62249486A JP S62249486 A JPS62249486 A JP S62249486A JP 9512486 A JP9512486 A JP 9512486A JP 9512486 A JP9512486 A JP 9512486A JP S62249486 A JPS62249486 A JP S62249486A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- resist
- type
- gate
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 17
- 230000000694 effects Effects 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 230000005669 field effect Effects 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に関し、特に、ゲー
ト電極の仕事関数を変丸る（ Ｖ ａｒｉａｂｌｅＷｏ
ｒｋｆｕｎｃｔｉｏｎ Ｇａｔｅ：以下ＶＷＧと称す
）絶縁膜ゲー１−（ＭＯＳ）電界効果半導体装置の製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, in particular, a method for manufacturing a gate electrode with a variable rounded work function.
The present invention relates to a method for manufacturing a rkfunction gate (hereinafter referred to as VWG) insulating film gate (MOS) field effect semiconductor device.
第２図（ａ）〜（ｃ）は従来のこの種の半導体装置の製
造方法の工程断面図を示すものである。まず、第２図（
ａ）に示すように、ｐ型シリコン基板１にゲート絶縁膜
２およびレジスト４をマスクにしてｎ型半導体からなる
ゲート電極３を形成し、次に第２図（ｂ）に示すように
、このデー１−電極３をマスクにして、ｎ型不純物■を
イオン注入することにより、ソース・ドレイン領域５を
形成する。以下、絶縁膜６を形成し、所定個所にコンク
クトホールを開孔し、Ａｌ配線７を形成して素子が完成
ずろ。FIGS. 2(a) to 2(c) show process cross-sectional views of a conventional method for manufacturing this type of semiconductor device. First, Figure 2 (
As shown in a), a gate electrode 3 made of an n-type semiconductor is formed on a p-type silicon substrate 1 using a gate insulating film 2 and a resist 4 as a mask, and then as shown in FIG. Source/drain regions 5 are formed by ion-implanting an n-type impurity (2) using the electrode 3 as a mask. Thereafter, an insulating film 6 is formed, concrete holes are opened at predetermined locations, and Al interconnections 7 are formed to complete the device.
従来のゲー１へ電極３は仕事関数が一定であったので、
チャネル長が短くなると、短チヤネル効果を抑えるため
にゲート電極３としてｎ型半導体電極を用い、表面チャ
ネル形にしていた。しかし、ｎ型半導体電極を用いた方
が埋め込みチャネルのｔ二め、移動度が向上することが
知られている。Since the work function of electrode 3 to the conventional gate 1 was constant,
When the channel length becomes short, an n-type semiconductor electrode is used as the gate electrode 3 to suppress the short channel effect, resulting in a surface channel type. However, it is known that the use of an n-type semiconductor electrode improves the mobility of the buried channel.
この発明は、上記のような問題点を解消するためになさ
れたもので、ゲート電極の一部に不純物をイオン注入し
、仕事関数を変えることによって動作速度の高速化を図
った半導体装置の製造方法を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and it is possible to manufacture a semiconductor device in which the operation speed is increased by implanting impurity ions into a part of the gate electrode and changing the work function. The purpose is to obtain a method.
この発明に係る半導体装置の製造方法は、第１導電形の
シリコン基板上にゲート絶縁膜を形成する工程、ゲーＩ
・絶縁膜の上にデーｌ−電極となる半導体層を形成する
工程、半導体層のゲート電極相当部分のみにしＪストを
残す工程、レジスｌ−をマスクに（）で半導体層をエツ
チングしてゲー）・’Ｚ ｔ’Ｂを形成する工程、ゲー
ト電極をマスクにして第２導電形の不純物をイオン注入
し、ソース・ドし・イン領域を形成する工程、シリコン
基板上に絶縁１嘆を形成する工程、ゲート電極の一部お
よびソース・ドレイン領域のコンタクＩ・部のみを開孔
する工程。A method for manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a silicon substrate of a first conductivity type, a step of forming a gate insulating film on a silicon substrate of a first conductivity type,
・The process of forming a semiconductor layer that will become the D-electrode on the insulating film, the process of leaving only the portion of the semiconductor layer corresponding to the gate electrode and leaving the J-stack, and etching the semiconductor layer with () using the resist L- as a mask to form the gate electrode. )・Process of forming 'Z t'B, process of ion-implanting second conductivity type impurities using the gate electrode as a mask to form source, dome, and in regions, and forming an insulating layer on the silicon substrate. A step of opening only a portion of the gate electrode and the contact I portion of the source/drain region.
ゲート電極の一部ｔ！けを選択的にレジストを除去する
工程、レジストをマスクにしてソース・ドレイン領域間
に埋め込み汗ヤ不ノ「を形成したい部分に対応するデー
１−電極部分の仕事関数を変えろために不純物をイオン
注入する工程、レジストを除去した後、ゲート電極のコ
ンタクトおよびソース・ドし・イン領域のコンタクト部
に電極配線する工程からなるものである。Part of the gate electrode t! In the step of selectively removing the resist, using the resist as a mask, impurities are ionized to change the work function of the D1-electrode portion corresponding to the area where the oxide layer is to be formed between the source and drain regions. This process consists of the step of implanting, and after removing the resist, the step of wiring electrodes to the contacts of the gate electrode and the contact portions of the source/drain/in regions.
この発明においては、ゲート電極の一部に不純物をイオ
ン注入することによってゲート電極の一部の仕事関数を
変え、ソース・ドレイン近傍のゲート電極は、イオン注
入領域の導電型と異ならしめて表面チャネルにすること
で、短チヤネル効果が抑んられ、それ以外の部分を埋め
込みチャネルにすることによす、動作速度の高速化が図
れる。In this invention, the work function of a part of the gate electrode is changed by ion-implanting an impurity into a part of the gate electrode, and the conductivity type of the gate electrode near the source/drain is made to be different from that of the ion-implanted region, so that it becomes a surface channel. By doing so, the short channel effect can be suppressed, and the operation speed can be increased by making the other portions into buried channels.
第１図（ａ）〜（ｄ）はこの発明の半導体装置の製造方
法の一実施例を説明するだめの工程断面図である。なお
、図中、第２図と同一符号は同一または相当部分を示す
。FIGS. 1(a) to 1(d) are process cross-sectional views for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention. In addition, in the figure, the same reference numerals as in FIG. 2 indicate the same or corresponding parts.
まず、第１図（ａ）に示すようにｐ型シリコン基板１に
ゲート絶縁膜２およびゲート電極３となる半導体層を形
成（７、ゲート電極相当部分のみにレジスト４を残す３
２次に、第１図（ｂ）に示すようにし・レスト４をマス
クにして、不純物（例えＬＬ’Ａｓ）■を５０ ＫｅＶ
、４ Ｘ ｉ Ｏ”ｅｍ−”で注入し、ソース・ドレイ
ン領域５を形成する。次に、第１図（ｃ）に示すように
絶縁膜６を堆積し、ソース・ドレインのコンククト窓お
よびゲート電極３のうちイオン注入領域、すなわちｐ型
半導体ゲート電極にしたい領域にコンタクト窓を開孔す
る。そして、ｐ型半導体ゲート電極にしたい領域を除い
て、レジスト８で覆い、不純物（例えばＢ）ＩＩを３０
ＫｅＶ。First, as shown in FIG. 1(a), a semiconductor layer that will become a gate insulating film 2 and a gate electrode 3 is formed on a p-type silicon substrate 1 (7, a resist 4 is left only in the portion corresponding to the gate electrode).
2. Next, as shown in FIG. 1(b), using the rest 4 as a mask, the impurity (for example LL'As) is heated to 50 KeV.
, 4XiO"em-" to form source/drain regions 5. Next, as shown in FIG. 1(c), an insulating film 6 is deposited, and contact windows are opened in the source/drain contact windows and in the ion implantation region of the gate electrode 3, that is, in the region desired to be a p-type semiconductor gate electrode. make a hole Then, except for the region where the p-type semiconductor gate electrode is desired, it is covered with resist 8, and an impurity (for example, B) II is added at 30%
KeV.
４ Ｘ １０ ”ｃｍ−”で注入し、ゲート電極３の一
部をｐ型ポリシリコンゲー１−９にし、ｖＷＧ構造が形
成されろ。最後に、第１図（ｄ）に示すようにレジスト
８を除去後、Ａｌ配線７を施して素子が完成する。A portion of the gate electrode 3 is made into a p-type polysilicon gate 1-9 by implantation of 4.times.10 "cm-" to form a vWG structure. Finally, as shown in FIG. 1(d), after removing the resist 8, Al wiring 7 is applied to complete the device.
なお、上記実施例では、ｎチャネル絶縁ゲート（ＭＯＳ
）電界効果半導体装置の製造方法について述べたが、も
ちろんｐ型基板をｎ型基板にし、ソース・ドレイン等に
注入するｎ型不純物をｐ型不純物にし、さらに、ゲート
電極３の一部のみに注入するｐ型不純物をｎ型不純物に
することにより、ｐチャネル絶縁ゲート（ＭＯＳ）電界
効果半導体装置にも適用可能である。Note that in the above embodiment, an n-channel insulated gate (MOS
) The method for manufacturing a field effect semiconductor device has been described, but of course, the p-type substrate is replaced with an n-type substrate, the n-type impurities implanted into the source/drain, etc. are replaced with p-type impurities, and furthermore, only a part of the gate electrode 3 is implanted. By replacing the p-type impurity with an n-type impurity, the present invention can also be applied to a p-channel insulated gate (MOS) field effect semiconductor device.
この発明は以上説明したとおり、ゲート電極の一部に不
純物をイオン注入してその部分の導電型をゲート電極の
他の部分の導電型と異ならしめるようにしたので、短チ
ヤネル効果を抑えた動作速度の速い半導体装置が得られ
る効果がある。As explained above, in this invention, impurity ions are implanted into a part of the gate electrode to make the conductivity type of that part different from the conductivity type of other parts of the gate electrode, so that the short channel effect can be suppressed. This has the effect of providing a high-speed semiconductor device.
第１図（ａ１〜（ｄ）はこの発明の一実施例の各工程で
の状態を示す断面図、第２図（ａ）〜（ｅ）は従来のＭ
ＯＳＦＥＴを説明するための断面図である。
図において、１はｐ型シリコン基板、２はゲート絶縁膜
、３はゲート電極、４，８はレンスト、５はソース・ド
レイン領域、６は絶縁膜、７はＡｔ’配線、９は不純物
注入により形成されたｐ型ボリンリコンゲ−１・である
。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
１１１１１１）・
１１ＮＩＪ ［“
第１図（ｄ）
第２図
１ｊｌｊｌ ト“
手続補正書（自発）
昭和 年 月 日
１、事件の表示 特願昭６１〜９５１２４号２、発
明の名称 半導体装置の製造方法３、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目２番３号
名 称 （６０１）三菱電機株式会社代表者 志 岐
守 哉
４、代理人
住 所 東京都千代田区丸の内二丁目２番３号５
、補正の対像
明細書の発明の詳細な説明の欄２図面の簡単な説明の欄
および図面
６、補正の内容
（１１明細書第２頁１６行の「ゲート絶縁膜２およびレ
ジスト４をマスクにして」を、「ゲーＩ・絶縁膜２およ
びゲート電極３となる半導体層を形成し、レジスト４を
マスクにして」と補正する。
（２）同じく第５頁１１行の「半導体層」を、「ｎ型半
導体層」と補正する。
（３） 同じく第５頁１２行の「・を残す。次に、」
を、下記のように補正する。
「・を残す。このレジスト４をマスクにしてゲート電極
３を形成する。次に、」
（４）同じ（第５頁１５行の「次に、」を、「次に、レ
ジス１−４を除去後、」と補正する−９（５）同じく第
５頁１８行、１９〜２０行の「ｐ型半導体ゲート電極」
を、それぞれ「ｐ型ゲート電極」と補正する。
（６）同じく第６頁３行の「ｐ型ポリシリコンゲ−１−
」を、「ｐ型ゲート電極」と補正する。
（７）同じく第７頁８〜９行の「ｐ型ポリシリコンゲー
ト」を、「ｐ型ゲート電極Ｊと補正する。
（８） 第１図（ｂ）、（Ｃ）を別紙のように補正す
る。
以 上FIGS. 1(a1 to d) are cross-sectional views showing the state at each step of an embodiment of the present invention, and FIGS. 2(a) to (e) are sectional views of the conventional M
FIG. 2 is a cross-sectional view for explaining an OSFET. In the figure, 1 is a p-type silicon substrate, 2 is a gate insulating film, 3 is a gate electrode, 4 and 8 are resists, 5 is a source/drain region, 6 is an insulating film, 7 is an At' wiring, and 9 is an impurity implanted The formed p-type borinliconge-1. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Figure 1 111111) / 11NIJ [“Figure 1 (d) Figure 2 1jljl t” Procedural amendment (voluntary) Showa year, month, day 1, case description patent application No. 61-95124 2, Title of the invention Method for manufacturing semiconductor devices 3, Relationship to the amended person's case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Representative of Mitsubishi Electric Corporation Person: Moriya Shiki 4, Agent Address: 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, Detailed explanation column 2 of the detailed description of the invention column 2 of the brief explanation of the drawings column of the corresponding specification of the amendment, Drawing 6, Contents of the amendment (11 "Mask the gate insulating film 2 and the resist 4" on page 2, line 16 of the specification) (2) Correct "semiconductor layer" on page 5, line 11. , correct it as "n-type semiconductor layer." (3) Similarly, on page 5, line 12, leave ". Next."
Correct as shown below. ``Leave ・.Use this resist 4 as a mask to form the gate electrode 3. Next'' (4) Same (Page 5, line 15, ``Next'', ``Next, resist 1-4 is formed.'') -9(5) "p-type semiconductor gate electrode" on page 5, line 18, line 19-20.
are respectively corrected as "p-type gate electrodes". (6) Also on page 6, line 3, “p-type polysilicon game 1-
" is corrected to "p-type gate electrode." (7) Similarly, correct “p-type polysilicon gate” in lines 8-9 of page 7 to “p-type gate electrode J.” (8) Correct Fig. 1 (b) and (C) as shown in the attached sheet. That's it.
Claims (1)
工程、前記ゲート絶縁膜の上にゲート電極となる半導体
層を形成する工程、前記半導体層のゲート電極相当部分
のみにレジストを残す工程、前記レジストをマスクにし
て前記半導体層をエッチングしてゲート電極を形成する
工程、前記ゲート電極をマスクとして第２導電形の不純
物をイオン注入しソース・ドレイン領域を形成する工程
、前記シリコン基板上に絶縁膜を形成する工程、前記ゲ
ート電極の一部およびソース・ドレイン領域のコンタク
ト部のみを開孔する工程、前記ゲート電極の一部だけを
選択的にレジストを除去する工程、前記レジストをマス
クにして前記ソース・ドレイン領域間に埋め込みチャネ
ルを形成したい部分に対応する前記ゲート電極部分の仕
事関数を変えるために不純物をイオン注入する工程、前
記レジストを除去した後、前記ゲート電極のコンタクト
およびソース・ドレイン領域のコンタクト部に電極配線
する工程を含むことを特徴とする半導体装置の製造方法
。a step of forming a gate insulating film on a silicon substrate of a first conductivity type; a step of forming a semiconductor layer to become a gate electrode on the gate insulating film; a step of leaving a resist only in a portion of the semiconductor layer corresponding to the gate electrode; a step of etching the semiconductor layer using the resist as a mask to form a gate electrode; a step of ion-implanting impurities of a second conductivity type using the gate electrode as a mask to form source/drain regions; a step of forming an insulating film, a step of opening only a portion of the gate electrode and a contact portion of the source/drain region, a step of selectively removing the resist from only a portion of the gate electrode, and a step of using the resist as a mask. a step of ion-implanting an impurity to change the work function of the gate electrode portion corresponding to a portion where a buried channel is to be formed between the source and drain regions; 1. A method of manufacturing a semiconductor device, comprising the step of wiring an electrode to a contact portion of a drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9512486A JPS62249486A (en) | 1986-04-22 | 1986-04-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9512486A JPS62249486A (en) | 1986-04-22 | 1986-04-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62249486A true JPS62249486A (en) | 1987-10-30 |
Family
ID=14129079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9512486A Pending JPS62249486A (en) | 1986-04-22 | 1986-04-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62249486A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7781288B2 (en) * | 2007-02-21 | 2010-08-24 | International Business Machines Corporation | Semiconductor structure including gate electrode having laterally variable work function |
-
1986
- 1986-04-22 JP JP9512486A patent/JPS62249486A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7781288B2 (en) * | 2007-02-21 | 2010-08-24 | International Business Machines Corporation | Semiconductor structure including gate electrode having laterally variable work function |
| US7989900B2 (en) * | 2007-02-21 | 2011-08-02 | International Business Machines Corporation | Semiconductor structure including gate electrode having laterally variable work function |
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