JP7416891B2 - 半導体構造及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 54
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 59
- 239000002184 metal Substances 0.000 claims description 59
- 239000000758 substrate Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 14
- 239000010410 layer Substances 0.000 description 231
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009510 drug design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
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- H01L23/528—Geometry or layout of the interconnection structure
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Photovoltaic Devices (AREA)
Description
本発明は半導体構造のグランドメタル層を第一グランド層及び第二グランド層に分けることで、回路層を誘電体層に直接設置し、1P2Mの構造を達成し、プロセスの複雑さを低下させ、半導体構造の体積を減少させている。また、第二グランド層も誘電体層に設置し、回路層が相互の電磁波により干渉するのを遮断し、半導体構造の電磁シールド能力を高めている。
110 基板
111 表面
112 導体パッド
120 誘電体層
121 開口部
130 接合層
131 第一接合部
132 第二接合部
140 グランドメタル層
141 第一グランド層
142 第二グランド層
150 回路層
PR フォトレジスト層パターン
O 孔部
M メタル層
H1 第一水平高さ
H2 第二水平高さ
200 半導体構造
210 基板
211 表面
220 導体パッド
230 第一誘電体層
240 第一接合層
241 第一接合部
242 第二接合部
250 第一回路層
260 グランドメタル層
270 第二誘電体層
280 第二接合層
290 第二回路層
10 半導体構造の製造方法
11 基板を提供する
12 誘電体層を形成する
13 接合層を形成する
14 フォトレジスト層パターンを形成する
15 メタル層を形成する
16 フォトレジスト層パターンを剥離する
17 接合層をエッチングする
Claims (10)
- 表面を有している基板と、
前記表面に設置され、複数の開口部を有し、各前記開口部からは前記表面が露出している誘電体層と、
前記誘電体層に設置されている接合層であって、前記接合層の第一接合部は前記開口部中に位置し、且つ前記第一接合部は前記表面に接続され、前記接合層の第二接合部は前記誘電体層に接続されている前記接合層と、
前記接合層に設置されているグランドメタル層であって、前記グランドメタル層の第一グランド層は前記接合層の前記第一接合部に接続され、前記グランドメタル層の第二グランド層は前記接合層の前記第二接合部に接続されている前記グランドメタル層と、
前記接合層の前記第二接合部に各々設置されている複数の回路層であって、隣接する2つの前記回路層の間には1つの前記第二グランド層を有している複数の前記回路層と、を備えていることを特徴とする半導体構造。 - 前記誘電体層、前記第一接合部及び前記第一グランド層は同じ第一水平高さに位置し、前記第二接合部、前記第二グランド層及び前記回路層は同じ第二水平高さに位置し、前記第二水平高さは前記第一水平高さより高いことを特徴とする請求項1に記載の半導体構造。
- 前記基板は複数の導体パッドを有し、前記導体パッドは前記基板の前記表面に設置され、前記誘電体層の前記開口部からは各前記導体パッドが露出し、前記接合層は前記開口部を介して前記導体パッドに接続され、各前記回路層は前記接合層を介して各前記導体パッドに接続されていることを特徴とする請求項2に記載の半導体構造。
- 前記第一グランド層は前記接合層を介して前記第二グランド層に接続されていることを特徴とする請求項2に記載の半導体構造。
- 前記グランドメタル層は如何なる電流信号も通過させないことを特徴とする請求項4に記載の半導体構造。
- 半導体構造の製造方法であって、
表面を有している基板を提供する工程と、
前記基板の前記表面に誘電体層を形成する工程であって、前記誘電体層は複数の開口部を有し、前記開口部からは前記表面が露出している工程と、
前記誘電体層に接合層を形成する工程であって、部分的な前記接合層が前記開口部中に位置していると共に前記表面に接続され、部分的な前記接合層が前記誘電体層に接続されている工程と、
前記接合層にフォトレジスト層パターンを形成する工程であって、前記フォトレジスト層パターンは複数の孔部を有し、前記孔部からは前記接合層が露出している工程と、
前記フォトレジスト層パターンの前記孔部中にメタル層を形成する工程であって、前記メタル層は前記孔部から露出している前記接合層に接続され、且つ部分的な前記メタル層が前記誘電体層の前記開口部中に位置している工程と、
前記フォトレジスト層パターンに被覆された前記接合層を露出するように前記フォトレジスト層パターンを剥離する工程と、
前記メタル層をマスクとして前記接合層をエッチングし、前記接合層に第一接合部及び第二接合部を形成し、前記第一接合部は前記開口部に位置し、且つ前記第一接合部を前記表面に接続し、前記第二接合部を前記誘電体層に接続し、前記メタル層はグランドメタル層及び複数の回路層から構成され、前記グランドメタル層の第一グランド層を前記接合層の前記第一接合部に接続し、前記グランドメタル層の第二グランド層を前記接合層の前記第二接合部に接続し、各前記回路層は前記接合層の前記第二接合部に設置し、且つ隣接する2つの前記回路層の間には1つの前記第二グランド層を有している工程と、を含むことを特徴とする半導体構造の製造方法。 - 前記誘電体層、前記第一接合部及び前記第一グランド層は同じ第一水平高さに位置し、前記第二接合部、前記第二グランド層及び前記回路層は同じ第二水平高さに位置し、前記第二水平高さは前記第一水平高さより高いことを特徴とする請求項6に記載の半導体構造の製造方法。
- 前記基板は複数の導体パッドを有し、前記導体パッドは前記基板の前記表面に設置され、前記誘電体層の前記開口部からは各前記導体パッドが露出し、前記接合層は前記開口部を介して前記導体パッドに接続され、各前記回路層が前記接合層を介して各前記導体パッドに接続されていることを特徴とする請求項7に記載の半導体構造の製造方法。
- 前記第一グランド層は前記接合層を介して前記第二グランド層に接続されていることを特徴とする請求項7に記載の半導体構造の製造方法。
- 前記グランドメタル層は如何なる電流信号も通過させないことを特徴とする請求項9に記載の半導体構造の製造方法。
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TW110144293 | 2021-11-26 | ||
TW110144293A TWI805099B (zh) | 2021-11-26 | 2021-11-26 | 半導體結構及其製造方法 |
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JP2023079175A JP2023079175A (ja) | 2023-06-07 |
JP7416891B2 true JP7416891B2 (ja) | 2024-01-17 |
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US (1) | US20230170301A1 (ja) |
JP (1) | JP7416891B2 (ja) |
KR (1) | KR20230078515A (ja) |
CN (1) | CN116190352A (ja) |
TW (1) | TWI805099B (ja) |
Citations (6)
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JP2007134359A (ja) | 2005-11-08 | 2007-05-31 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP2010074027A (ja) | 2008-09-22 | 2010-04-02 | Nippon Telegr & Teleph Corp <Ntt> | Fetスイッチ |
JP2013251520A (ja) | 2012-05-30 | 2013-12-12 | Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co Ltd | 一体的ファラデーシールドを備えた多層電子構造体 |
US20190131245A1 (en) | 2017-10-30 | 2019-05-02 | Qorvo Us, Inc. | Transmission line structure with high q factor and low insertion loss for millimeter wave applications |
CN111785700A (zh) | 2020-09-07 | 2020-10-16 | 成都知融科技股份有限公司 | 一种超宽带互连结构 |
KR20210061186A (ko) | 2019-11-19 | 2021-05-27 | 대구대학교 산학협력단 | 동일평면 도파관 소자를 이용한 d-(+)-포도당 용액의 농도변화에 따른 검출 및 전기적 특성 분석방법 |
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US8178953B2 (en) * | 2008-09-30 | 2012-05-15 | Infineon Technologies Ag | On-chip RF shields with front side redistribution lines |
US10475736B2 (en) * | 2017-09-28 | 2019-11-12 | Intel Corporation | Via architecture for increased density interface |
KR101942741B1 (ko) * | 2017-10-20 | 2019-01-28 | 삼성전기 주식회사 | 반도체 패키지 |
WO2019133015A1 (en) * | 2017-12-30 | 2019-07-04 | Intel Corporation | Zero-misalignment two-via structures |
KR20200089970A (ko) * | 2019-01-18 | 2020-07-28 | 삼성전자주식회사 | 집적회로 칩과 이를 포함하는 집적회로 패키지 및 디스플레이 장치 |
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- 2021-11-26 TW TW110144293A patent/TWI805099B/zh active
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- 2022-10-25 US US17/972,648 patent/US20230170301A1/en active Pending
- 2022-10-28 JP JP2022173354A patent/JP7416891B2/ja active Active
- 2022-10-28 CN CN202211341924.9A patent/CN116190352A/zh active Pending
- 2022-10-31 KR KR1020220142401A patent/KR20230078515A/ko unknown
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007134359A (ja) | 2005-11-08 | 2007-05-31 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP2010074027A (ja) | 2008-09-22 | 2010-04-02 | Nippon Telegr & Teleph Corp <Ntt> | Fetスイッチ |
JP2013251520A (ja) | 2012-05-30 | 2013-12-12 | Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co Ltd | 一体的ファラデーシールドを備えた多層電子構造体 |
US20190131245A1 (en) | 2017-10-30 | 2019-05-02 | Qorvo Us, Inc. | Transmission line structure with high q factor and low insertion loss for millimeter wave applications |
KR20210061186A (ko) | 2019-11-19 | 2021-05-27 | 대구대학교 산학협력단 | 동일평면 도파관 소자를 이용한 d-(+)-포도당 용액의 농도변화에 따른 검출 및 전기적 특성 분석방법 |
CN111785700A (zh) | 2020-09-07 | 2020-10-16 | 成都知融科技股份有限公司 | 一种超宽带互连结构 |
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TW202322334A (zh) | 2023-06-01 |
TWI805099B (zh) | 2023-06-11 |
US20230170301A1 (en) | 2023-06-01 |
CN116190352A (zh) | 2023-05-30 |
JP2023079175A (ja) | 2023-06-07 |
KR20230078515A (ko) | 2023-06-02 |
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