TWI483375B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI483375B
TWI483375B TW101103103A TW101103103A TWI483375B TW I483375 B TWI483375 B TW I483375B TW 101103103 A TW101103103 A TW 101103103A TW 101103103 A TW101103103 A TW 101103103A TW I483375 B TWI483375 B TW I483375B
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Taiwan
Prior art keywords
layer
circuit substrate
interconnect
interconnects
interconnect layer
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TW101103103A
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English (en)
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TW201236132A (en
Inventor
Keiju Yamada
Masaaki Ishida
Original Assignee
Toshiba Kk
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Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW201236132A publication Critical patent/TW201236132A/zh
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Publication of TWI483375B publication Critical patent/TWI483375B/zh

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    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Description

半導體裝置
本文所描述之實施例大體係關於一種半導體裝置。
本申請案係基於且主張2011年1月31日申請之先前日本專利申請案第2011-019273號之權利；該案之全文以引用之方式併入本文中。
一般而言，當電流流經半導體元件或周邊電路時，在電路周圍引發電場及磁場而產生不必要之電磁雜訊。不必要之電磁雜訊影響其他電路、元件等之操作。作為一實例，存在以下情況：自半導體裝置發射之電磁雜訊入射於天線上以引起對無線電波接收之干擾，該半導體裝置安裝於諸如蜂巢式電話之行動通信設備中。
為了屏蔽此電磁雜訊且保護半導體元件，提供了一種屏蔽板覆蓋電路模組之方法。然而，藉由屏蔽板覆蓋電路模組之方法可能難以小型化電路模組。
相比而言，存在一種半導體裝置(半導體封裝)，其中屏蔽膜形成於半導體元件本身之外周邊上。藉由將此半導體裝置安裝於電路模組中，可將電路模組小型化。半導體元件需要越高速之操作，則需要高度可靠之半導體裝置屏蔽越多電磁雜訊。
問題在於獲得屏蔽更多電磁雜訊之高度可靠之半導體裝置。
一般而言，根據一個實施例，一種半導體裝置包括一電路基板、一半導體元件、一密封樹脂層及一導電屏蔽層。該電路基板包括：一絕緣層；形成第一互連層之複數個互連件，該第一互連層提供於該絕緣層之一上表面側上；形成第二互連層之複數個互連件，該第二互連層提供於該絕緣層之一下表面側上；及複數個導通孔，該等導通孔自該絕緣層之該上表面穿透至該下表面。該半導體元件安裝於該電路基板之該上表面側上。該密封樹脂層提供於該電路基板之該上表面上且密封該半導體元件。該導電屏蔽層覆蓋該密封樹脂層及該電路基板之一末端部分之部分。複數個導通孔中之任一者與該導電屏蔽層電性連接。形成該等第二互連層之該複數個互連件中之任一者電性連接至能夠變成一接地電位之一外部連接端子。
一般而言，根據另一實施例，一種半導體裝置包括一電路基板、一半導體元件、一密封樹脂層及一導電屏蔽層。該電路基板包括：一絕緣層；形成第一互連層之複數個互連件，該第一互連層提供於該絕緣層之一上表面側上；及形成第二互連層之複數個互連件，該第二互連層提供於該絕緣層之一下表面側上。該半導體元件安裝於該電路基板之該上表面側上。該密封樹脂層提供於該電路基板之該上表面上且密封該半導體元件。該導電屏蔽層覆蓋該密封樹脂層及該電路基板之一末端部分之部分。形成該等第二互連層之該複數個互連件不與該導電屏蔽層接觸，電性連接至形成該等第一互連層之該複數個互連件中之任一者，且 拉伸至該電路基板之一末端以便曝露於該電路基板之一側表面處。
在下文，參考圖式描述實施例。在以下描述中，相同組件標有相同元件符號，且一旦完成描述，則適當地省略組件之描述。可適當合併下文描述之實施例。
第一實施例
圖1為用於描述根據第一實施例之半導體裝置之概覽的示意橫截面圖。
圖1展示根據第一實施例之半導體裝置1以及進一步展示其上安裝半導體裝置1之安裝基板100。
半導體裝置1為FBGA(細節距球狀柵格陣列)半導體封裝。半導體裝置1包括電路基板10。電路基板10亦稱為***式基板。電路基板10包括：絕緣層11；形成第一互連層之複數個互連件12，第一互連層提供於絕緣層11之上表面側上之外周邊上；及形成第二互連層之複數個互連件13，第二互連層提供於絕緣層11之下表面側上。電路基板10進一步包括複數個導通孔14，複數個導通孔14自絕緣層11之上表面(第一主要表面)穿透至下表面(第二主要表面)。覆蓋第一互連層12之部分之阻焊層15形成於電路基板10之上表面上。覆蓋第二互連層13之部分之阻焊層16形成於電路基板10之下表面上。形成第二互連層之複數個互連件13中之每一者為平台形互連層。外部連接端子17(其為焊球)連接至形成第二互連層之複數個互連件13中之每一者。延長 線19自外周邊之外部連接端子17延伸至電路基板10之外側。延長線19連接至曝露於電路基板10之側表面10w之導通孔14。延長線19為連接外周邊之外部連接端子17與最接近外周邊之外部連接端子17的導通孔14的連接線。外部連接端子17連接至安裝基板100之上表面側上提供之互連層101。
半導體元件20安裝於電路基板10之上表面側。電線(接線)21之一個末端連接至半導體元件20之上表面。電線21之另一末端連接至第一互連層12。電線21為導電部件，且電性連接形成第一互連層之複數個互連件12中之至少一者與半導體元件之表面上提供之電極(未圖示)。
半導體元件20之外周邊及電線21藉由電路基板10之上表面側上提供之密封樹脂層30密封。晶粒結著材料22形成於半導體元件20與電路基板10之間的空間中。密封樹脂層30及電路基板10之側表面10w之部分藉由導電屏蔽層40覆蓋。導電屏蔽層40連接至提供於電路基板10之側表面(外端)10w之導通孔14。曝露於電路基板10之側表面10w之導通孔中之至少一者可經設定為接地(GND)電位。因此，半導體元件20之外周邊、電線21、電路基板10之上表面側及覆蓋電路基板10之側表面10w之部分的導電屏蔽層40之電位可經設定成接地(GND)電位。
舉例而言，半導體元件20為諸如快閃記憶體及DRAM之記憶體元件、諸如微處理器之運算元件、信號處理元件或其類似者。舉例而言，電線21之材料為金(Au)、鋁(Al)、 銅(Cu)及/或其類似者。第一互連層12及第二互連層13為銅(Cu)箔、含銀(Ag)及/或銅(Cu)之導電膏或其類似者，且必要時表面鍍有鎳(Ni)、金(Au)及/或其類似者。舉例而言，導通孔14為柱狀電極。導通孔14可為所有組件皆由導電材料製成之柱狀電極，或可具有以下組態：除了柱狀電極外，亦包括為圓柱形狀之環狀圓柱形電極及嵌入環狀圓柱形電極之空室中之樹脂或其類似者。導通孔14之材料為銅(Cu)、鎢(W)及/或其類似者。
導電屏蔽層40較佳由具有儘可能低之電阻率之材料製成，以便屏蔽自半導體元件20發射之高頻雜訊。舉例而言，選擇銀(Ag)、銅(Cu)、鎳(Ni)、鋁(Al)及/或其類似者作為導電屏蔽層40之材料。更具體而言，導電屏蔽層40為具有固化之銀(Ag)膏的含銀(Ag)層，且將導電屏蔽層40之薄層電阻調整至0.1(Ω/□)或少於0.1。導電屏蔽層40具有幾μm至數10 μm(微米)之厚度，較佳為1至90 μm。
圖2A及2B為根據第一實施例之半導體裝置之示意平面圖，其中圖2A為電路基板之上表面側之示意平面圖，且圖2B為電路基板之下表面側之示意平面圖。當自垂直於絕緣層11之上表面(或下表面)之方向查看時，圖2A及2B為電路基板10之視圖。
如圖2A中所展示，複數個導通孔14提供於電路基板10之上表面側上。複數個導通孔14自絕緣層11之上表面穿透至下表面。由元件符號23環繞之矩形區域為用於半導體元件20之元件安裝區域23。導通孔14以複數形式安置於元件安 裝區域23中且/或於元件安裝區域23外部。形成第一互連層之複數個互連件12提供於元件安裝區域23外部。延長線18自元件安裝區域23中之導通孔14提供至第一互連層12。延長線18為半導體元件20之信號線、接地互連件等。延長線18為銅(Cu)箔、含銀(Ag)及/或銅(Cu)之導電膏或其類似者。
如圖2B中所展示，複數個外部連接端子17以垂直列及水平列提供於電路基板10之下表面側。複數個外部連接端子17中之每一者經由導通孔14電性連接至上表面側上之延長線18。亦即，外部連接端子17經由第二互連層13、導通孔14及延長線18電性連接至第一互連層12。儘管圖2B中未展示圖1中所說明之第二互連層13，但第二互連層13實際上與外部連接端子17接觸(參見圖1)。
在半導體裝置1中，由複數個外部連接端子17組成之群(其數目小於複數個外部連接端子17)可變成接地電位。舉例而言，將半導體裝置1安裝於安裝基板100上之後，外部連接端子17中之一些借助於提供於安裝基板100中之接地互連件變成接地電位。在圖式中，可變成接地電位之外部連接端子用元件符號17g表示，且被稱為外部連接端子17g。換言之，由形成第二互連層之複數個互連件13組成之群(其數目小於形成第二互連層之複數個互連件13)可變成接地電位。此外，與外部連接端子17g接觸之第二互連層13可變成接地電位。
在圖2B中，變成接地電位之外部連接端子17g(或與外部 連接端子17g接觸之第二互連層13)分別定位於元件安裝區域23之四個轉角。換言之，外部連接端子17g(或與外部連接端子17g接觸之第二互連層13)中之每一者定位於半導體元件之轉角。
在電路基板10中，由複數個導通孔14組成之群(其數目小於電路基板10之整個主要表面上提供之複數個導通孔14)經安置以便曝露於電路基板10之側表面10w。安置於側表面10w之複數個導通孔14中之每一者藉由用於製造程序中之切割刀片而於電路基板10之側表面處切割，且具有曝露表面。在半導體裝置1中，安置於側表面10w之複數個導通孔14中之每一者的曝露表面與導電屏蔽層40連接。
延長線19自變成接地電位之外部連接端子17g(或與外部連接端子17g接觸之第二互連層13)延伸。延長線19為銅(Cu)箔、含銀(Ag)及/或銅(Cu)之導電膏或其類似者。
延長線19進一步連接至安置於側表面10w之複數個導通孔14中之一些。在圖2B中，連接至延長線19之導通孔用元件符號14g表示，且被稱為導通孔14g。因此，安置於電路基板10之側表面10w之複數個導通孔14g可變成接地電位。
在半導體裝置1中，外部連接端子17g(或與外部連接端子17g接觸之第二互連層13)中之每一者電性連接至複數個導通孔14g中之每一者，複數個導通孔14g進一步為安置於側表面10w之導通孔14的部分；因此，導電屏蔽層40可變成接地電位。亦即，在半導體裝置1中，導電屏蔽層40與接地電位之間的觸點以複數形式提供。供應接地電位至導 通孔14g之延長線19可提供於電路基板10之上表面側上。
變成接地電位之外部連接端子17g(或與外部連接端子17g接觸之第二互連層13)之數目及配置不限於上文所描述之實例。下文描述另一實例。
圖3A及3B為根據第一實施例之半導體裝置之示意平面圖，其中圖3A為第一修改實例之電路基板之示意平面圖，且圖3B為第二修改實例之電路基板之示意平面圖。圖3A及3B說明電路基板10之下表面側。
在圖3A中所展示之電路基板10中，變成接地電位之外部連接端子17g(或與外部連接端子17g接觸之第二互連層13)中之每一者定位於元件安裝區域23之一個側面之中心部分中。換言之，外部連接端子17g(或與外部連接端子17g接觸之第二互連層13)中之每一者定位於半導體元件20之相鄰轉角之間。
延長線19自變成接地電位之外部連接端子17g(或與外部連接端子17g接觸之第二互連層13)延伸。延長線19進一步連接至安置於側表面10w之複數個導通孔14g。導通孔14g連接至導電屏蔽層40。
在圖3B中所展示之電路基板10中，組合圖2B之組態及圖3A之組態。亦即，變成接地電位之外部連接端子17g(或與外部連接端子17g接觸之第二互連層13)中之每一者定位於半導體元件20之轉角處及/或於相鄰轉角之間。
相鄰外部連接端子17g(或與外部連接端子17g接觸之相鄰第二互連層13)之間的距離經調整為不大於自半導體元 件20等發射之電磁雜訊之波長的一半。
接下來描述用於半導體裝置1之製造程序。
圖4A至4D為用於描述根據第一實施例之半導體裝置之製造程序之示意橫截面圖。
首先，如圖4A中所展示，在碎裂之前形成半導體裝置1。在此階段，電路基板10處於切割前之狀態，且連接複數個半導體裝置1。
接著，將切割刀片90沿切割線DL***至電路基板10中。在此階段，執行所謂的半切割，且阻止切割刀片90到達電路基板10之下表面側。亦即，在切割線DL附近之導通孔14的深度方向上中途停止***切割刀片90，且導通孔14在電路基板10之深度方向上曝露藉由切割所獲得之切割面。此狀態在圖4B中展示。
導通孔14之切割面未必需要成為導通孔14之中心，且導通孔14之部分包括於切割面中。為了增加導通孔14與導電屏蔽層40之間的接觸面積，導通孔14之切割面較佳處於導通孔14之中心附近。
隨後固化密封樹脂層30，且接著如圖4C中所展示，將導電屏蔽層40安放於密封樹脂層30上。亦將導電屏蔽層40埋設於由半切割形成之凹座90h中。
舉例而言，藉由轉移法、網板印刷法、噴霧應用法、噴射分配法、噴墨法、霧劑法、無電極電鍍法、電解電鍍法、濺鍍法、蒸鍍法或其類似者來執行導電屏蔽層40之形成。
當導電屏蔽層40埋設於凹座90h中時，導電屏蔽層40與導通孔14之切割面接觸。之後，必要時固化導電屏蔽層40。
接下來，如圖4D中所展示，執行用於碎裂之切割以形成半導體裝置1。
現將描述半導體裝置1之效應。
圖5A及5B為用於描述對電磁雜訊之屏蔽效應之模擬結果。
圖5A之水平軸表示自半導體元件20等發出之雜訊頻率(MHz)，且垂直軸表示屏蔽效應(dB)。圖5A之線(1)至(4)分別為基於圖5B之圖案(1)至(4)之計算之模擬結果。
在圖案(1)中，一個外部連接端子17g以電氣連續性連接至導電屏蔽層40。亦即，導電屏蔽層40與接地電位接觸之位置的數目為一。
在圖案(2)中，除了圖案(1)之外，安置於半導體元件20之轉角(四個轉角)之其他外部連接端子17g以電氣連續性連接至導電屏蔽層40。亦即，導電屏蔽層40與接地電位接觸之位置的數目為五。
在圖案(3)中，除了圖案(1)之外，安置於半導體元件20之相鄰轉角之間的其他外部連接端子17g以電氣連續性連接至導電屏蔽層40。亦即，導電屏蔽層40與接地電位接觸之位置的數目為五。
在圖案(4)中，除了圖案(1)之外，安置於半導體元件20之轉角(四個轉角)及半導體元件20之相鄰轉角之間的其他 外部連接端子17g以電氣連續性連接至導電屏蔽層40。亦即，導電屏蔽層40與接地電位接觸之位置的數目為九。
在50 MHz至900 MHz之雜訊頻率範圍中，線(1)展現6 dB至9 dB，然而線(2)及(3)展現13 dB至14 dB之增值。此外，線(4)展現大約15 dB之增值。舉例而言，在雜訊頻率為最高的900 MHz處，(2)及(3)比(1)高大約6 dB，且(4)比(1)高大約8 dB。因此，屏蔽效應隨著導電屏蔽層40與接地電位接觸之位置數目增加而改良。
在半導體裝置1中，因安置於電路基板10之側表面10w之導通孔14在厚度方向上穿透電路基板10，因此來自電路基板10之整個側表面的電磁波洩漏得以抑制。
此外，在半導體裝置1中，導電屏蔽層40與接地電位接觸之位置以複數形式提供，且位置之間的距離經調整為不大於自半導體元件20等發射之電磁雜訊之波長的一半。因此，可藉由導電屏蔽層40更加確定地屏蔽電磁雜訊。
在導電屏蔽層40與接地電位接觸之位置的數目僅為一的情況下，雜訊可容易地自電路基板10與導電屏蔽層40之間洩漏。舉例而言，當半導體元件20自某一位置發射雜訊時，在該某一位置與導電屏蔽層40與接地電位接觸之位置彼此遠離之情況下，雜訊可容易地自電路基板10與導電屏蔽層40之間洩漏。
相比而言，在半導體裝置1中，導電屏蔽層40與接地電位接觸之位置以複數形式提供，且導電屏蔽層40經均勻地設定成接地電位。因此，可藉由導電屏蔽層40更加確定地 屏蔽電磁雜訊。
第二實施例
圖6為根據第二實施例之半導體裝置之示意橫截面圖。
半導體裝置2之基本結構與半導體裝置1之基本結構相同。然而，在根據第二實施例之電路基板10中，提供於電路基板10之側表面10w之導通孔14未曝露於電路基板10之側表面10w。在根據第二實施例之電路基板10中，提供於電路基板10之側表面10w附近之導通孔14g上的互連層14m曝露於電路基板10之側表面10w。互連層14m由與導通孔14g相同之材料製成。將連接至導通孔14g之平台形狀之互連層14m連接至導電屏蔽層40。互連層14m電性連接至變成接地電位之外部連接端子端子17g(或與外部連接端子端子17g接觸之第二互連層13)。
換言之，將外部連接端子端子17g(或與外部連接端子端子17g接觸之第二互連層13)中之每一者電性連接至處於側表面10w之互連件14m；因此，導電屏蔽層40可變成接地電位。在半導體裝置2中，導電屏蔽層40與接地電位之間的觸點經由互連層14m以複數形式提供。同樣，因此而組態之半導體裝置2提供與半導體裝置1類似之效應。
第三實施例
圖7A及7B分別為根據第三實施例之半導體裝置之示意平面圖及用於描述屏蔽效應之圖表。圖7A展示半導體裝置之電路基板之示意平面圖，且圖7B展示用於描述屏蔽效應之圖表。
圖7A說明電路基板10之下表面側之平面圖。
在根據第三實施例之電路基板10中，作為第二互連層之呈環形形狀之互連層19r提供於經垂直且水平地配置之外部連接端子17g(或與外部連接端子17g接觸之第二互連層13)的外周邊。亦即，電路基板10進一步包括呈環形形狀之互連層19r，互連層19r環繞提供於絕緣層11之下表面側上的外部連接端子17g(或與外部連接端子17g接觸之第二互連層13)。互連層19r電性連接至外部連接端子17g(或與外部連接端子17g接觸之第二互連層13)中之任一者。
舉例而言，當外部連接端子17g變成接地電位時，所有互連層19r及導通孔14g變成接地電位。
外部連接端子17g及互連層19r在以窄於電磁雜訊之波長的一半的間距電性連接時生效；且連接之間距愈窄，屏蔽效應愈高。此外，互連層19r及導通孔14g在以窄於電磁雜訊之波長的一半的間距電性連接時生效；且連接之間距愈窄，屏蔽效應愈高。環形形狀之互連層19r在具有0.035 mm或更寬之線寬時生效，且加寬寬度至大約0.5 mm提供對電磁波之較高屏蔽效應。
圖7B展示在以下情況下之屏蔽效應：外部連接端子17g與互連層19r之間的間距經設定成1.6 mm或更少，互連層19r與導通孔14g之間的間距經設定成0.4 mm，且互連層19r之線寬經設定成0.5 mm。水平軸表示自半導體元件20等發射之雜訊頻率(MHz)，且垂直軸表示屏蔽效應(dB)。
與第一實施例及第二實施例相比，根據第三實施例之電 路基板有高磁場屏蔽效應。
第四實施例
圖8為根據第四實施例之半導體裝置之示意橫截面圖。
根據第四實施例之半導體裝置3包括電路基板10。電路基板10包括：絕緣層11；形成第一互連層之複數個互連件12，第一互連層提供於絕緣層11之上表面側上；及形成第二互連層之複數個互連件13，第二互連層提供於絕緣層11之下表面側上。半導體裝置3進一步包括：半導體元件20，半導體元件20安裝於電路基板10之上表面側上；密封樹脂層30，密封樹脂層30密封半導體元件20且提供於電路基板10之上表面上；及導電屏蔽層40，導電屏蔽層40覆蓋密封樹脂層30及電路基板10之末端部分之部分。
在半導體裝置3中，形成第二互連層之複數個互連件50以複數形式提供於電路基板10之下側面上，複數個互連件50不同於形成第一互連層之複數個互連件12及形成第二互連層之複數個互連件13。形成第二互連層之複數個互連件50未電性連接至導電屏蔽層40，且提供於絕緣層11之下表面側上之區域中，在此區域中未提供形成第二互連層之複數個互連件13。當鎳(Ni)、金(Au)及/或其類似者之電解電鍍處理在第一互連層12及電路基板10之上表面側上的延長線18上執行時，形成第二互連層之複數個互連件50起(例如)用於電鍍之互連件的作用。因此，第二互連層之互連件50電性連接至形成第一互連層之複數個互連件12中之任一者。
藉由將因此而組態之第二互連層之互連件50拉伸至電路基板10之下側面周圍，電路基板10之上表面側之互連件設計的容許裕量得以增加。此外，因形成第二互連層之複數個互連件50提供於電路基板10之下側上，因此形成第二互連層之複數個互連件50不與導電屏蔽層40接觸(不以電氣連續性連接)。因此，即使在第一互連層12及延長線18上執行電鍍處理後存在第二互連層之互連件50，第二互連層之互連件50仍不與導電屏蔽層40接觸。亦即，第二互連層之互連件50不需要藉由蝕刻製程來移除，且並未造成製造程序之成本增加。將複數個互連件50拉伸至電路基板10之末端以便曝露於側表面10w。
如圖式中所展示，亦在半導體裝置3中展示自絕緣層11之上表面穿透至下表面之複數個導通孔14進一步提供於電路基板10中，且由複數個導通孔組成之第一群(其數目小於複數個導通孔14)可曝露於電路基板10之側表面10w。在此情況下，第一群之導通孔14之曝露表面中的每一者與導電屏蔽層連接。曝露於側表面10w之導通孔14中之一些形成變成接地電位之導通孔14g。
必要時可完全地移除在第一至第四實施例中所描述之外部連接端子17(17g)；且同樣地，LGA(平台柵格陣列)結構之半導體裝置1至3包括於實施例中，在半導體裝置1至3中，形成第二互連層之複數個互連件13中之每一者曝露於電路基板10之下表面側上。
此外，必要時可移除安置於電路基板10之側表面10w之 複數個導通孔14中未電性連接至外部連接端子17g的彼等導通孔。此組態亦包括於實施例中。
在上文參考特定實例描述實施例。然而，實施例不限於此等特定實例。亦即，熟習此項技術者可適當地對此等特定實例進行設計修改，且此等修改亦包括於實施例之範疇內以達到包括實施例之精神的程度。上文所描述之特定實例之組件及其配置、材料、條件、形狀、大小等不限於所說明之彼等內容，但可適當地變更。
另外，熟習該項技術者可達成不超出實施例之理念的各種更改及修改。此等更改及修改亦應被視為不超出實施例之範疇。而且，實施例之組件可組合於技術可行性之範圍內，且組件之組合亦包括於實施例之範疇中以達到包括實施例之精神的程度。
雖然已描述某些實施例，但此等實施例僅以實例之方式呈現，且不欲限制本發明之範疇。實際上，本文中描述之新穎實施例可體現為各種其他形式；另外，在不脫離本發明之精神的情況下，可進行對本文中描述之實施例之各種省略、替換及形式的改變。附加申請專利範圍及其均等物意欲涵蓋屬於本發明之範疇及精神內的此等形式或修改。
1‧‧‧半導體裝置
2‧‧‧半導體裝置
3‧‧‧半導體裝置
10‧‧‧電路基板
10w‧‧‧側表面
11‧‧‧絕緣層
12‧‧‧互連件
13‧‧‧互連件
14‧‧‧導通孔
14g‧‧‧導通孔
14m‧‧‧互連層
15‧‧‧阻焊層
16‧‧‧阻焊層
17‧‧‧外部連接端子
17g‧‧‧外部連接端子
18‧‧‧延長線
19‧‧‧延長線
19r‧‧‧互連層
20‧‧‧半導體元件
21‧‧‧電線
22‧‧‧晶粒結著材料
23‧‧‧元件安裝區域
30‧‧‧密封樹脂層
40‧‧‧導電屏蔽層
50‧‧‧互連件
90‧‧‧切割刀片
90h‧‧‧凹座
100‧‧‧安裝基板
101‧‧‧互連層
圖1為用於描述根據第一實施例之半導體裝置之概覽的示意橫截面圖；圖2A及2B為根據第一實施例之半導體裝置之示意平面圖； 圖3A及3B為根據第一實施例之半導體裝置之示意平面圖；圖4A至4D為用於描述根據第一實施例之半導體裝置之製造程序的示意橫截面圖；圖5A及5B(1)至(4)為用於描述對電磁雜訊之屏蔽效應之模擬結果；圖6為根據第二實施例之半導體裝置之示意橫截面圖；圖7A及7B分別為根據第三實施例之半導體裝置之示意平面圖及用於描述屏蔽效應之圖表；圖8為根據第四實施例之半導體裝置之示意橫截面圖。
1‧‧‧半導體裝置
10‧‧‧電路基板
10w‧‧‧側表面
11‧‧‧絕緣層
12‧‧‧互連件
13‧‧‧互連件
14‧‧‧導通孔
15‧‧‧阻焊層
16‧‧‧阻焊層
17‧‧‧外部連接端子
19‧‧‧延長線
20‧‧‧半導體元件
21‧‧‧電線
22‧‧‧晶粒結著材料
30‧‧‧密封樹脂層
40‧‧‧導電屏蔽層
100‧‧‧安裝基板
101‧‧‧互連層

Claims (17)

  1. 一種半導體裝置，其包含：一電路基板，該電路基板包括：一絕緣層；形成第一互連層之複數個互連件，該等第一互連層係提供於該絕緣層之一上表面側上；形成第二互連層之複數個互連件，該等第二互連層係提供於該絕緣層之一下表面側上；及複數個導通孔(via)，該等導通孔自該絕緣層之該上表面穿透至該下表面；一半導體元件，其安裝於該電路基板之該上表面側上；一密封樹脂層，其提供於該電路基板之該上表面上且密封該半導體元件；及一導電屏蔽層，其覆蓋該密封樹脂層及該電路基板之一末端部分之部分；且該複數個導通孔中之任一者與該導電屏蔽層電性連接；形成該等第二互連層之該複數個互連件中之任一者電性連接至能變成一接地電位的外部連接端子之各者，相鄰之上述外部連接端子之間的距離係經調整為不大於自該半導體元件發射之電磁雜訊之波長的一半。
  2. 如請求項1之裝置，其中該複數個導通孔中之每一者曝露於該電路基板之一側表面，且曝露於該側表面之該複數個導通孔中之每一者與該導電屏蔽層連接。
  3. 如請求項1之裝置，其中當自垂直於該絕緣層之該上表 面之方向查看時，能夠變成一接地電位之該等第二互連層中之每一者係定位於該半導體元件之一轉角處。
  4. 如請求項1之裝置，其中當自垂直於該絕緣層之該上表面之方向查看時，能夠變成一接地電位之該等第二互連層中之每一者係定位於該半導體元件之相鄰轉角之間。
  5. 如請求項1之裝置，其中該電路基板進一步包括呈一平台形狀之一互連層，該互連層係提供於該電路基板之一側表面附近且曝露於該電路基板之一側表面；該複數個導通孔中之任一者電性連接至呈一平台形狀之該互連層；且呈一平台形狀之該互連層連接至該導電屏蔽層。
  6. 如請求項1之裝置，其中該電路基板進一步包括呈一環形形狀之一互連層，該互連層係提供於該絕緣層之一下表面側上，環繞該第二互連層且電性連接至該複數個導通孔中之任一者。
  7. 如請求項1之裝置，其中該導電屏蔽層含有銀(Ag)、銅(Cu)、鎳(Ni)及鋁(Al)中之至少一者。
  8. 一種半導體裝置，其包含：一電路基板，該電路基板包括：一絕緣層；形成第一互連層之複數個互連件，該等第一互連層係提供於該絕緣層之一上表面側上；及形成第二互連層之複數個互連件，該等第二互連層係提供於該絕緣層之一下表面側上； 一半導體元件，其安裝於該電路基板之該上表面側上；一密封樹脂層，其提供於該電路基板之該上表面上且密封該半導體元件；及一導電屏蔽層，其覆蓋該密封樹脂層及該電路基板之一末端部分之部分；且形成該等第二互連層之該複數個互連件不與該導電屏蔽層接觸，電性連接至形成該等第一互連層之該複數個互連件中之任一者，且拉伸至該電路基板之一末端以便曝露於該電路基板之一側表面。
  9. 如請求項8之裝置，其中該電路基板進一步包括：形成其他第二互連層之複數個互連件，該複數個互連件不同於形成提供於該絕緣層之一下表面側上之該等第二互連層之該複數個互連件；及複數個導通孔，其自該絕緣層之該上表面穿透至該下表面；且該複數個導通孔中之任一者與該導電屏蔽層電性連接；形成該等其他第二互連層之該複數個互連件中之任一者可變成一接地電位；能夠變成一接地電位之形成該等其他第二互連層之該複數個互連件中的任一者電性連接至該複數個導通孔中之任一者。
  10. 如請求項9之裝置，其中該複數個導通孔中之每一者曝露於該電路基板之一側表面處，且曝露於該側表面之該複數個導通孔中之每一者與該導電屏蔽層連接。
  11. 如請求項9之裝置，其中當自垂直於該絕緣層之該上表面之方向查看時，能夠變成一接地電位之該等其他第二互連層中之每一者係定位於該半導體元件之一轉角處。
  12. 如請求項9之裝置，其中當自垂直於該絕緣層之該上表面之方向查看時，能夠變成一接地電位之該等其他第二互連層中之每一者係定位於該半導體元件之相鄰轉角之間。
  13. 如請求項9之裝置，其中該第一互連層含有銀(Ag)及銅(Cu)中之至少一者。
  14. 如請求項9之裝置，其中該第一互連層之一表面部分地鍍有鎳(Ni)及金(Au)中之至少一者。
  15. 如請求項9之裝置，其中該第二互連層含有銀(Ag)及銅(Cu)中之至少一者。
  16. 如請求項9之裝置，其中該第二互連層之一表面部分地鍍有鎳(Ni)及金(Au)中之至少一者。
  17. 如請求項9之裝置，其中該導電屏蔽層含有銀(Ag)、銅(Cu)、鎳(Ni)及鋁(Al)中之至少一者。
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